1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 if !TFABOOT 5 select FSL_LAYERSCAPE 6 select FSL_LSCH2 7 select GICV2 8 select SKIP_LOWLEVEL_INIT 9 select SYS_FSL_SRDS_1 10 select SYS_HAS_SERDES 11 select SYS_FSL_DDR_BE 12 select SYS_FSL_MMDC 13 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE 14 select SYS_FSL_ERRATUM_A009798 15 select SYS_FSL_ERRATUM_A008997 16 select SYS_FSL_ERRATUM_A009007 17 select SYS_FSL_ERRATUM_A009008 18 select ARCH_EARLY_INIT_R 19 select BOARD_EARLY_INIT_F 20 select SYS_I2C_MXC 21 select SYS_I2C_MXC_I2C1 if !DM_I2C 22 select SYS_I2C_MXC_I2C2 if !DM_I2C 23 imply PANIC_HANG 24 imply TIMESTAMP 25 26config ARCH_LS1028A 27 bool 28 select ARMV8_SET_SMPEN 29 select ESBC_HDR_LS if CHAIN_OF_TRUST 30 select FSL_LAYERSCAPE 31 select FSL_LSCH3 32 select FSL_TZASC_400 33 select GICV3 34 select NXP_LSCH3_2 35 select SYS_FSL_HAS_CCI400 36 select SYS_FSL_SRDS_1 37 select SYS_HAS_SERDES 38 select SYS_FSL_DDR 39 select SYS_FSL_DDR_LE 40 select SYS_FSL_DDR_VER_50 41 select SYS_FSL_HAS_DDR3 42 select SYS_FSL_HAS_DDR4 43 select SYS_FSL_HAS_SEC 44 select SYS_FSL_SEC_COMPAT_5 45 select SYS_FSL_SEC_LE 46 select FSL_TZASC_1 47 select FSL_TZPC_BP147 48 select ARCH_EARLY_INIT_R 49 select BOARD_EARLY_INIT_F 50 select SYS_I2C_MXC 51 select SYS_FSL_ERRATUM_A008997 52 select SYS_FSL_ERRATUM_A009007 53 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 54 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 55 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 56 select SYS_FSL_ERRATUM_A050382 57 select SYS_FSL_ERRATUM_A011334 58 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 59 select RESV_RAM if GIC_V3_ITS 60 select SYS_HAS_ARMV8_SECURE_BASE 61 imply PANIC_HANG 62 63config ARCH_LS1043A 64 bool 65 select ARMV8_SET_SMPEN 66 select ARM_ERRATA_855873 if !TFABOOT 67 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT) 68 select FSL_LAYERSCAPE 69 select FSL_LSCH2 70 select GICV2 71 select HAS_FSL_XHCI_USB if USB_HOST 72 select SKIP_LOWLEVEL_INIT 73 select SYS_DPAA_FMAN 74 select SYS_FSL_SRDS_1 75 select SYS_HAS_SERDES 76 select SYS_FSL_DDR 77 select SYS_FSL_DDR_BE 78 select SYS_FSL_DDR_VER_50 79 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 80 select SYS_FSL_ERRATUM_A008997 if USB 81 select SYS_FSL_ERRATUM_A009008 if USB 82 select SYS_FSL_ERRATUM_A009660 if !TFABOOT 83 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 84 select SYS_FSL_ERRATUM_A009798 if USB 85 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 86 select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE 87 select SYS_FSL_ERRATUM_A010539 88 select SYS_FSL_HAS_DDR3 89 select SYS_FSL_HAS_DDR4 90 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 91 select ARCH_EARLY_INIT_R 92 select BOARD_EARLY_INIT_F 93 select SYS_I2C_MXC 94 select SYS_I2C_MXC_I2C1 if !DM_I2C 95 select SYS_I2C_MXC_I2C2 if !DM_I2C 96 select SYS_I2C_MXC_I2C3 if !DM_I2C 97 select SYS_I2C_MXC_I2C4 if !DM_I2C 98 select SYS_HAS_ARMV8_SECURE_BASE 99 imply CMD_PCI 100 imply ID_EEPROM 101 102config ARCH_LS1046A 103 bool 104 select ARMV8_SET_SMPEN 105 select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT) 106 select FSL_LAYERSCAPE 107 select FSL_LSCH2 108 select GICV2 109 select HAS_FSL_XHCI_USB if USB_HOST 110 select SKIP_LOWLEVEL_INIT 111 select SYS_DPAA_FMAN 112 select SYS_FSL_SRDS_1 113 select SYS_HAS_SERDES 114 select SYS_FSL_DDR 115 select SYS_FSL_DDR_BE 116 select SYS_FSL_DDR_VER_50 117 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 118 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 119 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 120 select SYS_FSL_ERRATUM_A008997 121 select SYS_FSL_ERRATUM_A009008 122 select SYS_FSL_ERRATUM_A009798 123 select SYS_FSL_ERRATUM_A009801 124 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 125 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 126 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 127 select SYS_FSL_ERRATUM_A010539 128 select SYS_FSL_HAS_DDR4 129 select SYS_FSL_SRDS_2 130 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 131 select ARCH_EARLY_INIT_R 132 select BOARD_EARLY_INIT_F 133 select SYS_I2C_MXC 134 select SYS_I2C_MXC_I2C1 if !DM_I2C 135 select SYS_I2C_MXC_I2C2 if !DM_I2C 136 select SYS_I2C_MXC_I2C3 if !DM_I2C 137 select SYS_I2C_MXC_I2C4 if !DM_I2C 138 imply ID_EEPROM 139 imply SCSI 140 imply SCSI_AHCI 141 imply SPL_SYS_I2C_LEGACY 142 143config ARCH_LS1088A 144 bool 145 select ARMV8_SET_SMPEN 146 select ARM_ERRATA_855873 if !TFABOOT 147 select ESBC_HDR_LS if CHAIN_OF_TRUST 148 select FSL_IFC 149 select FSL_LAYERSCAPE 150 select FSL_LSCH3 151 select GICV3 152 select SKIP_LOWLEVEL_INIT 153 select SYS_FSL_SRDS_1 154 select SYS_HAS_SERDES 155 select SYS_FSL_DDR 156 select SYS_FSL_DDR_LE 157 select SYS_FSL_DDR_VER_50 158 select SYS_FSL_EC1 159 select SYS_FSL_EC2 160 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 161 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 162 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 163 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 164 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 165 select SYS_FSL_ERRATUM_A009007 166 select SYS_FSL_HAS_CCI400 167 select SYS_FSL_HAS_DDR4 168 select SYS_FSL_HAS_RGMII 169 select SYS_FSL_HAS_SEC 170 select SYS_FSL_SEC_COMPAT_5 171 select SYS_FSL_SEC_LE 172 select SYS_FSL_SRDS_1 173 select SYS_FSL_SRDS_2 174 select FSL_TZASC_1 175 select FSL_TZASC_400 176 select FSL_TZPC_BP147 177 select ARCH_EARLY_INIT_R 178 select BOARD_EARLY_INIT_F 179 select SYS_I2C_MXC 180 select SYS_I2C_MXC_I2C1 if !TFABOOT 181 select SYS_I2C_MXC_I2C2 if !TFABOOT 182 select SYS_I2C_MXC_I2C3 if !TFABOOT 183 select SYS_I2C_MXC_I2C4 if !TFABOOT 184 select RESV_RAM if GIC_V3_ITS 185 imply ID_EEPROM 186 imply SCSI 187 imply SPL_SYS_I2C_LEGACY 188 imply PANIC_HANG 189 190config ARCH_LS2080A 191 bool 192 select ARMV8_SET_SMPEN 193 select ARM_ERRATA_826974 194 select ARM_ERRATA_828024 195 select ARM_ERRATA_829520 196 select ARM_ERRATA_833471 197 select ESBC_HDR_LS if CHAIN_OF_TRUST 198 select FSL_IFC 199 select FSL_LAYERSCAPE 200 select FSL_LSCH3 201 select SYS_FSL_OTHER_DDR_NUM_CTRLS 202 select GICV3 203 select SKIP_LOWLEVEL_INIT 204 select SYS_FSL_SRDS_1 205 select SYS_HAS_SERDES 206 select SYS_FSL_DDR 207 select SYS_FSL_DDR_LE 208 select SYS_FSL_DDR_VER_50 209 select SYS_FSL_HAS_CCN504 210 select SYS_FSL_HAS_DP_DDR 211 select SYS_FSL_HAS_SEC 212 select SYS_FSL_HAS_DDR4 213 select SYS_FSL_SEC_COMPAT_5 214 select SYS_FSL_SEC_LE 215 select SYS_FSL_SRDS_2 216 select FSL_TZASC_1 217 select FSL_TZASC_2 218 select FSL_TZASC_400 219 select FSL_TZPC_BP147 220 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 221 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 222 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 223 select SYS_FSL_ERRATUM_A008585 224 select SYS_FSL_ERRATUM_A008997 225 select SYS_FSL_ERRATUM_A009007 226 select SYS_FSL_ERRATUM_A009008 227 select SYS_FSL_ERRATUM_A009635 228 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 229 select SYS_FSL_ERRATUM_A009798 230 select SYS_FSL_ERRATUM_A009801 231 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 232 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 233 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 234 select SYS_FSL_ERRATUM_A009203 235 select ARCH_EARLY_INIT_R 236 select BOARD_EARLY_INIT_F 237 select SYS_I2C_MXC 238 select SYS_I2C_MXC_I2C1 if !TFABOOT 239 select SYS_I2C_MXC_I2C2 if !TFABOOT 240 select SYS_I2C_MXC_I2C3 if !TFABOOT 241 select SYS_I2C_MXC_I2C4 if !TFABOOT 242 select RESV_RAM if GIC_V3_ITS 243 imply DISTRO_DEFAULTS 244 imply ID_EEPROM 245 imply PANIC_HANG 246 imply SPL_SYS_I2C_LEGACY 247 248config ARCH_LX2162A 249 bool 250 select ARMV8_SET_SMPEN 251 select ESBC_HDR_LS if CHAIN_OF_TRUST 252 select FSL_DDR_BIST 253 select FSL_DDR_INTERACTIVE 254 select FSL_LAYERSCAPE 255 select FSL_LSCH3 256 select FSL_TZPC_BP147 257 select GICV3 258 select NXP_LSCH3_2 259 select SYS_HAS_SERDES 260 select SYS_FSL_SRDS_1 261 select SYS_FSL_SRDS_2 262 select SYS_FSL_DDR 263 select SYS_FSL_DDR_LE 264 select SYS_FSL_DDR_VER_50 265 select SYS_FSL_EC1 266 select SYS_FSL_EC2 267 select SYS_FSL_ERRATUM_A050204 268 select SYS_FSL_ERRATUM_A011334 269 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 270 select SYS_FSL_HAS_RGMII 271 select SYS_FSL_HAS_SEC 272 select SYS_FSL_HAS_CCN508 273 select SYS_FSL_HAS_DDR4 274 select SYS_FSL_SEC_COMPAT_5 275 select SYS_FSL_SEC_LE 276 select SYS_PCI_64BIT if PCI 277 select ARCH_EARLY_INIT_R 278 select BOARD_EARLY_INIT_F 279 select SYS_I2C_MXC 280 select RESV_RAM if GIC_V3_ITS 281 imply DISTRO_DEFAULTS 282 imply PANIC_HANG 283 imply SCSI 284 imply SCSI_AHCI 285 imply SPL_SYS_I2C_LEGACY 286 287config ARCH_LX2160A 288 bool 289 select ARMV8_SET_SMPEN 290 select ESBC_HDR_LS if CHAIN_OF_TRUST 291 select FSL_DDR_BIST 292 select FSL_DDR_INTERACTIVE 293 select FSL_LAYERSCAPE 294 select FSL_LSCH3 295 select FSL_TZPC_BP147 296 select GICV3 297 select HAS_FSL_XHCI_USB if USB_HOST 298 select NXP_LSCH3_2 299 select SYS_HAS_SERDES 300 select SYS_FSL_SRDS_1 301 select SYS_FSL_SRDS_2 302 select SYS_NXP_SRDS_3 303 select SYS_FSL_DDR 304 select SYS_FSL_DDR_LE 305 select SYS_FSL_DDR_VER_50 306 select SYS_FSL_EC1 307 select SYS_FSL_EC2 308 select SYS_FSL_ERRATUM_A050204 309 select SYS_FSL_ERRATUM_A011334 310 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 311 select SYS_FSL_HAS_RGMII 312 select SYS_FSL_HAS_SEC 313 select SYS_FSL_HAS_CCN508 314 select SYS_FSL_HAS_DDR4 315 select SYS_FSL_SEC_COMPAT_5 316 select SYS_FSL_SEC_LE 317 select SYS_PCI_64BIT if PCI 318 select ARCH_EARLY_INIT_R 319 select BOARD_EARLY_INIT_F 320 select SYS_I2C_MXC 321 select RESV_RAM if GIC_V3_ITS 322 imply DISTRO_DEFAULTS 323 imply ID_EEPROM 324 imply PANIC_HANG 325 imply SCSI 326 imply SCSI_AHCI 327 imply SPL_SYS_I2C_LEGACY 328 329config FSL_LSCH2 330 bool 331 select ARCH_MISC_INIT if FSL_CAAM 332 select SKIP_LOWLEVEL_INIT 333 select SYS_FSL_CCSR_GUR_BE 334 select SYS_FSL_CCSR_SCFG_BE 335 select SYS_FSL_ESDHC_BE 336 select SYS_FSL_IFC_BE 337 select SYS_FSL_PEX_LUT_BE 338 select SYS_FSL_HAS_CCI400 339 select SYS_FSL_HAS_SEC 340 select SYS_FSL_SEC_COMPAT_5 341 select SYS_FSL_SEC_BE 342 343config FSL_LSCH3 344 select ARCH_MISC_INIT 345 select SYS_FSL_CCSR_GUR_LE 346 select SYS_FSL_CCSR_SCFG_LE 347 select SYS_FSL_ESDHC_LE 348 select SYS_FSL_IFC_LE 349 select SYS_FSL_PEX_LUT_LE 350 bool 351 352config NXP_LSCH3_2 353 bool 354 355config SYS_FSL_CCSR_GUR_BE 356 bool 357 358config SYS_FSL_CCSR_SCFG_BE 359 bool 360 361config SYS_FSL_PEX_LUT_BE 362 bool 363 364config SYS_FSL_CCSR_GUR_LE 365 bool 366 367config SYS_FSL_CCSR_SCFG_LE 368 bool 369 370config SYS_FSL_ESDHC_LE 371 bool 372 373config SYS_FSL_IFC_LE 374 bool 375 376config SYS_FSL_PEX_LUT_LE 377 bool 378 379menu "Layerscape architecture" 380 depends on FSL_LSCH2 || FSL_LSCH3 381 382config FSL_LAYERSCAPE 383 bool 384 select ARM_SMCCC 385 386config HAS_FEATURE_GIC64K_ALIGN 387 bool 388 default y if ARCH_LS1043A 389 390config HAS_FEATURE_ENHANCED_MSI 391 bool 392 default y if ARCH_LS1043A 393 394config SYS_FSL_ERRATUM_A008997 395 bool "Workaround for USB PHY erratum A008997" 396 397config SYS_FSL_ERRATUM_A009007 398 bool 399 help 400 Workaround for USB PHY erratum A009007 401 402config SYS_FSL_ERRATUM_A009008 403 bool "Workaround for USB PHY erratum A009008" 404 405config SYS_FSL_ERRATUM_A009798 406 bool "Workaround for USB PHY erratum A009798" 407 408config SYS_FSL_ERRATUM_A050204 409 bool "Workaround for USB PHY erratum A050204" 410 help 411 USB3.0 Receiver needs to enable fixed equalization 412 for each of PHY instances in an SOC. This is similar 413 to erratum A-009007, but this one is for LX2160A and LX2162A, 414 and the register value is different. 415 416config SYS_FSL_ERRATUM_A010315 417 bool "Workaround for PCIe erratum A010315" 418 419config SYS_FSL_ERRATUM_A010539 420 bool "Workaround for PIN MUX erratum A010539" 421 422config MAX_CPUS 423 int "Maximum number of CPUs permitted for Layerscape" 424 default 2 if ARCH_LS1028A 425 default 4 if ARCH_LS1043A 426 default 4 if ARCH_LS1046A 427 default 16 if ARCH_LS2080A 428 default 8 if ARCH_LS1088A 429 default 16 if ARCH_LX2160A 430 default 16 if ARCH_LX2162A 431 default 1 432 help 433 Set this number to the maximum number of possible CPUs in the SoC. 434 SoCs may have multiple clusters with each cluster may have multiple 435 ports. If some ports are reserved but higher ports are used for 436 cores, count the reserved ports. This will allocate enough memory 437 in spin table to properly handle all cores. 438 439config EMC2305 440 bool "Fan controller" 441 help 442 Enable the EMC2305 fan controller for configuration of fan 443 speed. 444 445config QSPI_AHB_INIT 446 bool "Init the QSPI AHB bus" 447 help 448 The default setting for QSPI AHB bus just support 3bytes addressing. 449 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 450 bus for those flashes to support the full QSPI flash size. 451 452config FSPI_AHB_EN_4BYTE 453 bool "Enable 4-byte Fast Read command for AHB mode" 454 help 455 The default setting for FlexSPI AHB bus just supports 3-byte addressing. 456 But some FlexSPI flash sizes are up to 64MBytes. 457 This flag enables fast read command for AHB mode and modifies required 458 LUT to support full FlexSPI flash. 459 460config SYS_CCI400_OFFSET 461 hex "Offset for CCI400 base" 462 depends on SYS_FSL_HAS_CCI400 463 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A 464 default 0x180000 if FSL_LSCH2 465 help 466 Offset for CCI400 base 467 CCI400 base addr = CCSRBAR + CCI400_OFFSET 468 469config SYS_FSL_HAS_CCI400 470 bool 471 472config SYS_FSL_HAS_CCN504 473 bool 474 475config SYS_FSL_HAS_CCN508 476 bool 477 478config SYS_FSL_HAS_DP_DDR 479 bool 480 help 481 Defines the SoC has DP-DDR used for DPAA. 482 483config DP_DDR_CTRL 484 int 485 depends on SYS_FSL_HAS_DP_DDR 486 default 2 if ARCH_LS2080A 487 488config DP_DDR_DIMM_SLOTS_PER_CTLR 489 int 490 depends on SYS_FSL_HAS_DP_DDR 491 default 1 if ARCH_LS2080A 492 493config DP_DDR_NUM_CTRLS 494 int 495 depends on SYS_FSL_HAS_DP_DDR 496 default 1 if ARCH_LS2080A 497 498config SYS_DP_DDR_BASE 499 hex 500 depends on SYS_FSL_HAS_DP_DDR 501 default 0x6000000000 if ARCH_LS2080A 502 503config SYS_DP_DDR_BASE_PHY 504 int 505 depends on SYS_FSL_HAS_DP_DDR 506 default 0 if ARCH_LS2080A 507 help 508 DDR controller uses this value as the base address for binding. 509 It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 510 511config SYS_NXP_SRDS_3 512 bool 513 514config FSL_TZASC_1 515 bool 516 517config FSL_TZASC_2 518 bool 519 520config FSL_TZASC_400 521 bool 522 523config FSL_TZPC_BP147 524 bool 525endmenu 526 527menu "Layerscape clock tree configuration" 528 depends on FSL_LSCH2 || FSL_LSCH3 529 530config CLUSTER_CLK_FREQ 531 int "Reference clock of core cluster" 532 depends on ARCH_LS1012A 533 default 100000000 534 help 535 This number is the reference clock frequency of core PLL. 536 For most platforms, the core PLL and Platform PLL have the same 537 reference clock, but for some platforms, LS1012A for instance, 538 they are provided sepatately. 539 540config SYS_FSL_PCLK_DIV 541 int "Platform clock divider" 542 default 1 if ARCH_LS1028A 543 default 1 if ARCH_LS1043A 544 default 1 if ARCH_LS1046A 545 default 1 if ARCH_LS1088A 546 default 2 547 help 548 This is the divider that is used to derive Platform clock from 549 Platform PLL, in another word: 550 Platform_clk = Platform_PLL_freq / this_divider 551 552config SYS_FSL_DSPI_CLK_DIV 553 int "DSPI clock divider" 554 default 1 if ARCH_LS1043A 555 default 2 556 help 557 This is the divider that is used to derive DSPI clock from Platform 558 clock, in another word DSPI_clk = Platform_clk / this_divider. 559 560config SYS_FSL_DUART_CLK_DIV 561 int "DUART clock divider" 562 default 1 if ARCH_LS1043A 563 default 4 if ARCH_LX2160A 564 default 4 if ARCH_LX2162A 565 default 2 566 help 567 This is the divider that is used to derive DUART clock from Platform 568 clock, in another word DUART_clk = Platform_clk / this_divider. 569 570config SYS_FSL_I2C_CLK_DIV 571 int "I2C clock divider" 572 default 1 if ARCH_LS1043A 573 default 4 if ARCH_LS1012A 574 default 4 if ARCH_LS1028A 575 default 8 if ARCH_LX2160A 576 default 8 if ARCH_LX2162A 577 default 8 if ARCH_LS1088A 578 default 2 579 help 580 This is the divider that is used to derive I2C clock from Platform 581 clock, in another word I2C_clk = Platform_clk / this_divider. 582 583config SYS_FSL_IFC_CLK_DIV 584 int "IFC clock divider" 585 default 1 if ARCH_LS1043A 586 default 4 if ARCH_LS1012A 587 default 4 if ARCH_LS1028A 588 default 8 if ARCH_LX2160A 589 default 8 if ARCH_LX2162A 590 default 8 if ARCH_LS1088A 591 default 2 592 help 593 This is the divider that is used to derive IFC clock from Platform 594 clock, in another word IFC_clk = Platform_clk / this_divider. 595 596config SYS_FSL_LPUART_CLK_DIV 597 int "LPUART clock divider" 598 default 1 if ARCH_LS1043A 599 default 2 600 help 601 This is the divider that is used to derive LPUART clock from Platform 602 clock, in another word LPUART_clk = Platform_clk / this_divider. 603 604config SYS_FSL_SDHC_CLK_DIV 605 int "SDHC clock divider" 606 default 1 if ARCH_LS1043A 607 default 1 if ARCH_LS1012A 608 default 2 609 help 610 This is the divider that is used to derive SDHC clock from Platform 611 clock, in another word SDHC_clk = Platform_clk / this_divider. 612 613config SYS_FSL_QMAN_CLK_DIV 614 int "QMAN clock divider" 615 default 1 if ARCH_LS1043A 616 default 2 617 help 618 This is the divider that is used to derive QMAN clock from Platform 619 clock, in another word QMAN_clk = Platform_clk / this_divider. 620endmenu 621 622config RESV_RAM 623 bool 624 help 625 Reserve memory from the top, tracked by gd->arch.resv_ram. This 626 reserved RAM can be used by special driver that resides in memory 627 after U-Boot exits. It's up to implementation to allocate and allow 628 access to this reserved memory. For example, the reserved RAM can 629 be at the high end of physical memory. The reserve RAM may be 630 excluded from memory bank(s) passed to OS, or marked as reserved. 631 632config SYS_FSL_EC1 633 bool 634 help 635 Ethernet controller 1, this is connected to 636 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs 637 Provides DPAA2 capabilities 638 639config SYS_FSL_EC2 640 bool 641 help 642 Ethernet controller 2, this is connected to 643 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs 644 Provides DPAA2 capabilities 645 646config SYS_FSL_ERRATUM_A008336 647 bool 648 649config SYS_FSL_ERRATUM_A008514 650 bool 651 652config SYS_FSL_ERRATUM_A008585 653 bool 654 655config SYS_FSL_ERRATUM_A008850 656 bool 657 658config SYS_FSL_ERRATUM_A009203 659 bool 660 661config SYS_FSL_ERRATUM_A009635 662 bool 663 664config SYS_FSL_ERRATUM_A009660 665 bool 666 667config SYS_FSL_ERRATUM_A050382 668 bool 669 670config SYS_FSL_HAS_RGMII 671 bool 672 depends on SYS_FSL_EC1 || SYS_FSL_EC2 673 674config HAS_FSL_XHCI_USB 675 bool 676 help 677 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 678 pins, select it when the pins are assigned to USB. 679 680config SYS_FSL_BOOTROM_BASE 681 hex 682 depends on FSL_LSCH2 683 default 0x0 684 685config SYS_FSL_BOOTROM_SIZE 686 hex 687 depends on FSL_LSCH2 688 default 0x1000000 689