1menu "RISC-V architecture"
2	depends on RISCV
3
4config SYS_ARCH
5	default "riscv"
6
7choice
8	prompt "Target select"
9	optional
10
11config TARGET_ANDES_AE350
12	bool "Support Andes ae350"
13
14config TARGET_ANDES_VOYAGER
15	bool "Support Andes Voyager Board"
16
17config TARGET_BANANAPI_F3
18	bool "Support BananaPi F3 Board"
19
20config TARGET_K230_CANMV
21	bool "Support K230 CanMV Board"
22
23config TARGET_LICHEERV_NANO
24	bool "Support LicheeRV Nano Board"
25
26config TARGET_MICROCHIP_ICICLE
27	bool "Support Microchip PolarFire-SoC Icicle Board"
28
29config TARGET_MILKV_DUO
30	bool "Support Milk-v Duo Board"
31
32config TARGET_OPENPITON_RISCV64
33	bool "Support RISC-V cores on OpenPiton SoC"
34
35config TARGET_QEMU_VIRT
36	bool "Support QEMU Virt & RVVM Boards"
37	select BOARD_LATE_INIT
38
39config TARGET_SIFIVE_UNLEASHED
40	bool "Support SiFive Unleashed Board"
41
42config TARGET_SIFIVE_UNMATCHED
43	bool "Support SiFive Unmatched Board"
44	select SYS_CACHE_SHIFT_6
45
46config TARGET_SIPEED_MAIX
47	bool "Support Sipeed Maix Board"
48	select SYS_CACHE_SHIFT_6
49
50config TARGET_STARFIVE_VISIONFIVE2
51	bool "Support StarFive VisionFive2 Board"
52	select BOARD_LATE_INIT
53
54config TARGET_TH1520_LPI4A
55	bool "Support Sipeed's TH1520 Lichee PI 4A Board"
56	select SYS_CACHE_SHIFT_6
57
58config TARGET_XILINX_MBV
59	bool "Support AMD/Xilinx MicroBlaze V"
60
61config TARGET_ASPEED_AST2700_IBEX
62	bool "Support Ibex RISC-V cores on Aspeed AST2700 SoC"
63
64endchoice
65
66config SYS_ICACHE_OFF
67	bool "Do not enable icache"
68	help
69	  Do not enable instruction cache in U-Boot.
70
71config SPL_SYS_ICACHE_OFF
72	bool "Do not enable icache in SPL"
73	depends on SPL
74	default SYS_ICACHE_OFF
75	help
76	  Do not enable instruction cache in SPL.
77
78config SYS_DCACHE_OFF
79	bool "Do not enable dcache"
80	help
81	  Do not enable data cache in U-Boot.
82
83config SYS_CACHE_THEAD_CMO
84	bool "THEAD non-standard cache operations"
85	depends on !SYS_DCACHE_OFF
86	default n
87	help
88	  Support for non-standard cache management operations on SoCs based on
89	  T-Head C906/C910 cores.
90
91config SPL_SYS_DCACHE_OFF
92	bool "Do not enable dcache in SPL"
93	depends on SPL
94	default SYS_DCACHE_OFF
95	help
96	  Do not enable data cache in SPL.
97
98config SPL_ZERO_MEM_BEFORE_USE
99	bool "Zero memory before use"
100	depends on SPL
101	help
102	  Zero stack/GD/malloc area in SPL before using them, this is needed for
103	  Sifive core devices that uses L2 cache to store SPL.
104
105# board-specific options below
106source "board/andestech/ae350/Kconfig"
107source "board/andestech/voyager/Kconfig"
108source "board/aspeed/ibex_ast2700/Kconfig"
109source "board/canaan/k230_canmv/Kconfig"
110source "board/emulation/qemu-riscv/Kconfig"
111source "board/microchip/mpfs_icicle/Kconfig"
112source "board/openpiton/riscv64/Kconfig"
113source "board/sifive/unleashed/Kconfig"
114source "board/sifive/unmatched/Kconfig"
115source "board/sipeed/maix/Kconfig"
116source "board/sophgo/milkv_duo/Kconfig"
117source "board/sophgo/licheerv_nano/Kconfig"
118source "board/spacemit/bananapi-f3/Kconfig"
119source "board/starfive/visionfive2/Kconfig"
120source "board/thead/th1520_lpi4a/Kconfig"
121source "board/xilinx/mbv/Kconfig"
122
123# platform-specific options below
124source "arch/riscv/cpu/andes/Kconfig"
125source "arch/riscv/cpu/cv1800b/Kconfig"
126source "arch/riscv/cpu/fu540/Kconfig"
127source "arch/riscv/cpu/fu740/Kconfig"
128source "arch/riscv/cpu/ast2700/Kconfig"
129source "arch/riscv/cpu/generic/Kconfig"
130source "arch/riscv/cpu/jh7110/Kconfig"
131source "arch/riscv/cpu/k1/Kconfig"
132source "arch/riscv/cpu/k230/Kconfig"
133source "arch/riscv/cpu/th1520/Kconfig"
134
135# architecture-specific options below
136
137choice
138	prompt "Base ISA"
139	default ARCH_RV32I
140
141config ARCH_RV32I
142	bool "RV32I"
143	select 32BIT
144	help
145	  Choose this option to target the RV32I base integer instruction set.
146
147config ARCH_RV64I
148	bool "RV64I"
149	select 64BIT
150	select SPL_64BIT if SPL
151	select PHYS_64BIT
152	help
153	  Choose this option to target the RV64I base integer instruction set.
154
155endchoice
156
157config FRAMEPOINTER
158	bool "Build with frame pointer for stack unwinding"
159	help
160	  Choose this option to use the frame pointer so the stack can be
161	  unwound if needed. This is useful for tracing where faults came
162	  from as the source may be several functions back
163
164	  If you say Y here, then the code size will be increased due to
165	  having to store the fp.
166
167config SPL_FRAMEPOINTER
168	bool "Build SPL with frame pointer for stack unwinding"
169	depends on SPL
170	help
171	  Choose this option to use the frame pointer so the stack can be
172	  unwound if needed. This is useful for tracing where faults came
173	  from as the source may be several functions back
174
175	  If you say Y here, then the code size will be increased due to
176	  having to store the fp.
177
178choice
179	prompt "Code Model"
180	default CMODEL_MEDLOW
181
182config CMODEL_MEDLOW
183	bool "medium low code model"
184	help
185	  U-Boot and its statically defined symbols must lie within a single 2 GiB
186	  address range and must lie between absolute addresses -2 GiB and +2 GiB.
187
188config CMODEL_MEDANY
189	bool "medium any code model"
190	help
191	  U-Boot and its statically defined symbols must be within any single 2 GiB
192	  address range.
193
194endchoice
195
196choice
197	prompt "Run Mode"
198	default RISCV_MMODE
199
200config RISCV_MMODE
201	bool "Machine"
202	help
203	  Choose this option to build U-Boot for RISC-V M-Mode.
204
205config RISCV_SMODE
206	bool "Supervisor"
207	imply DEBUG_UART
208	help
209	  Choose this option to build U-Boot for RISC-V S-Mode.
210
211endchoice
212
213choice
214	prompt "SPL Run Mode"
215	default SPL_RISCV_MMODE
216	depends on SPL
217
218config SPL_RISCV_MMODE
219	bool "Machine"
220	help
221	  Choose this option to build U-Boot SPL for RISC-V M-Mode.
222
223config SPL_RISCV_SMODE
224	bool "Supervisor"
225	help
226	  Choose this option to build U-Boot SPL for RISC-V S-Mode.
227
228endchoice
229
230config RISCV_ISA_C
231	bool "Emit compressed instructions"
232	default y
233	help
234	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
235	  when building U-Boot, which results in compressed instructions in the
236	  U-Boot binary.
237
238config RISCV_ISA_F
239	bool "Standard extension for Single-Precision Floating Point"
240	default y
241	help
242	  Adds "F" to the ISA string passed to the compiler.
243
244config RISCV_ISA_D
245	bool "Standard extension for Double-Precision Floating Point"
246	depends on RISCV_ISA_F
247	default y
248	help
249	  Adds "D" to the ISA string passed to the compiler and changes the
250	  riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
251	  lp64d.
252
253config RISCV_ISA_ZBB
254	bool "Zbb extension support for bit manipulation instructions"
255	help
256	  Adds ZBB extension (basic bit manipulation) to the ISA subsets
257	  that the toolchain is allowed to emit when building U-Boot.
258	  The Zbb extension provides instructions to accelerate a number
259	  of bit-specific operations (count bit population, sign extending,
260	  bitrotation, etc) and enables optimized string routines.
261
262menu "Use assembly optimized implementation of string routines"
263
264config USE_ARCH_STRLEN
265	bool "Use an assembly optimized implementation of strlen"
266	default y
267	depends on RISCV_ISA_ZBB
268	help
269	  Enable the generation of an optimized version of strlen using
270	  Zbb extension.
271
272config SPL_USE_ARCH_STRLEN
273	bool "Use an assembly optimized implementation of strlen for SPL"
274	default y if USE_ARCH_STRLEN
275	depends on RISCV_ISA_ZBB
276	depends on SPL
277	help
278	  Enable the generation of an optimized version of strlen using
279	  Zbb extension.
280
281config TPL_USE_ARCH_STRLEN
282	bool "Use an assembly optimized implementation of strlen for TPL"
283	default y if USE_ARCH_STRLEN
284	depends on RISCV_ISA_ZBB
285	depends on TPL
286	help
287	  Enable the generation of an optimized version of strlen using
288	  Zbb extension.
289
290config USE_ARCH_STRCMP
291	bool "Use an assembly optimized implementation of strcmp"
292	default y
293	depends on RISCV_ISA_ZBB
294	help
295	  Enable the generation of an optimized version of strcmp using
296	  Zbb extension.
297
298config SPL_USE_ARCH_STRCMP
299	bool "Use an assembly optimized implementation of strcmp for SPL"
300	default y if USE_ARCH_STRCMP
301	depends on RISCV_ISA_ZBB
302	depends on SPL
303	help
304	  Enable the generation of an optimized version of strcmp using
305	  Zbb extension.
306
307config TPL_USE_ARCH_STRCMP
308	bool "Use an assembly optimized implementation of strcmp for TPL"
309	default y if USE_ARCH_STRCMP
310	depends on RISCV_ISA_ZBB
311	depends on TPL
312	help
313	  Enable the generation of an optimized version of strcmp using
314	  Zbb extension.
315
316config USE_ARCH_STRNCMP
317	bool "Use an assembly optimized implementation of strncmp"
318	default y
319	depends on RISCV_ISA_ZBB
320	help
321	  Enable the generation of an optimized version of strncmp using
322	  Zbb extension.
323
324config SPL_USE_ARCH_STRNCMP
325	bool "Use an assembly optimized implementation of strncmp for SPL"
326	default y if USE_ARCH_STRNCMP
327	depends on RISCV_ISA_ZBB
328	depends on SPL
329	help
330	  Enable the generation of an optimized version of strncmp using
331	  Zbb extension.
332
333config TPL_USE_ARCH_STRNCMP
334	bool "Use an assembly optimized implementation of strncmp for TPL"
335	default y if USE_ARCH_STRNCMP
336	depends on RISCV_ISA_ZBB
337	depends on TPL
338	help
339	  Enable the generation of an optimized version of strncmp using
340	  Zbb extension.
341
342endmenu
343
344config RISCV_ISA_A
345	bool "Standard extension for Atomic Instructions"
346	default y
347	help
348	  Adds "A" to the ISA string passed to the compiler.
349
350config RISCV_ISA_ZICBOM
351	bool "Zicbom support"
352	depends on !SYS_DISABLE_DCACHE_OPS
353
354config DMA_ADDR_T_64BIT
355	bool
356	default y if 64BIT
357
358config RISCV_ACLINT
359	bool
360	depends on RISCV_MMODE
361	select REGMAP
362	select SYSCON
363	help
364	  The RISC-V ACLINT block holds memory-mapped control and status registers
365	  associated with software and timer interrupts.
366
367config SPL_RISCV_ACLINT
368	bool
369	depends on SPL_RISCV_MMODE
370	select SPL_REGMAP
371	select SPL_SYSCON
372	help
373	  The RISC-V ACLINT block holds memory-mapped control and status registers
374	  associated with software and timer interrupts.
375
376config SIFIVE_CACHE
377	bool
378	help
379	  This enables the operations to configure SiFive cache
380
381config ANDES_PLICSW
382	bool
383	depends on RISCV_MMODE || SPL_RISCV_MMODE
384	select REGMAP
385	select SYSCON
386	select SPL_REGMAP if SPL
387	select SPL_SYSCON if SPL
388	help
389	  The Andes PLICSW block holds memory-mapped claim and pending
390	  registers associated with software interrupt.
391
392config SMP
393	bool "Symmetric Multi-Processing"
394	depends on SBI_V01 || !RISCV_SMODE
395	help
396	  This enables support for systems with more than one CPU. If
397	  you say N here, U-Boot will run on single and multiprocessor
398	  machines, but will use only one CPU of a multiprocessor
399	  machine. If you say Y here, U-Boot will run on many, but not
400	  all, single processor machines.
401
402config SPL_SMP
403	bool "Symmetric Multi-Processing in SPL"
404	depends on SPL && SPL_RISCV_MMODE
405	default y
406	help
407	  This enables support for systems with more than one CPU in SPL.
408	  If you say N here, U-Boot SPL will run on single and multiprocessor
409	  machines, but will use only one CPU of a multiprocessor
410	  machine. If you say Y here, U-Boot SPL will run on many, but not
411	  all, single processor machines.
412
413config NR_CPUS
414	int "Maximum number of CPUs (2-32)"
415	range 2 32
416	depends on SMP || SPL_SMP
417	default 8
418	help
419	  On multiprocessor machines, U-Boot sets up a stack for each CPU.
420	  Stack memory is pre-allocated. U-Boot must therefore know the
421	  maximum number of CPUs that may be present.
422
423config SBI
424	bool
425	default y if RISCV_SMODE || SPL_RISCV_SMODE
426
427choice
428	prompt "SBI support"
429	default SBI_V02
430
431config SBI_V01
432	bool "SBI v0.1 support"
433	depends on SBI
434	help
435	  This config allows kernel to use SBI v0.1 APIs. This will be
436	  deprecated in future once legacy M-mode software are no longer in use.
437
438config SBI_V02
439	bool "SBI v0.2 or later support"
440	depends on SBI
441	help
442	  The SBI specification introduced the concept of extensions in version
443	  v0.2. With this configuration option U-Boot can detect and use SBI
444	  extensions. With the HSM extension introduced in SBI 0.2, only a
445	  single hart needs to boot and enter the operating system. The booting
446	  hart can bring up secondary harts one by one afterwards.
447
448	  Choose this option if OpenSBI release v0.7 or above is used together
449	  with U-Boot.
450
451endchoice
452
453config SBI_IPI
454	bool
455	depends on SBI
456	default y if RISCV_SMODE || SPL_RISCV_SMODE
457	depends on SMP
458
459config XIP
460	bool "XIP mode"
461	help
462	  XIP (eXecute In Place) is a method for executing code directly
463	  from a NOR flash memory without copying the code to ram.
464	  Say yes here if U-Boot boots from flash directly.
465
466config SPL_XIP
467	bool "Enable XIP mode for SPL"
468	help
469	  If SPL starts in read-only memory (XIP for example) then we shouldn't
470	  rely on lock variables (for example hart_lottery and available_harts_lock),
471	  this affects only SPL, other stages should proceed as non-XIP.
472
473config AVAILABLE_HARTS
474	bool "Send IPI by available harts"
475	depends on !XIP
476	default y
477	help
478	  By default, IPI sending mechanism will depend on available_harts.
479	  If disable this, it will send IPI by CPUs node numbers of device tree.
480
481config SHOW_REGS
482	default y
483	bool "Show registers on unhandled exception"
484	help
485	  By default only the program counter and the return address register
486	  are shown in crash dumps. Enable this symbol to show all registers in
487	  main U-Boot.
488
489config SPL_SHOW_REGS
490	bool "In SPL show registers on unhandled exception"
491	depends on SPL
492	help
493	  By default only the program counter and the return address register
494	  are shown in crash dumps. Enable this symbol to show all registers in
495	  SPL.
496
497config RISCV_PRIV_1_9
498	bool "Use version 1.9 of the RISC-V priviledged specification"
499	help
500	  Older versions of the RISC-V priviledged specification had
501	  separate counter enable CSRs for each privilege mode. Writing
502	  to the unified mcounteren CSR on a processor implementing the
503	  old specification will result in an illegal instruction
504	  exception. In addition to counter CSR changes, the way virtual
505	  memory is configured was also changed.
506
507config STACK_SIZE_SHIFT
508	int "Stack size shift"
509	default 14
510
511config OF_BOARD_FIXUP
512	default y if OF_SEPARATE && RISCV_SMODE
513
514menu "Use assembly optimized implementation of memory routines"
515
516config USE_ARCH_MEMCPY
517	bool "Use an assembly optimized implementation of memcpy"
518	default y
519	help
520	  Enable the generation of an optimized version of memcpy.
521	  Such an implementation may be faster under some conditions
522	  but may increase the binary size.
523
524config SPL_USE_ARCH_MEMCPY
525	bool "Use an assembly optimized implementation of memcpy for SPL"
526	default y if USE_ARCH_MEMCPY
527	depends on SPL
528	help
529	  Enable the generation of an optimized version of memcpy.
530	  Such an implementation may be faster under some conditions
531	  but may increase the binary size.
532
533config TPL_USE_ARCH_MEMCPY
534	bool "Use an assembly optimized implementation of memcpy for TPL"
535	default y if USE_ARCH_MEMCPY
536	depends on TPL
537	help
538	  Enable the generation of an optimized version of memcpy.
539	  Such an implementation may be faster under some conditions
540	  but may increase the binary size.
541
542config USE_ARCH_MEMMOVE
543	bool "Use an assembly optimized implementation of memmove"
544	default y
545	help
546	  Enable the generation of an optimized version of memmove.
547	  Such an implementation may be faster under some conditions
548	  but may increase the binary size.
549
550config SPL_USE_ARCH_MEMMOVE
551	bool "Use an assembly optimized implementation of memmove for SPL"
552	default y if USE_ARCH_MEMCPY
553	depends on SPL
554	help
555	  Enable the generation of an optimized version of memmove.
556	  Such an implementation may be faster under some conditions
557	  but may increase the binary size.
558
559config TPL_USE_ARCH_MEMMOVE
560	bool "Use an assembly optimized implementation of memmove for TPL"
561	default y if USE_ARCH_MEMCPY
562	depends on TPL
563	help
564	  Enable the generation of an optimized version of memmove.
565	  Such an implementation may be faster under some conditions
566	  but may increase the binary size.
567
568config USE_ARCH_MEMSET
569	bool "Use an assembly optimized implementation of memset"
570	default y
571	help
572	  Enable the generation of an optimized version of memset.
573	  Such an implementation may be faster under some conditions
574	  but may increase the binary size.
575
576config SPL_USE_ARCH_MEMSET
577	bool "Use an assembly optimized implementation of memset for SPL"
578	default y if USE_ARCH_MEMSET
579	depends on SPL
580	help
581	  Enable the generation of an optimized version of memset.
582	  Such an implementation may be faster under some conditions
583	  but may increase the binary size.
584
585config TPL_USE_ARCH_MEMSET
586	bool "Use an assembly optimized implementation of memset for TPL"
587	default y if USE_ARCH_MEMSET
588	depends on TPL
589	help
590	  Enable the generation of an optimized version of memset.
591	  Such an implementation may be faster under some conditions
592	  but may increase the binary size.
593
594endmenu
595
596config SPL_LOAD_FIT_OPENSBI_OS_BOOT
597	bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT"
598	depends on SPL_LOAD_FIT
599	help
600	  Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly.
601	  This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
602	  -> linux to u-boot SPL -> OpenSBI -> linux.
603
604config SPL_OPTEE_LOAD_ADDR
605	hex "OP-TEE Trusted OS image load address"
606	depends on OPTEE
607	help
608	  Load address of the OP-TEE binary.
609
610endmenu
611