1if ARCH_STM32MP 2 3config SPL 4 select SPL_BOARD_INIT 5 select SPL_CLK 6 select SPL_DM 7 select SPL_DM_SEQ_ALIAS 8 select SPL_DRIVERS_MISC 9 select SPL_FRAMEWORK 10 select SPL_GPIO 11 select SPL_LIBCOMMON_SUPPORT 12 select SPL_LIBGENERIC_SUPPORT 13 select SPL_OF_CONTROL 14 select SPL_OF_TRANSLATE 15 select SPL_PINCTRL 16 select SPL_REGMAP 17 select SPL_DM_RESET 18 select SPL_SERIAL 19 select SPL_SYSCON 20 select SPL_WATCHDOG if WATCHDOG 21 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE 22 imply SPL_BOOTSTAGE if BOOTSTAGE 23 imply SPL_DISPLAY_PRINT 24 imply SPL_LIBDISK_SUPPORT 25 imply SPL_SPI_LOAD if SPL_SPI 26 27config SYS_SOC 28 default "stm32mp" 29 30config SYS_MALLOC_LEN 31 default 0x2000000 32 33config ENV_SIZE 34 default 0x2000 35 36choice 37 prompt "Select STMicroelectronics STM32MPxxx Soc" 38 default STM32MP15X 39 40config STM32MP13X 41 bool "Support STMicroelectronics STM32MP13x Soc" 42 select ARCH_EARLY_INIT_R 43 select ARM_SMCCC if TFABOOT 44 select ARCH_SUPPORT_PSCI if !TFABOOT 45 select BINMAN if !TFABOOT 46 select CPU_V7A 47 select CPU_V7_HAS_NONSEC 48 select CPU_V7_HAS_VIRT 49 select OF_BOARD if TFABOOT 50 select OF_BOARD_SETUP 51 select PINCTRL_STM32 52 select STM32_RCC 53 select STM32_RESET 54 select STM32_SERIAL 55 select SUPPORT_SPL if !TFABOOT 56 select SYS_ARCH_TIMER 57 imply CMD_NVEDIT_INFO 58 imply OF_UPSTREAM 59 help 60 support of STMicroelectronics SOC STM32MP13x family 61 STMicroelectronics MPU with core ARMv7 62 63config STM32MP15X 64 bool "Support STMicroelectronics STM32MP15x Soc" 65 select ARCH_EARLY_INIT_R 66 select ARCH_SUPPORT_PSCI 67 select BINMAN 68 select CPU_V7A 69 select CPU_V7_HAS_NONSEC 70 select CPU_V7_HAS_VIRT 71 select OF_BOARD if TFABOOT 72 select OF_BOARD_SETUP 73 select PINCTRL_STM32 74 select STM32_RCC 75 select STM32_RESET 76 select STM32_SERIAL 77 select SUPPORT_SPL 78 select SYS_ARCH_TIMER 79 imply CMD_NVEDIT_INFO 80 imply OF_UPSTREAM 81 help 82 support of STMicroelectronics SOC STM32MP15x family 83 STM32MP157, STM32MP153 or STM32MP151 84 STMicroelectronics MPU with core ARMv7 85 dual core A7 for STM32MP157/3, monocore for STM32MP151 86 87config STM32MP23X 88 bool "Support STMicroelectronics STM32MP23x Soc" 89 select ARM64 90 select CLK_STM32MP25 91 select OF_BOARD 92 select PINCTRL_STM32 93 select STM32_RCC 94 select STM32_RESET 95 select STM32_SERIAL 96 select STM32MP_TAMP_NVMEM 97 select SYS_ARCH_TIMER 98 select TFABOOT 99 imply CLK_SCMI 100 imply CMD_NVEDIT_INFO 101 imply DM_REGULATOR 102 imply DM_REGULATOR_SCMI 103 imply OF_UPSTREAM 104 imply OPTEE 105 imply RESET_SCMI 106 imply SYSRESET_PSCI 107 imply TEE 108 imply VERSION_VARIABLE 109 help 110 Support of STMicroelectronics SOC STM32MP23x family 111 STMicroelectronics MPU with 2 * A53 core and 1 M33 core 112 113config STM32MP25X 114 bool "Support STMicroelectronics STM32MP25x Soc" 115 select ARM64 116 select CLK_STM32MP25 117 select OF_BOARD 118 select PINCTRL_STM32 119 select STM32_RCC 120 select STM32_RESET 121 select STM32_SERIAL 122 select SYS_ARCH_TIMER 123 select TFABOOT 124 imply CLK_SCMI 125 imply CMD_NVEDIT_INFO 126 imply DM_REGULATOR 127 imply DM_REGULATOR_SCMI 128 imply OF_UPSTREAM 129 imply OPTEE 130 imply RESET_SCMI 131 imply SYSRESET_PSCI 132 imply TEE 133 imply VERSION_VARIABLE 134 help 135 Support of STMicroelectronics SOC STM32MP25x family 136 STMicroelectronics MPU with 2 * A53 core and 1 M33 core 137endchoice 138 139config NR_DRAM_BANKS 140 default 1 141 142config DDR_CACHEABLE_SIZE 143 hex "Size of the DDR marked cacheable in pre-reloc stage" 144 default 0x40000000 145 help 146 Define the size of the DDR marked as cacheable in U-Boot 147 pre-reloc stage. 148 This option can be useful to avoid speculatif access 149 to secured area of DDR used by TF-A or OP-TEE before U-Boot 150 initialization. 151 The areas marked "no-map" in device tree should be located 152 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. 153 154config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 155 hex "Partition on MMC2 to use to load U-Boot from" 156 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION 157 default 1 158 help 159 Partition on the second MMC to load U-Boot from when the MMC is being 160 used in raw mode 161 162config STM32_ECDSA_VERIFY 163 bool "STM32 ECDSA verification via the ROM API" 164 depends on SPL_ECDSA_VERIFY 165 default y 166 help 167 Say y to enable the uclass driver for ECDSA verification using the 168 ROM API provided on STM32MP. 169 The ROM API is only available during SPL for now. 170 171config STM32MP_TAMP_NVMEM 172 bool "STM32 TAMP backup registers via NVMEM API" 173 select NVMEM 174 default y 175 help 176 Say y to enable the uclass driver for TAMP Backup registers using the 177 NVMEM API. It allows to access to boot mode or others shared information 178 between software components/execution levels. 179 180config CMD_STM32KEY 181 bool "command stm32key to fuse public key hash" 182 depends on CMDLINE 183 help 184 fuse public key hash in corresponding fuse used to authenticate 185 binary. 186 This command is used to evaluate the secure boot on stm32mp SOC, 187 it is deactivated by default in real products. 188 189config MFD_STM32_TIMERS 190 bool "STM32 multifonction timer support" 191 help 192 Select this to enable support for the multifunction timer found on 193 STM32 devices. 194 195source "arch/arm/mach-stm32mp/Kconfig.13x" 196source "arch/arm/mach-stm32mp/Kconfig.15x" 197source "arch/arm/mach-stm32mp/Kconfig.23x" 198source "arch/arm/mach-stm32mp/Kconfig.25x" 199source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" 200 201config STM32MP15_PWR 202 bool "Enable driver for STM32MP15x PWR" 203 depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) 204 default y if STM32MP15X 205 help 206 This config enables implementation of driver-model pmic and 207 regulator uclass features for access to STM32MP15x PWR. 208 209config SPL_STM32MP15_PWR 210 bool "Enable driver for STM32MP15x PWR in SPL" 211 depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X) 212 default y if STM32MP15X 213 help 214 This config enables implementation of driver-model pmic and 215 regulator uclass features for access to STM32MP15x PWR in SPL. 216 217endif 218