1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config PPC_SPINTABLE_COMPATIBLE 5 depends on MP 6 def_bool y 7 help 8 To comply with ePAPR 1.1, the spin table has been moved to 9 cache-enabled memory. Old OS may not work with this change. A patch 10 is waiting to be accepted for Linux kernel. Other OS needs similar 11 fix to spin table. For OSes with old spin table code, we can enable 12 this temporary fix by setting environmental variable 13 "spin_table_compat". For new OSes, set "spin_table_compat=no". After 14 Linux is fixed, we can remove this macro and related code. For now, 15 it is enabled by default. 16 17config SYS_CPU 18 default "mpc85xx" 19 20config CMD_ERRATA 21 bool "Enable the 'errata' command" 22 depends on MPC85xx 23 default y 24 help 25 This enables the 'errata' command which displays a list of errata 26 work-arounds which are enabled for the current board. 27 28config FSL_PREPBL_ESDHC_BOOT_SECTOR 29 bool "Generate QorIQ pre-PBL eSDHC boot sector" 30 depends on MPC85xx 31 depends on SDCARD 32 help 33 With this option final image would have prepended QorIQ pre-PBL eSDHC 34 boot sector suitable for SD card images. This boot sector instruct 35 BootROM to configure L2 SRAM and eSDHC then load image from SD card 36 into L2 SRAM and finally jump to image entry point. 37 38 This is alternative to Freescale boot_format tool, but works only for 39 SD card images and only for L2 SRAM booting. U-Boot images generated 40 with this option should not passed to boot_format tool. 41 42 For other configuration like booting from eSPI or configuring SDRAM 43 please use Freescale boot_format tool without this option. See file 44 doc/README.mpc85xx-sd-spi-boot 45 46config FSL_PREPBL_ESDHC_BOOT_SECTOR_START 47 int "QorIQ pre-PBL eSDHC boot sector start offset" 48 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR 49 range 0 23 50 default 0 51 help 52 QorIQ pre-PBL eSDHC boot sector may be located on one of the first 53 24 SD card sectors. Select SD card sector on which final U-Boot 54 image (with this boot sector) would be installed. 55 56 By default first SD card sector (0) is used. But this may be changed 57 to allow installing U-Boot image on some partition (with fixed start 58 sector). 59 60 Please note that any sector on SD card prior this boot sector must 61 not contain ASCII "BOOT" bytes at sector offset 0x40. 62 63config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA 64 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector" 65 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR 66 default 1 67 range 1 8388607 68 help 69 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot 70 sector on which would be stored raw U-Boot image. 71 72 By default is it second sector (1) which is the first available free 73 sector (on the first sector is stored boot sector). It can be any 74 sector number which offset in bytes can be expressed by 32-bit number. 75 76 In case this final U-Boot image (with this boot sector) is put on 77 the FAT32 partition into reserved boot area, this data sector needs 78 to be at least 2 (third sector) because FAT32 use second sector for 79 its data. 80 81choice 82 prompt "Target select" 83 optional 84 85config TARGET_SOCRATES 86 bool "Support socrates" 87 select ARCH_MPC8544 88 select BINMAN 89 90config TARGET_P3041DS 91 bool "Support P3041DS" 92 select PHYS_64BIT 93 select ARCH_P3041 94 select BOARD_LATE_INIT if CHAIN_OF_TRUST 95 select FSL_NGPIXIS 96 imply CMD_SATA 97 imply PANIC_HANG 98 99config TARGET_P4080DS 100 bool "Support P4080DS" 101 select PHYS_64BIT 102 select ARCH_P4080 103 select BOARD_LATE_INIT if CHAIN_OF_TRUST 104 select FSL_NGPIXIS 105 imply CMD_SATA 106 imply PANIC_HANG 107 108config TARGET_P5040DS 109 bool "Support P5040DS" 110 select PHYS_64BIT 111 select ARCH_P5040 112 select BOARD_LATE_INIT if CHAIN_OF_TRUST 113 select FSL_NGPIXIS 114 select SYS_FSL_RAID_ENGINE 115 imply CMD_SATA 116 imply PANIC_HANG 117 118config TARGET_MPC8548CDS 119 bool "Support MPC8548CDS" 120 select ARCH_MPC8548 121 select FSL_VIA 122 select SYS_CACHE_SHIFT_5 123 124config TARGET_P1010RDB_PA 125 bool "Support P1010RDB_PA" 126 select ARCH_P1010 127 select BOARD_LATE_INIT if CHAIN_OF_TRUST 128 select SUPPORT_SPL 129 select SUPPORT_TPL 130 select SYS_L2_SIZE_256KB 131 imply CMD_EEPROM 132 imply CMD_SATA 133 imply PANIC_HANG 134 135config TARGET_P1010RDB_PB 136 bool "Support P1010RDB_PB" 137 select ARCH_P1010 138 select BOARD_LATE_INIT if CHAIN_OF_TRUST 139 select SUPPORT_SPL 140 select SUPPORT_TPL 141 select SYS_L2_SIZE_256KB 142 imply CMD_EEPROM 143 imply CMD_SATA 144 imply PANIC_HANG 145 146config TARGET_P1020RDB_PC 147 bool "Support P1020RDB-PC" 148 select SUPPORT_SPL 149 select SUPPORT_TPL 150 select ARCH_P1020 151 select SYS_L2_SIZE_256KB 152 imply CMD_EEPROM 153 imply CMD_SATA 154 imply PANIC_HANG 155 156config TARGET_P1020RDB_PD 157 bool "Support P1020RDB-PD" 158 select SUPPORT_SPL 159 select SUPPORT_TPL 160 select ARCH_P1020 161 select SYS_L2_SIZE_256KB 162 imply CMD_EEPROM 163 imply CMD_SATA 164 imply PANIC_HANG 165 166config TARGET_P2020RDB 167 bool "Support P2020RDB-PC" 168 select SUPPORT_SPL 169 select SUPPORT_TPL 170 select ARCH_P2020 171 select SYS_L2_SIZE_512KB 172 imply CMD_EEPROM 173 imply CMD_SATA 174 imply SATA_SIL 175 176config TARGET_TURRIS_1X 177 bool "Support Turris 1.x" 178 select SUPPORT_SPL 179 select ARCH_P2020 180 select BOARD_EARLY_INIT_F 181 select BOARD_EARLY_INIT_R 182 select LAST_STAGE_INIT 183 select OF_BOARD_SETUP 184 select SYS_L2_SIZE_512KB 185 186config TARGET_P2041RDB 187 bool "Support P2041RDB" 188 select ARCH_P2041 189 select BOARD_LATE_INIT if CHAIN_OF_TRUST 190 select FSL_CORENET 191 select PHYS_64BIT 192 select SYS_L3_SIZE_1024KB 193 imply CMD_SATA 194 imply FSL_SATA 195 196config TARGET_QEMU_PPCE500 197 bool "Support qemu-ppce500" 198 select ARCH_QEMU_E500 199 select PHYS_64BIT 200 select SYS_RAMBOOT 201 imply OF_HAS_PRIOR_STAGE 202 203config TARGET_T1024RDB 204 bool "Support T1024RDB" 205 select ARCH_T1024 206 select BOARD_LATE_INIT if CHAIN_OF_TRUST 207 select SUPPORT_SPL 208 select PHYS_64BIT 209 select FSL_DDR_INTERACTIVE 210 select SYS_L3_SIZE_256KB 211 imply CMD_EEPROM 212 imply PANIC_HANG 213 214config TARGET_T1042D4RDB 215 bool "Support T1042D4RDB" 216 select ARCH_T1042 217 select BOARD_LATE_INIT if CHAIN_OF_TRUST 218 select SUPPORT_SPL 219 select PHYS_64BIT 220 select SYS_L3_SIZE_256KB 221 imply PANIC_HANG 222 223config TARGET_T2080QDS 224 bool "Support T2080QDS" 225 select ARCH_T2080 226 select BOARD_LATE_INIT if CHAIN_OF_TRUST 227 select SUPPORT_SPL 228 select PHYS_64BIT 229 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 230 select FSL_DDR_INTERACTIVE 231 select SYS_L3_SIZE_512KB 232 imply CMD_SATA 233 234config TARGET_T2080RDB 235 bool "Support T2080RDB" 236 select ARCH_T2080 237 select BOARD_LATE_INIT if CHAIN_OF_TRUST 238 select SUPPORT_SPL 239 select PHYS_64BIT 240 select SYS_L3_SIZE_512KB 241 imply CMD_SATA 242 imply PANIC_HANG 243 244config TARGET_T4240RDB 245 bool "Support T4240RDB" 246 select ARCH_T4240 247 select SUPPORT_SPL 248 select PHYS_64BIT 249 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 250 select SYS_L3_SIZE_512KB 251 imply CMD_SATA 252 imply PANIC_HANG 253 254config TARGET_KMP204X 255 bool "Support kmp204x" 256 select VENDOR_KM 257 258config TARGET_KMCENT2 259 bool "Support kmcent2" 260 select VENDOR_KM 261 select EVENT 262 select FSL_CORENET 263 select SYS_DPAA_FMAN 264 select SYS_DPAA_PME 265 select SYS_L3_SIZE_256KB 266 267endchoice 268 269config ARCH_B4420 270 bool 271 select E500MC 272 select E6500 273 select FSL_CORENET 274 select FSL_LAW 275 select HETROGENOUS_CLUSTERS 276 select SYS_FSL_DDR_VER_47 277 select SYS_FSL_ERRATUM_A004477 278 select SYS_FSL_ERRATUM_A005871 279 select SYS_FSL_ERRATUM_A006379 280 select SYS_FSL_ERRATUM_A006384 281 select SYS_FSL_ERRATUM_A006475 282 select SYS_FSL_ERRATUM_A006593 283 select SYS_FSL_ERRATUM_A007075 284 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 285 select SYS_FSL_ERRATUM_A007212 286 select SYS_FSL_ERRATUM_A009942 287 select SYS_FSL_HAS_DDR3 288 select SYS_FSL_HAS_SEC 289 select SYS_FSL_QORIQ_CHASSIS2 290 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 291 select SYS_FSL_SEC_BE 292 select SYS_FSL_SEC_COMPAT_4 293 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 294 select SYS_FSL_USB1_PHY_ENABLE 295 select SYS_PPC64 296 select FSL_IFC 297 imply CMD_EEPROM 298 imply CMD_NAND 299 imply CMD_REGINFO 300 301config ARCH_B4860 302 bool 303 select E500MC 304 select E6500 305 select FSL_CORENET 306 select FSL_LAW 307 select HETROGENOUS_CLUSTERS 308 select SYS_FSL_DDR_VER_47 309 select SYS_FSL_ERRATUM_A004477 310 select SYS_FSL_ERRATUM_A005871 311 select SYS_FSL_ERRATUM_A006379 312 select SYS_FSL_ERRATUM_A006384 313 select SYS_FSL_ERRATUM_A006475 314 select SYS_FSL_ERRATUM_A006593 315 select SYS_FSL_ERRATUM_A007075 316 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 317 select SYS_FSL_ERRATUM_A007212 318 select SYS_FSL_ERRATUM_A007907 319 select SYS_FSL_ERRATUM_A009942 320 select SYS_FSL_HAS_DDR3 321 select SYS_FSL_HAS_SEC 322 select SYS_FSL_QORIQ_CHASSIS2 323 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 324 select SYS_FSL_SEC_BE 325 select SYS_FSL_SEC_COMPAT_4 326 select SYS_FSL_SRDS_1 327 select SYS_FSL_SRDS_2 328 select SYS_FSL_SRIO_LIODN 329 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 330 select SYS_FSL_USB1_PHY_ENABLE 331 select SYS_PPC64 332 select FSL_IFC 333 imply CMD_EEPROM 334 imply CMD_NAND 335 imply CMD_REGINFO 336 337config ARCH_BSC9131 338 bool 339 select FSL_LAW 340 select SYS_FSL_DDR_VER_44 341 select SYS_FSL_ERRATUM_A004477 342 select SYS_FSL_ERRATUM_A005125 343 select SYS_FSL_ERRATUM_ESDHC111 344 select SYS_FSL_HAS_DDR3 345 select SYS_FSL_HAS_SEC 346 select SYS_FSL_SEC_BE 347 select SYS_FSL_SEC_COMPAT_4 348 select FSL_IFC 349 imply CMD_EEPROM 350 imply CMD_NAND 351 imply CMD_REGINFO 352 353config ARCH_BSC9132 354 bool 355 select FSL_LAW 356 select SYS_FSL_DDR_VER_46 357 select SYS_FSL_ERRATUM_A004477 358 select SYS_FSL_ERRATUM_A005125 359 select SYS_FSL_ERRATUM_A005434 360 select SYS_FSL_ERRATUM_ESDHC111 361 select SYS_FSL_ERRATUM_I2C_A004447 362 select SYS_FSL_ERRATUM_IFC_A002769 363 select FSL_PCIE_RESET 364 select SYS_FSL_HAS_DDR3 365 select SYS_FSL_HAS_SEC 366 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 367 select SYS_FSL_SEC_BE 368 select SYS_FSL_SEC_COMPAT_4 369 select SYS_PPC_E500_USE_DEBUG_TLB 370 select FSL_IFC 371 imply CMD_EEPROM 372 imply CMD_MTDPARTS 373 imply CMD_NAND 374 imply CMD_PCI 375 imply CMD_REGINFO 376 377config ARCH_C29X 378 bool 379 select FSL_LAW 380 select SYS_FSL_DDR_VER_46 381 select SYS_FSL_ERRATUM_A005125 382 select SYS_FSL_ERRATUM_ESDHC111 383 select FSL_PCIE_RESET 384 select SYS_FSL_HAS_DDR3 385 select SYS_FSL_HAS_SEC 386 select SYS_FSL_SEC_BE 387 select SYS_FSL_SEC_COMPAT_6 388 select SYS_PPC_E500_USE_DEBUG_TLB 389 select FSL_IFC 390 imply CMD_NAND 391 imply CMD_PCI 392 imply CMD_REGINFO 393 394config ARCH_MPC8536 395 bool 396 select FSL_LAW 397 select SYS_FSL_ERRATUM_A004508 398 select SYS_FSL_ERRATUM_A005125 399 select FSL_PCIE_RESET 400 select SYS_FSL_HAS_DDR2 401 select SYS_FSL_HAS_DDR3 402 select SYS_FSL_HAS_SEC 403 select SYS_FSL_SEC_BE 404 select SYS_FSL_SEC_COMPAT_2 405 select SYS_PPC_E500_USE_DEBUG_TLB 406 select FSL_ELBC 407 imply CMD_NAND 408 imply CMD_SATA 409 imply CMD_REGINFO 410 411config ARCH_MPC8540 412 bool 413 select FSL_LAW 414 select SYS_FSL_HAS_DDR1 415 416config ARCH_MPC8544 417 bool 418 select BTB 419 select FSL_LAW 420 select SYS_CACHE_SHIFT_5 421 select SYS_FSL_ERRATUM_A005125 422 select FSL_PCIE_RESET 423 select SYS_FSL_HAS_DDR2 424 select SYS_FSL_HAS_SEC 425 select SYS_FSL_SEC_BE 426 select SYS_FSL_SEC_COMPAT_2 427 select SYS_PPC_E500_USE_DEBUG_TLB 428 select FSL_ELBC 429 430config ARCH_MPC8548 431 bool 432 select BTB 433 select FSL_LAW 434 select SYS_FSL_ERRATUM_A005125 435 select SYS_FSL_ERRATUM_NMG_DDR120 436 select SYS_FSL_ERRATUM_NMG_LBC103 437 select SYS_FSL_ERRATUM_NMG_ETSEC129 438 select SYS_FSL_ERRATUM_I2C_A004447 439 select FSL_PCIE_RESET 440 select SYS_FSL_HAS_DDR2 441 select SYS_FSL_HAS_DDR1 442 select SYS_FSL_HAS_SEC 443 select SYS_FSL_RMU 444 select SYS_FSL_SEC_BE 445 select SYS_FSL_SEC_COMPAT_2 446 select SYS_PPC_E500_USE_DEBUG_TLB 447 imply CMD_REGINFO 448 449config ARCH_MPC8560 450 bool 451 select FSL_LAW 452 select SYS_FSL_HAS_DDR1 453 454config ARCH_P1010 455 bool 456 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL 457 select BTB 458 select FSL_LAW 459 select SYS_CACHE_SHIFT_5 460 select SYS_HAS_SERDES 461 select SYS_FSL_ERRATUM_A004477 462 select SYS_FSL_ERRATUM_A004508 463 select SYS_FSL_ERRATUM_A005125 464 select SYS_FSL_ERRATUM_A005275 465 select SYS_FSL_ERRATUM_A006261 466 select SYS_FSL_ERRATUM_A007075 467 select SYS_FSL_ERRATUM_ESDHC111 468 select SYS_FSL_ERRATUM_I2C_A004447 469 select SYS_FSL_ERRATUM_IFC_A002769 470 select SYS_FSL_ERRATUM_P1010_A003549 471 select SYS_FSL_ERRATUM_SEC_A003571 472 select SYS_FSL_ERRATUM_IFC_A003399 473 select FSL_PCIE_RESET 474 select SYS_FSL_HAS_DDR3 475 select SYS_FSL_HAS_SEC 476 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 477 select SYS_FSL_SEC_BE 478 select SYS_FSL_SEC_COMPAT_4 479 select SYS_FSL_USB1_PHY_ENABLE 480 select SYS_PPC_E500_USE_DEBUG_TLB 481 select FSL_IFC 482 imply CMD_EEPROM 483 imply CMD_MTDPARTS 484 imply CMD_NAND 485 imply CMD_SATA 486 imply CMD_PCI 487 imply CMD_REGINFO 488 imply FSL_SATA 489 imply TIMESTAMP 490 491config ARCH_P1011 492 bool 493 select FSL_LAW 494 select SYS_FSL_ERRATUM_A004508 495 select SYS_FSL_ERRATUM_A005125 496 select SYS_FSL_ERRATUM_ELBC_A001 497 select SYS_FSL_ERRATUM_ESDHC111 498 select FSL_PCIE_DISABLE_ASPM 499 select SYS_FSL_HAS_DDR3 500 select SYS_FSL_HAS_SEC 501 select SYS_FSL_SEC_BE 502 select SYS_FSL_SEC_COMPAT_2 503 select SYS_PPC_E500_USE_DEBUG_TLB 504 select FSL_ELBC 505 506config ARCH_P1020 507 bool 508 select BTB 509 select FSL_LAW 510 select SYS_CACHE_SHIFT_5 511 select SYS_FSL_ERRATUM_A004508 512 select SYS_FSL_ERRATUM_A005125 513 select SYS_FSL_ERRATUM_ELBC_A001 514 select SYS_FSL_ERRATUM_ESDHC111 515 select FSL_PCIE_DISABLE_ASPM 516 select FSL_PCIE_RESET 517 select SYS_FSL_HAS_DDR3 518 select SYS_FSL_HAS_SEC 519 select SYS_FSL_SEC_BE 520 select SYS_FSL_SEC_COMPAT_2 521 select SYS_PPC_E500_USE_DEBUG_TLB 522 select FSL_ELBC 523 imply CMD_NAND 524 imply CMD_SATA 525 imply CMD_PCI 526 imply CMD_REGINFO 527 imply SATA_SIL 528 529config ARCH_P1021 530 bool 531 select FSL_LAW 532 select SYS_FSL_ERRATUM_A004508 533 select SYS_FSL_ERRATUM_A005125 534 select SYS_FSL_ERRATUM_ELBC_A001 535 select SYS_FSL_ERRATUM_ESDHC111 536 select FSL_PCIE_DISABLE_ASPM 537 select FSL_PCIE_RESET 538 select SYS_FSL_HAS_DDR3 539 select SYS_FSL_HAS_SEC 540 select SYS_FSL_SEC_BE 541 select SYS_FSL_SEC_COMPAT_2 542 select SYS_PPC_E500_USE_DEBUG_TLB 543 select FSL_ELBC 544 imply CMD_REGINFO 545 imply CMD_NAND 546 imply CMD_SATA 547 imply CMD_REGINFO 548 imply SATA_SIL 549 550config ARCH_P1023 551 bool 552 select FSL_LAW 553 select SYS_FSL_ERRATUM_A004508 554 select SYS_FSL_ERRATUM_A005125 555 select SYS_FSL_ERRATUM_I2C_A004447 556 select FSL_PCIE_RESET 557 select SYS_FSL_HAS_DDR3 558 select SYS_FSL_HAS_SEC 559 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 560 select SYS_FSL_SEC_BE 561 select SYS_FSL_SEC_COMPAT_4 562 select FSL_ELBC 563 564config ARCH_P1024 565 bool 566 select FSL_LAW 567 select SYS_FSL_ERRATUM_A004508 568 select SYS_FSL_ERRATUM_A005125 569 select SYS_FSL_ERRATUM_ELBC_A001 570 select SYS_FSL_ERRATUM_ESDHC111 571 select FSL_PCIE_DISABLE_ASPM 572 select FSL_PCIE_RESET 573 select SYS_FSL_HAS_DDR3 574 select SYS_FSL_HAS_SEC 575 select SYS_FSL_RMU 576 select SYS_FSL_SEC_BE 577 select SYS_FSL_SEC_COMPAT_2 578 select SYS_PPC_E500_USE_DEBUG_TLB 579 select FSL_ELBC 580 imply CMD_EEPROM 581 imply CMD_NAND 582 imply CMD_SATA 583 imply CMD_PCI 584 imply CMD_REGINFO 585 imply SATA_SIL 586 587config ARCH_P1025 588 bool 589 select FSL_LAW 590 select SYS_FSL_ERRATUM_A004508 591 select SYS_FSL_ERRATUM_A005125 592 select SYS_FSL_ERRATUM_ELBC_A001 593 select SYS_FSL_ERRATUM_ESDHC111 594 select FSL_PCIE_DISABLE_ASPM 595 select FSL_PCIE_RESET 596 select SYS_FSL_HAS_DDR3 597 select SYS_FSL_HAS_SEC 598 select SYS_FSL_SEC_BE 599 select SYS_FSL_SEC_COMPAT_2 600 select SYS_PPC_E500_USE_DEBUG_TLB 601 select FSL_ELBC 602 imply CMD_SATA 603 imply CMD_REGINFO 604 605config ARCH_P2020 606 bool 607 select BTB 608 select FSL_LAW 609 select SYS_CACHE_SHIFT_5 610 select SYS_FSL_ERRATUM_A004477 611 select SYS_FSL_ERRATUM_A004508 612 select SYS_FSL_ERRATUM_A005125 613 select SYS_FSL_ERRATUM_ESDHC111 614 select SYS_FSL_ERRATUM_ESDHC_A001 615 select FSL_PCIE_RESET 616 select SYS_FSL_HAS_DDR3 617 select SYS_FSL_HAS_SEC 618 select SYS_FSL_SEC_BE 619 select SYS_FSL_SEC_COMPAT_2 620 select SYS_PPC_E500_USE_DEBUG_TLB 621 select FSL_ELBC 622 imply CMD_EEPROM 623 imply CMD_NAND 624 imply CMD_REGINFO 625 imply TIMESTAMP 626 627config ARCH_P2041 628 bool 629 select BACKSIDE_L2_CACHE 630 select E500MC 631 select FSL_LAW 632 select SYS_CACHE_SHIFT_6 633 select SYS_DPAA_FMAN 634 select SYS_DPAA_PME 635 select SYS_DPAA_RMAN 636 select SYS_FSL_ERRATUM_A004510 637 select SYS_FSL_ERRATUM_A004849 638 select SYS_FSL_ERRATUM_A005275 639 select SYS_FSL_ERRATUM_A006261 640 select SYS_FSL_ERRATUM_CPU_A003999 641 select SYS_FSL_ERRATUM_DDR_A003 642 select SYS_FSL_ERRATUM_DDR_A003474 643 select SYS_FSL_ERRATUM_ESDHC111 644 select SYS_FSL_ERRATUM_I2C_A004447 645 select SYS_FSL_ERRATUM_NMG_CPU_A011 646 select SYS_FSL_ERRATUM_SRIO_A004034 647 select SYS_FSL_ERRATUM_USB14 648 select SYS_FSL_HAS_DDR3 649 select SYS_FSL_HAS_SEC 650 select SYS_FSL_QORIQ_CHASSIS1 651 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 652 select SYS_FSL_SEC_BE 653 select SYS_FSL_SEC_COMPAT_4 654 select SYS_FSL_USB1_PHY_ENABLE 655 select SYS_FSL_USB2_PHY_ENABLE 656 select FSL_ELBC 657 imply CMD_NAND 658 659config ARCH_P3041 660 bool 661 select BACKSIDE_L2_CACHE 662 select E500MC 663 select FSL_CORENET 664 select FSL_LAW 665 select SYS_CACHE_SHIFT_6 666 select SYS_FSL_DDR_VER_44 667 select SYS_FSL_ERRATUM_A004510 668 select SYS_FSL_ERRATUM_A004849 669 select SYS_FSL_ERRATUM_A005275 670 select SYS_FSL_ERRATUM_A005812 671 select SYS_FSL_ERRATUM_A006261 672 select SYS_FSL_ERRATUM_CPU_A003999 673 select SYS_FSL_ERRATUM_DDR_A003 674 select SYS_FSL_ERRATUM_DDR_A003474 675 select SYS_FSL_ERRATUM_ESDHC111 676 select SYS_FSL_ERRATUM_I2C_A004447 677 select SYS_FSL_ERRATUM_NMG_CPU_A011 678 select SYS_FSL_ERRATUM_SRIO_A004034 679 select SYS_FSL_ERRATUM_USB14 680 select SYS_FSL_HAS_DDR3 681 select SYS_FSL_HAS_SEC 682 select SYS_FSL_QORIQ_CHASSIS1 683 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 684 select SYS_FSL_SEC_BE 685 select SYS_FSL_SEC_COMPAT_4 686 select SYS_FSL_USB1_PHY_ENABLE 687 select SYS_FSL_USB2_PHY_ENABLE 688 select FSL_ELBC 689 imply CMD_NAND 690 imply CMD_SATA 691 imply CMD_REGINFO 692 imply FSL_SATA 693 694config ARCH_P4080 695 bool 696 select BACKSIDE_L2_CACHE 697 select E500MC 698 select FSL_CORENET 699 select FSL_LAW 700 select SYS_CACHE_SHIFT_6 701 select SYS_FSL_DDR_VER_44 702 select SYS_FSL_ERRATUM_A004510 703 select SYS_FSL_ERRATUM_A004580 704 select SYS_FSL_ERRATUM_A004849 705 select SYS_FSL_ERRATUM_A005812 706 select SYS_FSL_ERRATUM_A007075 707 select SYS_FSL_ERRATUM_CPC_A002 708 select SYS_FSL_ERRATUM_CPC_A003 709 select SYS_FSL_ERRATUM_CPU_A003999 710 select SYS_FSL_ERRATUM_DDR_A003 711 select SYS_FSL_ERRATUM_DDR_A003474 712 select SYS_FSL_ERRATUM_ELBC_A001 713 select SYS_FSL_ERRATUM_ESDHC111 714 select SYS_FSL_ERRATUM_ESDHC13 715 select SYS_FSL_ERRATUM_ESDHC135 716 select SYS_FSL_ERRATUM_I2C_A004447 717 select SYS_FSL_ERRATUM_NMG_CPU_A011 718 select SYS_FSL_ERRATUM_SRIO_A004034 719 select SYS_FSL_PCIE_COMPAT_P4080_PCIE 720 select SYS_P4080_ERRATUM_CPU22 721 select SYS_P4080_ERRATUM_PCIE_A003 722 select SYS_P4080_ERRATUM_SERDES8 723 select SYS_P4080_ERRATUM_SERDES9 724 select SYS_P4080_ERRATUM_SERDES_A001 725 select SYS_P4080_ERRATUM_SERDES_A005 726 select SYS_FSL_HAS_DDR3 727 select SYS_FSL_HAS_SEC 728 select SYS_FSL_QORIQ_CHASSIS1 729 select SYS_FSL_RMU 730 select SYS_FSL_SEC_BE 731 select SYS_FSL_SEC_COMPAT_4 732 select FSL_ELBC 733 imply CMD_SATA 734 imply CMD_REGINFO 735 imply SATA_SIL 736 737config ARCH_P5040 738 bool 739 select BACKSIDE_L2_CACHE 740 select E500MC 741 select FSL_CORENET 742 select FSL_LAW 743 select SYS_CACHE_SHIFT_6 744 select SYS_FSL_DDR_VER_44 745 select SYS_FSL_ERRATUM_A004510 746 select SYS_FSL_ERRATUM_A004699 747 select SYS_FSL_ERRATUM_A005275 748 select SYS_FSL_ERRATUM_A005812 749 select SYS_FSL_ERRATUM_A006261 750 select SYS_FSL_ERRATUM_DDR_A003 751 select SYS_FSL_ERRATUM_DDR_A003474 752 select SYS_FSL_ERRATUM_ESDHC111 753 select SYS_FSL_ERRATUM_USB14 754 select SYS_FSL_HAS_DDR3 755 select SYS_FSL_HAS_SEC 756 select SYS_FSL_QORIQ_CHASSIS1 757 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 758 select SYS_FSL_SEC_BE 759 select SYS_FSL_SEC_COMPAT_4 760 select SYS_FSL_USB1_PHY_ENABLE 761 select SYS_FSL_USB2_PHY_ENABLE 762 select SYS_PPC64 763 select FSL_ELBC 764 imply CMD_SATA 765 imply CMD_REGINFO 766 imply FSL_SATA 767 768config ARCH_QEMU_E500 769 bool 770 select SYS_CACHE_SHIFT_5 771 772config ARCH_T1024 773 bool 774 select BACKSIDE_L2_CACHE 775 select E500MC 776 select E5500 777 select FSL_CORENET 778 select FSL_LAW 779 select SYS_CACHE_SHIFT_6 780 select SYS_DPAA_FMAN 781 select SYS_FSL_DDR_VER_50 782 select SYS_FSL_ERRATUM_A008378 783 select SYS_FSL_ERRATUM_A008109 784 select SYS_FSL_ERRATUM_A009663 785 select SYS_FSL_ERRATUM_A009942 786 select SYS_FSL_ERRATUM_ESDHC111 787 select SYS_FSL_HAS_DDR3 788 select SYS_FSL_HAS_DDR4 789 select SYS_FSL_HAS_SEC 790 select SYS_FSL_QORIQ_CHASSIS2 791 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 792 select SYS_FSL_SEC_BE 793 select SYS_FSL_SEC_COMPAT_5 794 select SYS_FSL_SINGLE_SOURCE_CLK 795 select SYS_FSL_SRDS_1 796 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 797 select SYS_FSL_USB_DUAL_PHY_ENABLE 798 select FSL_IFC 799 imply CMD_EEPROM 800 imply CMD_NAND 801 imply CMD_MTDPARTS 802 imply CMD_REGINFO 803 804config ARCH_T1040 805 bool 806 select BACKSIDE_L2_CACHE 807 select E500MC 808 select E5500 809 select FSL_CORENET 810 select FSL_LAW 811 select SYS_CACHE_SHIFT_6 812 select SYS_DPAA_FMAN 813 select SYS_DPAA_PME 814 select SYS_FSL_DDR_VER_50 815 select SYS_FSL_ERRATUM_A008044 816 select SYS_FSL_ERRATUM_A008378 817 select SYS_FSL_ERRATUM_A008109 818 select SYS_FSL_ERRATUM_A009663 819 select SYS_FSL_ERRATUM_A009942 820 select SYS_FSL_ERRATUM_ESDHC111 821 select SYS_FSL_HAS_DDR3 822 select SYS_FSL_HAS_DDR4 823 select SYS_FSL_HAS_SEC 824 select SYS_FSL_QORIQ_CHASSIS2 825 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 826 select SYS_FSL_SEC_BE 827 select SYS_FSL_SEC_COMPAT_5 828 select SYS_FSL_SINGLE_SOURCE_CLK 829 select SYS_FSL_SRDS_1 830 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 831 select SYS_FSL_USB_DUAL_PHY_ENABLE 832 select FSL_IFC 833 imply CMD_MTDPARTS 834 imply CMD_NAND 835 imply CMD_REGINFO 836 837config ARCH_T1042 838 bool 839 select BACKSIDE_L2_CACHE 840 select E500MC 841 select E5500 842 select FSL_CORENET 843 select FSL_LAW 844 select SYS_CACHE_SHIFT_6 845 select SYS_DPAA_FMAN 846 select SYS_DPAA_PME 847 select SYS_FSL_DDR_VER_50 848 select SYS_FSL_ERRATUM_A008044 849 select SYS_FSL_ERRATUM_A008378 850 select SYS_FSL_ERRATUM_A008109 851 select SYS_FSL_ERRATUM_A009663 852 select SYS_FSL_ERRATUM_A009942 853 select SYS_FSL_ERRATUM_ESDHC111 854 select SYS_FSL_HAS_DDR3 855 select SYS_FSL_HAS_DDR4 856 select SYS_FSL_HAS_SEC 857 select SYS_FSL_QORIQ_CHASSIS2 858 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 859 select SYS_FSL_SEC_BE 860 select SYS_FSL_SEC_COMPAT_5 861 select SYS_FSL_SINGLE_SOURCE_CLK 862 select SYS_FSL_SRDS_1 863 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 864 select SYS_FSL_USB_DUAL_PHY_ENABLE 865 select FSL_IFC 866 imply CMD_MTDPARTS 867 imply CMD_NAND 868 imply CMD_REGINFO 869 870config ARCH_T2080 871 bool 872 select E500MC 873 select E6500 874 select FSL_CORENET 875 select FSL_LAW 876 select SYS_CACHE_SHIFT_6 877 select SYS_DPAA_DCE if !NOBQFMAN 878 select SYS_DPAA_FMAN if !NOBQFMAN 879 select SYS_DPAA_PME if !NOBQFMAN 880 select SYS_DPAA_RMAN if !NOBQFMAN 881 select SYS_FSL_DDR_VER_47 882 select SYS_FSL_ERRATUM_A006379 883 select SYS_FSL_ERRATUM_A006593 884 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 885 select SYS_FSL_ERRATUM_A007212 886 select SYS_FSL_ERRATUM_A007815 887 select SYS_FSL_ERRATUM_A007907 888 select SYS_FSL_ERRATUM_A008109 889 select SYS_FSL_ERRATUM_A009942 890 select SYS_FSL_ERRATUM_ESDHC111 891 select FSL_PCIE_RESET 892 select SYS_FSL_HAS_DDR3 893 select SYS_FSL_HAS_SEC 894 select SYS_FSL_QORIQ_CHASSIS2 895 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 896 select SYS_FSL_SEC_BE 897 select SYS_FSL_SEC_COMPAT_4 898 select SYS_FSL_SRDS_1 899 select SYS_FSL_SRDS_2 900 select SYS_FSL_SRIO_LIODN 901 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 902 select SYS_FSL_USB_DUAL_PHY_ENABLE 903 select SYS_PMAN if !NOBQFMAN 904 select SYS_PPC64 905 select FSL_IFC 906 imply CMD_SATA 907 imply CMD_NAND 908 imply CMD_REGINFO 909 imply FSL_SATA 910 imply ID_EEPROM 911 912config ARCH_T4240 913 bool 914 select E500MC 915 select E6500 916 select FSL_CORENET 917 select FSL_LAW 918 select SYS_CACHE_SHIFT_6 919 select SYS_DPAA_DCE if !NOBQFMAN 920 select SYS_DPAA_FMAN if !NOBQFMAN 921 select SYS_DPAA_PME if !NOBQFMAN 922 select SYS_DPAA_RMAN if !NOBQFMAN 923 select SYS_FSL_DDR_VER_47 924 select SYS_FSL_ERRATUM_A004468 925 select SYS_FSL_ERRATUM_A005871 926 select SYS_FSL_ERRATUM_A006261 927 select SYS_FSL_ERRATUM_A006379 928 select SYS_FSL_ERRATUM_A006593 929 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST 930 select SYS_FSL_ERRATUM_A007798 931 select SYS_FSL_ERRATUM_A007815 932 select SYS_FSL_ERRATUM_A007907 933 select SYS_FSL_ERRATUM_A008109 934 select SYS_FSL_ERRATUM_A009942 935 select SYS_FSL_HAS_DDR3 936 select SYS_FSL_HAS_SEC 937 select SYS_FSL_QORIQ_CHASSIS2 938 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 939 select SYS_FSL_SEC_BE 940 select SYS_FSL_SEC_COMPAT_4 941 select SYS_FSL_SRDS_1 942 select SYS_FSL_SRDS_2 943 select SYS_FSL_SRIO_LIODN 944 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN 945 select SYS_FSL_USB_DUAL_PHY_ENABLE 946 select SYS_PMAN if !NOBQFMAN 947 select SYS_PPC64 948 select FSL_IFC 949 imply CMD_SATA 950 imply CMD_NAND 951 imply CMD_REGINFO 952 imply FSL_SATA 953 954config MPC85XX_HAVE_RESET_VECTOR 955 bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc" 956 depends on MPC85xx 957 958config BTB 959 bool "toggle branch predition" 960 961config BOOKE 962 bool 963 default y 964 965config E500 966 bool 967 default y 968 help 969 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 970 971config E500MC 972 bool 973 select BTB 974 imply CMD_PCI 975 help 976 Enble PowerPC E500MC core 977 978config E5500 979 bool 980 981config E6500 982 bool 983 select BTB 984 help 985 Enable PowerPC E6500 core 986 987config NOBQFMAN 988 bool 989 990config FSL_LAW 991 bool 992 help 993 Use Freescale common code for Local Access Window 994 995config HETROGENOUS_CLUSTERS 996 bool 997 998config MAX_CPUS 999 int "Maximum number of CPUs permitted for MPC85xx" 1000 default 12 if ARCH_T4240 1001 default 8 if ARCH_P4080 1002 default 4 if ARCH_B4860 || \ 1003 ARCH_P2041 || \ 1004 ARCH_P3041 || \ 1005 ARCH_P5040 || \ 1006 ARCH_T1040 || \ 1007 ARCH_T1042 || \ 1008 ARCH_T2080 1009 default 2 if ARCH_B4420 || \ 1010 ARCH_BSC9132 || \ 1011 ARCH_P1020 || \ 1012 ARCH_P1021 || \ 1013 ARCH_P1023 || \ 1014 ARCH_P1024 || \ 1015 ARCH_P1025 || \ 1016 ARCH_P2020 || \ 1017 ARCH_T1024 1018 default 1 1019 help 1020 Set this number to the maximum number of possible CPUs in the SoC. 1021 SoCs may have multiple clusters with each cluster may have multiple 1022 ports. If some ports are reserved but higher ports are used for 1023 cores, count the reserved ports. This will allocate enough memory 1024 in spin table to properly handle all cores. 1025 1026config SYS_CCSRBAR_DEFAULT 1027 hex "Default CCSRBAR address" 1028 default 0xff700000 if ARCH_BSC9131 || \ 1029 ARCH_BSC9132 || \ 1030 ARCH_C29X || \ 1031 ARCH_MPC8536 || \ 1032 ARCH_MPC8540 || \ 1033 ARCH_MPC8544 || \ 1034 ARCH_MPC8548 || \ 1035 ARCH_MPC8560 || \ 1036 ARCH_P1010 || \ 1037 ARCH_P1011 || \ 1038 ARCH_P1020 || \ 1039 ARCH_P1021 || \ 1040 ARCH_P1024 || \ 1041 ARCH_P1025 || \ 1042 ARCH_P2020 1043 default 0xff600000 if ARCH_P1023 1044 default 0xfe000000 if ARCH_B4420 || \ 1045 ARCH_B4860 || \ 1046 ARCH_P2041 || \ 1047 ARCH_P3041 || \ 1048 ARCH_P4080 || \ 1049 ARCH_P5040 || \ 1050 ARCH_T1024 || \ 1051 ARCH_T1040 || \ 1052 ARCH_T1042 || \ 1053 ARCH_T2080 || \ 1054 ARCH_T4240 1055 default 0xe0000000 if ARCH_QEMU_E500 1056 help 1057 Default value of CCSRBAR comes from power-on-reset. It 1058 is fixed on each SoC. Some SoCs can have different value 1059 if changed by pre-boot regime. The value here must match 1060 the current value in SoC. If not sure, do not change. 1061 1062config SYS_DPAA_PME 1063 bool 1064 1065config SYS_DPAA_DCE 1066 bool 1067 1068config SYS_DPAA_RMAN 1069 bool 1070 1071config A003399_NOR_WORKAROUND 1072 bool 1073 help 1074 Enables a workaround for IFC erratum A003399. It is only required 1075 during NOR boot. 1076 1077config A008044_WORKAROUND 1078 bool 1079 help 1080 Enables a workaround for T1040/T1042 erratum A008044. It is only 1081 required during NAND boot and valid for Rev 1.0 SoC revision 1082 1083config SYS_FSL_ERRATUM_A004468 1084 bool 1085 1086config SYS_FSL_ERRATUM_A004477 1087 bool 1088 1089config SYS_FSL_ERRATUM_A004508 1090 bool 1091 1092config SYS_FSL_ERRATUM_A004580 1093 bool 1094 1095config SYS_FSL_ERRATUM_A004699 1096 bool 1097 1098config SYS_FSL_ERRATUM_A004849 1099 bool 1100 1101config SYS_FSL_ERRATUM_A004510 1102 bool 1103 1104config SYS_FSL_ERRATUM_A004510_SVR_REV 1105 hex 1106 depends on SYS_FSL_ERRATUM_A004510 1107 default 0x20 if ARCH_P4080 1108 default 0x10 1109 1110config SYS_FSL_ERRATUM_A004510_SVR_REV2 1111 hex 1112 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1113 default 0x11 1114 1115config SYS_FSL_ERRATUM_A005125 1116 bool 1117 1118config SYS_FSL_ERRATUM_A005434 1119 bool 1120 1121config SYS_FSL_ERRATUM_A005812 1122 bool 1123 1124config SYS_FSL_ERRATUM_A005871 1125 bool 1126 1127config SYS_FSL_ERRATUM_A005275 1128 bool 1129 1130config SYS_FSL_ERRATUM_A006261 1131 bool 1132 1133config SYS_FSL_ERRATUM_A006379 1134 bool 1135 1136config SYS_FSL_ERRATUM_A006384 1137 bool 1138 1139config SYS_FSL_ERRATUM_A006475 1140 bool 1141 1142config SYS_FSL_ERRATUM_A006593 1143 bool 1144 1145config SYS_FSL_ERRATUM_A007075 1146 bool 1147 1148config SYS_FSL_ERRATUM_A007186 1149 bool 1150 1151config SYS_FSL_ERRATUM_A007212 1152 bool 1153 1154config SYS_FSL_ERRATUM_A007815 1155 bool 1156 1157config SYS_FSL_ERRATUM_A007798 1158 bool 1159 1160config SYS_FSL_ERRATUM_A007907 1161 bool 1162 1163config SYS_FSL_ERRATUM_A008044 1164 bool 1165 select A008044_WORKAROUND if MTD_RAW_NAND 1166 1167config SYS_FSL_ERRATUM_CPC_A002 1168 bool 1169 1170config SYS_FSL_ERRATUM_CPC_A003 1171 bool 1172 1173config SYS_FSL_ERRATUM_CPU_A003999 1174 bool 1175 1176config SYS_FSL_ERRATUM_ELBC_A001 1177 bool 1178 1179config SYS_FSL_ERRATUM_I2C_A004447 1180 bool 1181 1182config SYS_FSL_A004447_SVR_REV 1183 hex 1184 depends on SYS_FSL_ERRATUM_I2C_A004447 1185 default 0x00 if ARCH_MPC8548 1186 default 0x10 if ARCH_P1010 1187 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1188 default 0x20 if ARCH_P3041 || ARCH_P4080 1189 1190config SYS_FSL_ERRATUM_IFC_A002769 1191 bool 1192 1193config SYS_FSL_ERRATUM_IFC_A003399 1194 bool 1195 1196config SYS_FSL_ERRATUM_NMG_CPU_A011 1197 bool 1198 1199config SYS_FSL_ERRATUM_NMG_ETSEC129 1200 bool 1201 1202config SYS_FSL_ERRATUM_NMG_LBC103 1203 bool 1204 1205config SYS_FSL_ERRATUM_P1010_A003549 1206 bool 1207 1208config SYS_FSL_ERRATUM_SATA_A001 1209 bool 1210 1211config SYS_FSL_ERRATUM_SEC_A003571 1212 bool 1213 1214config SYS_FSL_ERRATUM_SRIO_A004034 1215 bool 1216 1217config SYS_FSL_ERRATUM_USB14 1218 bool 1219 1220config SYS_P4080_ERRATUM_CPU22 1221 bool 1222 1223config SYS_P4080_ERRATUM_PCIE_A003 1224 bool 1225 1226config SYS_P4080_ERRATUM_SERDES8 1227 bool 1228 1229config SYS_P4080_ERRATUM_SERDES9 1230 bool 1231 1232config SYS_P4080_ERRATUM_SERDES_A001 1233 bool 1234 1235config SYS_P4080_ERRATUM_SERDES_A005 1236 bool 1237 1238config FSL_PCIE_DISABLE_ASPM 1239 bool 1240 1241config FSL_PCIE_RESET 1242 bool 1243 1244config SYS_PMAN 1245 bool 1246 1247config SYS_FSL_RAID_ENGINE 1248 bool 1249 1250config SYS_FSL_RMU 1251 bool 1252 1253config SYS_FSL_QORIQ_CHASSIS1 1254 bool 1255 1256config SYS_FSL_QORIQ_CHASSIS2 1257 bool 1258 1259config SYS_FSL_NUM_LAWS 1260 int "Number of local access windows" 1261 depends on FSL_LAW 1262 default 32 if ARCH_B4420 || \ 1263 ARCH_B4860 || \ 1264 ARCH_P2041 || \ 1265 ARCH_P3041 || \ 1266 ARCH_P4080 || \ 1267 ARCH_P5040 || \ 1268 ARCH_T2080 || \ 1269 ARCH_T4240 1270 default 16 if ARCH_T1024 || \ 1271 ARCH_T1040 || \ 1272 ARCH_T1042 1273 default 12 if ARCH_BSC9131 || \ 1274 ARCH_BSC9132 || \ 1275 ARCH_C29X || \ 1276 ARCH_MPC8536 || \ 1277 ARCH_P1010 || \ 1278 ARCH_P1011 || \ 1279 ARCH_P1020 || \ 1280 ARCH_P1021 || \ 1281 ARCH_P1023 || \ 1282 ARCH_P1024 || \ 1283 ARCH_P1025 || \ 1284 ARCH_P2020 1285 default 10 if ARCH_MPC8544 || \ 1286 ARCH_MPC8548 1287 default 8 if ARCH_MPC8540 || \ 1288 ARCH_MPC8560 1289 help 1290 Number of local access windows. This is fixed per SoC. 1291 If not sure, do not change. 1292 1293config SYS_FSL_CORES_PER_CLUSTER 1294 int 1295 depends on SYS_FSL_QORIQ_CHASSIS2 1296 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240 1297 default 2 if ARCH_B4420 1298 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 1299 1300config SYS_FSL_THREADS_PER_CORE 1301 int 1302 depends on SYS_FSL_QORIQ_CHASSIS2 1303 default 2 if E6500 1304 default 1 1305 1306config SYS_NUM_TLBCAMS 1307 int "Number of TLB CAM entries" 1308 default 64 if E500MC 1309 default 16 1310 help 1311 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1312 16 for other E500 SoCs. 1313 1314config L2_CACHE 1315 bool "Enable L2 cache support" 1316 1317if HETROGENOUS_CLUSTERS 1318 1319config SYS_MAPLE 1320 def_bool y 1321 1322config SYS_CPRI 1323 def_bool y 1324 1325config PPC_CLUSTER_START 1326 int 1327 default 0 1328 1329config DSP_CLUSTER_START 1330 int 1331 default 1 1332 1333config SYS_CPRI_CLK 1334 int 1335 default 3 1336 1337config SYS_ULB_CLK 1338 int 1339 default 4 1340 1341config SYS_ETVPE_CLK 1342 int 1343 default 1 1344 1345config MAX_DSP_CPUS 1346 int 1347 default 12 if ARCH_B4860 1348 default 2 if ARCH_B4420 1349endif 1350 1351config SYS_L2_SIZE_256KB 1352 bool 1353 1354config SYS_L2_SIZE_512KB 1355 bool 1356 1357config SYS_L2_SIZE 1358 int 1359 default 262144 if SYS_L2_SIZE_256KB 1360 default 524288 if SYS_L2_SIZE_512KB 1361 1362config BACKSIDE_L2_CACHE 1363 bool 1364 1365config SYS_L3_SIZE_256KB 1366 bool 1367 1368config SYS_L3_SIZE_512KB 1369 bool 1370 1371config SYS_L3_SIZE_1024KB 1372 bool 1373 1374config SYS_L3_SIZE 1375 int 1376 default 262144 if SYS_L3_SIZE_256KB 1377 default 524288 if SYS_L3_SIZE_512KB 1378 default 1048576 if SYS_L3_SIZE_512KB 1379 1380config SYS_PPC64 1381 bool 1382 1383config SYS_PPC_E500_USE_DEBUG_TLB 1384 bool 1385 1386config FSL_ELBC 1387 bool 1388 1389config SYS_PPC_E500_DEBUG_TLB 1390 int "Temporary TLB entry for external debugger" 1391 depends on SYS_PPC_E500_USE_DEBUG_TLB 1392 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1393 default 1 if ARCH_MPC8536 1394 default 2 if ARCH_P1011 || \ 1395 ARCH_P1020 || \ 1396 ARCH_P1021 || \ 1397 ARCH_P1024 || \ 1398 ARCH_P1025 || \ 1399 ARCH_P2020 1400 default 3 if ARCH_P1010 || \ 1401 ARCH_BSC9132 || \ 1402 ARCH_C29X 1403 help 1404 Select a temporary TLB entry to be used during boot to work 1405 around limitations in e500v1 and e500v2 external debugger 1406 support. This reduces the portions of the boot code where 1407 breakpoints and single stepping do not work. The value of this 1408 symbol should be set to the TLB1 entry to be used for this 1409 purpose. If unsure, do not change. 1410 1411config SYS_FSL_IFC_CLK_DIV 1412 int "Divider of platform clock" 1413 depends on FSL_IFC 1414 default 2 if ARCH_B4420 || \ 1415 ARCH_B4860 || \ 1416 ARCH_T1024 || \ 1417 ARCH_T1040 || \ 1418 ARCH_T1042 || \ 1419 ARCH_T4240 1420 default 1 1421 help 1422 Defines divider of platform clock(clock input to 1423 IFC controller). 1424 1425config SYS_FSL_LBC_CLK_DIV 1426 int "Divider of platform clock" 1427 depends on FSL_ELBC || ARCH_MPC8540 || \ 1428 ARCH_MPC8548 || \ 1429 ARCH_MPC8560 1430 1431 default 2 if ARCH_P2041 || \ 1432 ARCH_P3041 || \ 1433 ARCH_P4080 || \ 1434 ARCH_P5040 1435 default 1 1436 1437 help 1438 Defines divider of platform clock(clock input to 1439 eLBC controller). 1440 1441config ENABLE_36BIT_PHYS 1442 bool "Enable 36bit physical address space support" 1443 1444config SYS_BOOK3E_HV 1445 bool "Category E.HV is supported" 1446 depends on BOOKE 1447 1448config FSL_CORENET 1449 bool 1450 select SYS_FSL_CPC 1451 1452config FSL_NGPIXIS 1453 bool 1454 1455config SYS_CPC_REINIT_F 1456 bool 1457 help 1458 The CPC is configured as SRAM at the time of U-Boot entry and is 1459 required to be re-initialized. 1460 1461config SYS_FSL_CPC 1462 bool 1463 1464config SYS_CACHE_STASHING 1465 bool "Enable cache stashing" 1466 1467config SYS_FSL_PCIE_COMPAT_P4080_PCIE 1468 bool 1469 1470config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 1471 bool 1472 1473config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 1474 bool 1475 1476config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 1477 bool 1478 1479config SYS_FSL_PCIE_COMPAT 1480 string 1481 depends on FSL_CORENET 1482 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE 1483 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 1484 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 1485 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 1486 help 1487 Defines the string to utilize when trying to match PCIe device tree 1488 nodes for the given platform. 1489 1490config SYS_FSL_SINGLE_SOURCE_CLK 1491 bool 1492 1493config SYS_FSL_SRIO_LIODN 1494 bool 1495 1496config SYS_FSL_TBCLK_DIV 1497 int 1498 default 32 if ARCH_P2041 || ARCH_P3041 1499 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \ 1500 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \ 1501 ARCH_T1024 || ARCH_T2080 1502 default 8 1503 help 1504 Defines the core time base clock divider ratio compared to the system 1505 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can 1506 be 16 or 32. The ratio varies from SoC to Soc. 1507 1508config SYS_FSL_USB1_PHY_ENABLE 1509 bool 1510 1511config SYS_FSL_USB2_PHY_ENABLE 1512 bool 1513 1514config SYS_FSL_USB_DUAL_PHY_ENABLE 1515 bool 1516 1517config SYS_MPC85XX_NO_RESETVEC 1518 bool "Discard resetvec section and move bootpg section up" 1519 depends on MPC85xx && !MPC85XX_HAVE_RESET_VECTOR 1520 help 1521 If this variable is specified, the section .resetvec is not kept and 1522 the section .bootpg is placed in the previous 4k of the .text section. 1523 1524config SPL_SYS_MPC85XX_NO_RESETVEC 1525 bool "Discard resetvec section and move bootpg section up, in SPL" 1526 depends on MPC85xx && SPL && !MPC85XX_HAVE_RESET_VECTOR 1527 help 1528 If this variable is specified, the section .resetvec is not kept and 1529 the section .bootpg is placed in the previous 4k of the .text section, 1530 of the SPL portion of the binary. 1531 1532config TPL_SYS_MPC85XX_NO_RESETVEC 1533 bool "Discard resetvec section and move bootpg section up, in TPL" 1534 depends on MPC85xx && TPL && !MPC85XX_HAVE_RESET_VECTOR 1535 help 1536 If this variable is specified, the section .resetvec is not kept and 1537 the section .bootpg is placed in the previous 4k of the .text section, 1538 of the SPL portion of the binary. 1539 1540config FSL_VIA 1541 bool 1542 1543source "board/CZ.NIC/turris_1x/Kconfig" 1544source "board/emulation/qemu-ppce500/Kconfig" 1545source "board/freescale/mpc8548cds/Kconfig" 1546source "board/freescale/p1010rdb/Kconfig" 1547source "board/freescale/p1_p2_rdb_pc/Kconfig" 1548source "board/freescale/p2041rdb/Kconfig" 1549source "board/freescale/t102xrdb/Kconfig" 1550source "board/freescale/t104xrdb/Kconfig" 1551source "board/freescale/t208xqds/Kconfig" 1552source "board/freescale/t208xrdb/Kconfig" 1553source "board/freescale/t4rdb/Kconfig" 1554source "board/socrates/Kconfig" 1555 1556endmenu 1557