1if ARCH_SOCFPGA 2 3config ERR_PTR_OFFSET 4 default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range 5 6config NR_DRAM_BANKS 7 default 1 8 9config SOCFPGA_SECURE_VAB_AUTH 10 bool "Enable boot image authentication with Secure Device Manager" 11 depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \ 12 TARGET_SOCFPGA_AGILEX5 13 select FIT_IMAGE_POST_PROCESS 14 select SHA384 15 select SHA512 16 select SPL_FIT_IMAGE_POST_PROCESS 17 help 18 All images loaded from FIT will be authenticated by Secure Device 19 Manager. 20 21config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE 22 bool "Allow non-FIT VAB signed images" 23 depends on SOCFPGA_SECURE_VAB_AUTH 24 25config SPL_SIZE_LIMIT 26 default 0x10000 if TARGET_SOCFPGA_GEN5 27 28config SPL_SIZE_LIMIT_PROVIDE_STACK 29 default 0x200 if TARGET_SOCFPGA_GEN5 30 31config SPL_STACK_R_ADDR 32 default 0x00800000 if TARGET_SOCFPGA_GEN5 33 34config SPL_SYS_MALLOC_F 35 default y if TARGET_SOCFPGA_GEN5 36 37config SPL_SYS_MALLOC_F_LEN 38 default 0x800 if TARGET_SOCFPGA_GEN5 39 40config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 41 default 0xa2 42 43config SYS_MALLOC_F_LEN 44 default 0x2000 if TARGET_SOCFPGA_ARRIA10 45 default 0x2000 if TARGET_SOCFPGA_GEN5 46 47config TEXT_BASE 48 default 0x01000040 if TARGET_SOCFPGA_ARRIA10 49 default 0x01000040 if TARGET_SOCFPGA_GEN5 50 51config TARGET_SOCFPGA_AGILEX 52 bool 53 select ARMV8_MULTIENTRY 54 select ARMV8_SET_SMPEN 55 select BINMAN if SPL_ATF 56 select CLK 57 select FPGA_INTEL_SDM_MAILBOX 58 select GICV2 59 select NCORE_CACHE 60 select SPL_CLK if SPL 61 select TARGET_SOCFPGA_SOC64 62 63config TARGET_SOCFPGA_AGILEX7M 64 bool 65 select ARMV8_MULTIENTRY 66 select ARMV8_SET_SMPEN 67 select BINMAN if SPL_ATF 68 select CLK 69 select FPGA_INTEL_SDM_MAILBOX 70 select GICV2 71 select NCORE_CACHE 72 select SPL_CLK if SPL 73 select TARGET_SOCFPGA_SOC64 74 75config TARGET_SOCFPGA_AGILEX5 76 bool 77 select BINMAN if SPL_ATF 78 select CLK 79 select FPGA_INTEL_SDM_MAILBOX 80 select SPL_CLK if SPL 81 select TARGET_SOCFPGA_SOC64 82 83config TARGET_SOCFPGA_ARRIA5 84 bool 85 select TARGET_SOCFPGA_GEN5 86 87config TARGET_SOCFPGA_ARRIA10 88 bool 89 select GICV2 90 select SPL_ALTERA_SDRAM 91 select SPL_BOARD_INIT if SPL 92 select SPL_CACHE if SPL 93 select CLK 94 select SPL_CLK if SPL 95 select DM_I2C 96 select DM_RESET 97 select SPL_DM_RESET if SPL 98 select REGMAP 99 select SPL_REGMAP if SPL 100 select SYSCON 101 select SPL_SYSCON if SPL 102 select ETH_DESIGNWARE_SOCFPGA 103 imply FPGA_SOCFPGA 104 imply SPL_USE_TINY_PRINTF 105 106config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM 107 bool "Always reprogram Arria 10 FPGA" 108 depends on TARGET_SOCFPGA_ARRIA10 109 help 110 Arria 10 FPGA is only programmed during the cold boot. 111 This option forces the FPGA to be reprogrammed every reboot, 112 allowing to change the bitstream and apply it with warm reboot. 113 114config TARGET_SOCFPGA_CYCLONE5 115 bool 116 select TARGET_SOCFPGA_GEN5 117 118config TARGET_SOCFPGA_GEN5 119 bool 120 select SPL_ALTERA_SDRAM 121 imply FPGA_SOCFPGA 122 imply SPL_SIZE_LIMIT_SUBTRACT_GD 123 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC 124 imply SPL_STACK_R 125 imply SPL_SYS_MALLOC_SIMPLE 126 imply SPL_USE_TINY_PRINTF 127 128config TARGET_SOCFPGA_N5X 129 bool 130 select ARMV8_MULTIENTRY 131 select ARMV8_SET_SMPEN 132 select BINMAN if SPL_ATF 133 select CLK 134 select GICV2 135 select NCORE_CACHE 136 select SPL_ALTERA_SDRAM 137 select SPL_CLK if SPL 138 select TARGET_SOCFPGA_SOC64 139 140config TARGET_SOCFPGA_N5X_SOCDK 141 bool "Intel eASIC SoCDK (N5X)" 142 select TARGET_SOCFPGA_N5X 143 144config TARGET_SOCFPGA_SOC64 145 bool 146 147config TARGET_SOCFPGA_STRATIX10 148 bool 149 select ARMV8_MULTIENTRY 150 select ARMV8_SET_SMPEN 151 select BINMAN if SPL_ATF 152 select FPGA_INTEL_SDM_MAILBOX 153 select GICV2 154 select TARGET_SOCFPGA_SOC64 155 156choice 157 prompt "Altera SOCFPGA board select" 158 optional 159 160config TARGET_SOCFPGA_AGILEX_SOCDK 161 bool "Intel SOCFPGA SoCDK (Agilex)" 162 select TARGET_SOCFPGA_AGILEX 163 164config TARGET_SOCFPGA_AGILEX7M_SOCDK 165 bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" 166 select TARGET_SOCFPGA_AGILEX7M 167 168config TARGET_SOCFPGA_AGILEX5_SOCDK 169 bool "Intel SOCFPGA SoCDK (Agilex5)" 170 select TARGET_SOCFPGA_AGILEX5 171 172config TARGET_SOCFPGA_ARIES_MCVEVK 173 bool "Aries MCVEVK (Cyclone V)" 174 select TARGET_SOCFPGA_CYCLONE5 175 176config TARGET_SOCFPGA_ARRIA10_SOCDK 177 bool "Altera SOCFPGA SoCDK (Arria 10)" 178 select TARGET_SOCFPGA_ARRIA10 179 180config TARGET_SOCFPGA_ARRIA5_SECU1 181 bool "ABB SECU1 (Arria V)" 182 select TARGET_SOCFPGA_ARRIA5 183 select VENDOR_KM 184 185config TARGET_SOCFPGA_ARRIA5_SOCDK 186 bool "Altera SOCFPGA SoCDK (Arria V)" 187 select TARGET_SOCFPGA_ARRIA5 188 189config TARGET_SOCFPGA_CHAMELEONV3 190 bool "Google Chameleon v3 (Arria 10)" 191 select TARGET_SOCFPGA_ARRIA10 192 193config TARGET_SOCFPGA_CYCLONE5_SOCDK 194 bool "Altera SOCFPGA SoCDK (Cyclone V)" 195 select TARGET_SOCFPGA_CYCLONE5 196 197config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 198 bool "Devboards DBM-SoC1 (Cyclone V)" 199 select TARGET_SOCFPGA_CYCLONE5 200 201config TARGET_SOCFPGA_EBV_SOCRATES 202 bool "EBV SoCrates (Cyclone V)" 203 select TARGET_SOCFPGA_CYCLONE5 204 205config TARGET_SOCFPGA_IS1 206 bool "IS1 (Cyclone V)" 207 select TARGET_SOCFPGA_CYCLONE5 208 209config TARGET_SOCFPGA_SOFTING_VINING_FPGA 210 bool "Softing VIN|ING FPGA (Cyclone V)" 211 select BOARD_LATE_INIT 212 select TARGET_SOCFPGA_CYCLONE5 213 214config TARGET_SOCFPGA_SR1500 215 bool "SR1500 (Cyclone V)" 216 select TARGET_SOCFPGA_CYCLONE5 217 218config TARGET_SOCFPGA_STRATIX10_SOCDK 219 bool "Intel SOCFPGA SoCDK (Stratix 10)" 220 select TARGET_SOCFPGA_STRATIX10 221 222config TARGET_SOCFPGA_TERASIC_DE0_NANO 223 bool "Terasic DE0-Nano-Atlas (Cyclone V)" 224 select TARGET_SOCFPGA_CYCLONE5 225 226config TARGET_SOCFPGA_TERASIC_DE10_NANO 227 bool "Terasic DE10-Nano (Cyclone V)" 228 select TARGET_SOCFPGA_CYCLONE5 229 230config TARGET_SOCFPGA_TERASIC_DE10_STANDARD 231 bool "Terasic DE10-Standard (Cyclone V)" 232 select TARGET_SOCFPGA_CYCLONE5 233 234config TARGET_SOCFPGA_TERASIC_DE1_SOC 235 bool "Terasic DE1-SoC (Cyclone V)" 236 select TARGET_SOCFPGA_CYCLONE5 237 238config TARGET_SOCFPGA_TERASIC_SOCKIT 239 bool "Terasic SoCkit (Cyclone V)" 240 select TARGET_SOCFPGA_CYCLONE5 241 242endchoice 243 244config SYS_BOARD 245 default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK 246 default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK 247 default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK 248 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 249 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 250 default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3 251 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 252 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 253 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 254 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 255 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 256 default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD 257 default "is1" if TARGET_SOCFPGA_IS1 258 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 259 default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK 260 default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 261 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 262 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 263 default "sr1500" if TARGET_SOCFPGA_SR1500 264 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 265 default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA 266 267config SYS_VENDOR 268 default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK 269 default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK 270 default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK 271 default "intel" if TARGET_SOCFPGA_N5X_SOCDK 272 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 273 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 274 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 275 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK 276 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK 277 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 278 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 279 default "google" if TARGET_SOCFPGA_CHAMELEONV3 280 default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1 281 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA 282 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 283 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 284 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 285 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD 286 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 287 288config SYS_SOC 289 default "socfpga" 290 291config SYS_CONFIG_NAME 292 default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK 293 default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK 294 default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK 295 default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 296 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 297 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 298 default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3 299 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 300 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 301 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 302 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 303 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 304 default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD 305 default "socfpga_is1" if TARGET_SOCFPGA_IS1 306 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK 307 default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK 308 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 309 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 310 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 311 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 312 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA 313 314endif 315