1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
4  */
5 
6 /* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
7 #define CPU_STM32MP157Cxx	0x05000000
8 #define CPU_STM32MP157Axx	0x05000001
9 #define CPU_STM32MP153Cxx	0x05000024
10 #define CPU_STM32MP153Axx	0x05000025
11 #define CPU_STM32MP151Cxx	0x0500002E
12 #define CPU_STM32MP151Axx	0x0500002F
13 #define CPU_STM32MP157Fxx	0x05000080
14 #define CPU_STM32MP157Dxx	0x05000081
15 #define CPU_STM32MP153Fxx	0x050000A4
16 #define CPU_STM32MP153Dxx	0x050000A5
17 #define CPU_STM32MP151Fxx	0x050000AE
18 #define CPU_STM32MP151Dxx	0x050000AF
19 
20 #define CPU_STM32MP135Cxx	0x05010000
21 #define CPU_STM32MP135Axx	0x05010001
22 #define CPU_STM32MP133Cxx	0x050100C0
23 #define CPU_STM32MP133Axx	0x050100C1
24 #define CPU_STM32MP131Cxx	0x050106C8
25 #define CPU_STM32MP131Axx	0x050106C9
26 #define CPU_STM32MP135Fxx	0x05010800
27 #define CPU_STM32MP135Dxx	0x05010801
28 #define CPU_STM32MP133Fxx	0x050108C0
29 #define CPU_STM32MP133Dxx	0x050108C1
30 #define CPU_STM32MP131Fxx	0x05010EC8
31 #define CPU_STM32MP131Dxx	0x05010EC9
32 
33 /* ID for STM32MP23x = Device Part Number (RPN) (bit31:0) */
34 #define CPU_STM32MP235Cxx	0x00082182
35 #define CPU_STM32MP233Cxx	0x000B318E
36 #define CPU_STM32MP231Cxx	0x000B31EF
37 #define CPU_STM32MP235Axx	0x40082F82
38 #define CPU_STM32MP233Axx	0x400B3F8E
39 #define CPU_STM32MP231Axx	0x400B3FEF
40 #define CPU_STM32MP235Fxx	0x80082182
41 #define CPU_STM32MP233Fxx	0x800B318E
42 #define CPU_STM32MP231Fxx	0x800B31EF
43 #define CPU_STM32MP235Dxx	0xC0082F82
44 #define CPU_STM32MP233Dxx	0xC00B3F8E
45 #define CPU_STM32MP231Dxx	0xC00B3FEF
46 
47 /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
48 #define CPU_STM32MP257Cxx	0x00002000
49 #define CPU_STM32MP255Cxx	0x00082000
50 #define CPU_STM32MP253Cxx	0x000B2004
51 #define CPU_STM32MP251Cxx	0x000B3065
52 #define CPU_STM32MP257Axx	0x40002E00
53 #define CPU_STM32MP255Axx	0x40082E00
54 #define CPU_STM32MP253Axx	0x400B2E04
55 #define CPU_STM32MP251Axx	0x400B3E65
56 #define CPU_STM32MP257Fxx	0x80002000
57 #define CPU_STM32MP255Fxx	0x80082000
58 #define CPU_STM32MP253Fxx	0x800B2004
59 #define CPU_STM32MP251Fxx	0x800B3065
60 #define CPU_STM32MP257Dxx	0xC0002E00
61 #define CPU_STM32MP255Dxx	0xC0082E00
62 #define CPU_STM32MP253Dxx	0xC00B2E04
63 #define CPU_STM32MP251Dxx	0xC00B3E65
64 
65 /* return CPU_STMP32MP...Xxx constants */
66 u32 get_cpu_type(void);
67 
68 #define CPU_DEV_STM32MP15	0x500
69 #define CPU_DEV_STM32MP13	0x501
70 #define CPU_DEV_STM32MP23	0x505
71 #define CPU_DEV_STM32MP25	0x505
72 
73 /* return CPU_DEV constants */
74 u32 get_cpu_dev(void);
75 
76 /* Silicon revision = REV_ID[15:0] of Device Version */
77 #define CPU_REV1	0x1000
78 #define CPU_REV1_1	0x1001
79 #define CPU_REV1_2	0x1003
80 #define CPU_REV2	0x2000
81 #define CPU_REV2_1	0x2001
82 #define CPU_REV2_2	0x2003
83 
84 /* OTP revision ID = 6 bits : 3 for Major / 3 for Minor */
85 #define OTP_REVID_1	0b001000
86 #define OTP_REVID_1_1	0b001001
87 #define OTP_REVID_1_2	0b001010
88 #define OTP_REVID_2	0b010000
89 #define OTP_REVID_2_1	0b010001
90 #define OTP_REVID_2_2	0b010010
91 
92 /* return SoC revision = Silicon revision (STM32MP1) or OTP revision ID (STM32MP2)*/
93 u32 get_cpu_rev(void);
94 
95 /* Get Package options from OTP */
96 u32 get_cpu_package(void);
97 
98 /* package used for STM32MP15x */
99 #define STM32MP15_PKG_AA_LBGA448	4
100 #define STM32MP15_PKG_AB_LBGA354	3
101 #define STM32MP15_PKG_AC_TFBGA361	2
102 #define STM32MP15_PKG_AD_TFBGA257	1
103 #define STM32MP15_PKG_UNKNOWN		0
104 
105 /* package used for STM32MP23x */
106 #define STM32MP23_PKG_CUSTOM		0
107 #define STM32MP23_PKG_AL_VFBGA361	1
108 #define STM32MP23_PKG_AK_VFBGA424	3
109 #define STM32MP23_PKG_AJ_TFBGA361	7
110 
111 /* package used for STM32MP25x */
112 #define STM32MP25_PKG_CUSTOM		0
113 #define STM32MP25_PKG_AL_VFBGA361	1
114 #define STM32MP25_PKG_AK_VFBGA424	3
115 #define STM32MP25_PKG_AI_TFBGA436	5
116 #define STM32MP25_PKG_UNKNOWN		7
117 
118 /* Get SOC name */
119 #define SOC_NAME_SIZE 20
120 void get_soc_name(char name[SOC_NAME_SIZE]);
121 
122 /* return boot mode */
123 u32 get_bootmode(void);
124 
125 /* return auth status and partition */
126 u32 get_bootauth(void);
127 
128 int get_eth_nb(void);
129 int setup_mac_address(void);
130 int setup_serial_number(void);
131 
132 /* board power management : configure vddcore according OPP */
133 void board_vddcore_init(u32 voltage_mv);
134 
135 /* weak function */
136 void stm32mp_cpu_init(void);
137 void stm32mp_misc_init(void);
138 
139 /* helper function: read data from OTP */
140 u32 get_otp(int index, int shift, int mask);
141 
142 uintptr_t get_stm32mp_rom_api_table(void);
143 uintptr_t get_stm32mp_bl2_dtb(void);
144 
145 /* helper function: check "closed" state in product "Life Cycle" */
146 #ifdef CONFIG_CMD_STM32KEY
147 bool stm32mp_is_closed(void);
148 #else
stm32mp_is_closed(void)149 static inline bool stm32mp_is_closed(void) { return false; }
150 #endif
151