1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Author: Dipen Dudhat <dipen.dudhat@freescale.com> 5 */ 6 7 #ifndef __FSL_IFC_H 8 #define __FSL_IFC_H 9 10 #ifdef CONFIG_FSL_IFC 11 #include <config.h> 12 #include <part.h> 13 #ifdef CONFIG_ARM 14 #include <asm/arch/soc.h> 15 #else 16 #include <asm/ppc.h> 17 #endif 18 19 #define FSL_IFC_V1_1_0 0x01010000 20 #define FSL_IFC_V2_0_0 0x02000000 21 22 #ifdef CONFIG_SYS_FSL_IFC_LE 23 #define ifc_in32(a) in_le32(a) 24 #define ifc_out32(a, v) out_le32(a, v) 25 #define ifc_in16(a) in_le16(a) 26 #define ifc_out16(a, v) out_le16(a, v) 27 #elif defined(CONFIG_SYS_FSL_IFC_BE) 28 #define ifc_in32(a) in_be32(a) 29 #define ifc_out32(a, v) out_be32(a, v) 30 #define ifc_in16(a) in_be16(a) 31 #define ifc_out16(a, v) out_be16(a, v) 32 #else 33 #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined 34 #endif 35 36 /* 37 * CSPR - Chip Select Property Register 38 */ 39 #define CSPR_BA 0xFFFF0000 40 #define CSPR_BA_SHIFT 16 41 #define CSPR_PORT_SIZE 0x00000180 42 #define CSPR_PORT_SIZE_SHIFT 7 43 /* Port Size 8 bit */ 44 #define CSPR_PORT_SIZE_8 0x00000080 45 /* Port Size 16 bit */ 46 #define CSPR_PORT_SIZE_16 0x00000100 47 /* Port Size 32 bit */ 48 #define CSPR_PORT_SIZE_32 0x00000180 49 /* Write Protect */ 50 #define CSPR_WP 0x00000040 51 #define CSPR_WP_SHIFT 6 52 /* Machine Select */ 53 #define CSPR_MSEL 0x00000006 54 #define CSPR_MSEL_SHIFT 1 55 /* External Transceiver Enable */ 56 #define CSPR_TE 0x00000010 57 /* NOR */ 58 #define CSPR_MSEL_NOR 0x00000000 59 /* NAND */ 60 #define CSPR_MSEL_NAND 0x00000002 61 /* GPCM */ 62 #define CSPR_MSEL_GPCM 0x00000004 63 /* Bank Valid */ 64 #define CSPR_V 0x00000001 65 #define CSPR_V_SHIFT 0 66 67 /* Convert an address into the right format for the CSPR Registers */ 68 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) 69 70 /* 71 * Address Mask Register 72 */ 73 #define IFC_AMASK_MASK 0xFFFF0000 74 #define IFC_AMASK_SHIFT 16 75 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ 76 (LOG2(n) - IFC_AMASK_SHIFT)) 77 78 /* 79 * Chip Select Option Register IFC_NAND Machine 80 */ 81 /* Enable ECC Encoder */ 82 #define CSOR_NAND_ECC_ENC_EN 0x80000000 83 #define CSOR_NAND_ECC_MODE_MASK 0x30000000 84 /* 4 bit correction per 520 Byte sector */ 85 #define CSOR_NAND_ECC_MODE_4 0x00000000 86 /* 8 bit correction per 528 Byte sector */ 87 #define CSOR_NAND_ECC_MODE_8 0x10000000 88 /* Enable ECC Decoder */ 89 #define CSOR_NAND_ECC_DEC_EN 0x04000000 90 /* Row Address Length */ 91 #define CSOR_NAND_RAL_MASK 0x01800000 92 #define CSOR_NAND_RAL_SHIFT 20 93 #define CSOR_NAND_RAL_1 0x00000000 94 #define CSOR_NAND_RAL_2 0x00800000 95 #define CSOR_NAND_RAL_3 0x01000000 96 #define CSOR_NAND_RAL_4 0x01800000 97 /* Page Size 512b, 2k, 4k */ 98 #define CSOR_NAND_PGS_MASK 0x00180000 99 #define CSOR_NAND_PGS_SHIFT 16 100 #define CSOR_NAND_PGS_512 0x00000000 101 #define CSOR_NAND_PGS_2K 0x00080000 102 #define CSOR_NAND_PGS_4K 0x00100000 103 #define CSOR_NAND_PGS_8K 0x00180000 104 /* Spare region Size */ 105 #define CSOR_NAND_SPRZ_MASK 0x0000E000 106 #define CSOR_NAND_SPRZ_SHIFT 13 107 #define CSOR_NAND_SPRZ_16 0x00000000 108 #define CSOR_NAND_SPRZ_64 0x00002000 109 #define CSOR_NAND_SPRZ_128 0x00004000 110 #define CSOR_NAND_SPRZ_210 0x00006000 111 #define CSOR_NAND_SPRZ_218 0x00008000 112 #define CSOR_NAND_SPRZ_224 0x0000A000 113 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 114 /* Pages Per Block */ 115 #define CSOR_NAND_PB_MASK 0x00000700 116 #define CSOR_NAND_PB_SHIFT 8 117 #define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) 118 /* Time for Read Enable High to Output High Impedance */ 119 #define CSOR_NAND_TRHZ_MASK 0x0000001C 120 #define CSOR_NAND_TRHZ_SHIFT 2 121 #define CSOR_NAND_TRHZ_20 0x00000000 122 #define CSOR_NAND_TRHZ_40 0x00000004 123 #define CSOR_NAND_TRHZ_60 0x00000008 124 #define CSOR_NAND_TRHZ_80 0x0000000C 125 #define CSOR_NAND_TRHZ_100 0x00000010 126 /* Buffer control disable */ 127 #define CSOR_NAND_BCTLD 0x00000001 128 129 /* 130 * Chip Select Option Register - NOR Flash Mode 131 */ 132 /* Enable Address shift Mode */ 133 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 134 /* Page Read Enable from NOR device */ 135 #define CSOR_NOR_PGRD_EN 0x10000000 136 /* AVD Toggle Enable during Burst Program */ 137 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 138 /* Address Data Multiplexing Shift */ 139 #define CSOR_NOR_ADM_MASK 0x0003E000 140 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 141 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 142 /* Type of the NOR device hooked */ 143 #define CSOR_NOR_NOR_MODE_ASYNC_NOR 0x00000000 144 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 145 /* Time for Read Enable High to Output High Impedance */ 146 #define CSOR_NOR_TRHZ_MASK 0x0000001C 147 #define CSOR_NOR_TRHZ_SHIFT 2 148 #define CSOR_NOR_TRHZ_20 0x00000000 149 #define CSOR_NOR_TRHZ_40 0x00000004 150 #define CSOR_NOR_TRHZ_60 0x00000008 151 #define CSOR_NOR_TRHZ_80 0x0000000C 152 #define CSOR_NOR_TRHZ_100 0x00000010 153 /* Buffer control disable */ 154 #define CSOR_NOR_BCTLD 0x00000001 155 156 /* 157 * Chip Select Option Register - GPCM Mode 158 */ 159 /* GPCM Mode - Normal */ 160 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 161 /* GPCM Mode - GenericASIC */ 162 #define CSOR_GPCM_GPMODE_ASIC 0x80000000 163 /* Parity Mode odd/even */ 164 #define CSOR_GPCM_PARITY_EVEN 0x40000000 165 /* Parity Checking enable/disable */ 166 #define CSOR_GPCM_PAR_EN 0x20000000 167 /* GPCM Timeout Count */ 168 #define CSOR_GPCM_GPTO_MASK 0x0F000000 169 #define CSOR_GPCM_GPTO_SHIFT 24 170 #define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 171 /* GPCM External Access Termination mode for read access */ 172 #define CSOR_GPCM_RGETA_EXT 0x00080000 173 /* GPCM External Access Termination mode for write access */ 174 #define CSOR_GPCM_WGETA_EXT 0x00040000 175 /* Address Data Multiplexing Shift */ 176 #define CSOR_GPCM_ADM_MASK 0x0003E000 177 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 178 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 179 /* Generic ASIC Parity error indication delay */ 180 #define CSOR_GPCM_GAPERRD_MASK 0x00000180 181 #define CSOR_GPCM_GAPERRD_SHIFT 7 182 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 183 /* Time for Read Enable High to Output High Impedance */ 184 #define CSOR_GPCM_TRHZ_MASK 0x0000001C 185 #define CSOR_GPCM_TRHZ_20 0x00000000 186 #define CSOR_GPCM_TRHZ_40 0x00000004 187 #define CSOR_GPCM_TRHZ_60 0x00000008 188 #define CSOR_GPCM_TRHZ_80 0x0000000C 189 #define CSOR_GPCM_TRHZ_100 0x00000010 190 /* Buffer control disable */ 191 #define CSOR_GPCM_BCTLD 0x00000001 192 193 /* 194 * Flash Timing Registers (FTIM0 - FTIM2_CSn) 195 */ 196 /* 197 * FTIM0 - NAND Flash Mode 198 */ 199 #define FTIM0_NAND 0x7EFF3F3F 200 #define FTIM0_NAND_TCCST_SHIFT 25 201 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) 202 #define FTIM0_NAND_TWP_SHIFT 16 203 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) 204 #define FTIM0_NAND_TWCHT_SHIFT 8 205 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) 206 #define FTIM0_NAND_TWH_SHIFT 0 207 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) 208 /* 209 * FTIM1 - NAND Flash Mode 210 */ 211 #define FTIM1_NAND 0xFFFF3FFF 212 #define FTIM1_NAND_TADLE_SHIFT 24 213 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) 214 #define FTIM1_NAND_TWBE_SHIFT 16 215 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) 216 #define FTIM1_NAND_TRR_SHIFT 8 217 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) 218 #define FTIM1_NAND_TRP_SHIFT 0 219 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) 220 /* 221 * FTIM2 - NAND Flash Mode 222 */ 223 #define FTIM2_NAND 0x1FE1F8FF 224 #define FTIM2_NAND_TRAD_SHIFT 21 225 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) 226 #define FTIM2_NAND_TREH_SHIFT 11 227 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) 228 #define FTIM2_NAND_TWHRE_SHIFT 0 229 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) 230 /* 231 * FTIM3 - NAND Flash Mode 232 */ 233 #define FTIM3_NAND 0xFF000000 234 #define FTIM3_NAND_TWW_SHIFT 24 235 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) 236 237 /* 238 * FTIM0 - NOR Flash Mode 239 */ 240 #define FTIM0_NOR 0xF03F3F3F 241 #define FTIM0_NOR_TACSE_SHIFT 28 242 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) 243 #define FTIM0_NOR_TEADC_SHIFT 16 244 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) 245 #define FTIM0_NOR_TAVDS_SHIFT 8 246 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) 247 #define FTIM0_NOR_TEAHC_SHIFT 0 248 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) 249 /* 250 * FTIM1 - NOR Flash Mode 251 */ 252 #define FTIM1_NOR 0xFF003F3F 253 #define FTIM1_NOR_TACO_SHIFT 24 254 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) 255 #define FTIM1_NOR_TRAD_NOR_SHIFT 8 256 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) 257 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 258 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) 259 /* 260 * FTIM2 - NOR Flash Mode 261 */ 262 #define FTIM2_NOR 0x0F3CFCFF 263 #define FTIM2_NOR_TCS_SHIFT 24 264 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) 265 #define FTIM2_NOR_TCH_SHIFT 18 266 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) 267 #define FTIM2_NOR_TWPH_SHIFT 10 268 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) 269 #define FTIM2_NOR_TWP_SHIFT 0 270 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) 271 272 /* 273 * FTIM0 - Normal GPCM Mode 274 */ 275 #define FTIM0_GPCM 0xF03F3F3F 276 #define FTIM0_GPCM_TACSE_SHIFT 28 277 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) 278 #define FTIM0_GPCM_TEADC_SHIFT 16 279 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) 280 #define FTIM0_GPCM_TAVDS_SHIFT 8 281 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) 282 #define FTIM0_GPCM_TEAHC_SHIFT 0 283 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) 284 /* 285 * FTIM1 - Normal GPCM Mode 286 */ 287 #define FTIM1_GPCM 0xFF003F00 288 #define FTIM1_GPCM_TACO_SHIFT 24 289 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) 290 #define FTIM1_GPCM_TRAD_SHIFT 8 291 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) 292 /* 293 * FTIM2 - Normal GPCM Mode 294 */ 295 #define FTIM2_GPCM 0x0F3C00FF 296 #define FTIM2_GPCM_TCS_SHIFT 24 297 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) 298 #define FTIM2_GPCM_TCH_SHIFT 18 299 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) 300 #define FTIM2_GPCM_TWP_SHIFT 0 301 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) 302 303 /* 304 * Ready Busy Status Register (RB_STAT) 305 */ 306 /* CSn is READY */ 307 #define IFC_RB_STAT_READY_CS0 0x80000000 308 #define IFC_RB_STAT_READY_CS1 0x40000000 309 #define IFC_RB_STAT_READY_CS2 0x20000000 310 #define IFC_RB_STAT_READY_CS3 0x10000000 311 312 /* 313 * General Control Register (GCR) 314 */ 315 #define IFC_GCR_MASK 0x8000F800 316 /* reset all IFC hardware */ 317 #define IFC_GCR_SOFT_RST_ALL 0x80000000 318 /* Turnaroud Time of external buffer */ 319 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 320 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 321 322 /* 323 * Common Event and Error Status Register (CM_EVTER_STAT) 324 */ 325 /* Chip select error */ 326 #define IFC_CM_EVTER_STAT_CSER 0x80000000 327 328 /* 329 * Common Event and Error Enable Register (CM_EVTER_EN) 330 */ 331 /* Chip select error checking enable */ 332 #define IFC_CM_EVTER_EN_CSEREN 0x80000000 333 334 /* 335 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 336 */ 337 /* Chip select error interrupt enable */ 338 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 339 340 /* 341 * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 342 */ 343 /* transaction type of error Read/Write */ 344 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 345 #define IFC_CM_ERATTR0_ERAID 0x0FF00000 346 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 347 348 /* 349 * Clock Control Register (CCR) 350 */ 351 #define IFC_CCR_MASK 0x0F0F8800 352 /* Clock division ratio */ 353 #define IFC_CCR_CLK_DIV_MASK 0x0F000000 354 #define IFC_CCR_CLK_DIV_SHIFT 24 355 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 356 /* IFC Clock Delay */ 357 #define IFC_CCR_CLK_DLY_MASK 0x000F0000 358 #define IFC_CCR_CLK_DLY_SHIFT 16 359 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 360 /* Invert IFC clock before sending out */ 361 #define IFC_CCR_INV_CLK_EN 0x00008000 362 /* Fedback IFC Clock */ 363 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 364 365 /* 366 * Clock Status Register (CSR) 367 */ 368 /* Clk is stable */ 369 #define IFC_CSR_CLK_STAT_STABLE 0x80000000 370 371 /* 372 * IFC_NAND Machine Specific Registers 373 */ 374 /* 375 * NAND Configuration Register (NCFGR) 376 */ 377 /* Auto Boot Mode */ 378 #define IFC_NAND_NCFGR_BOOT 0x80000000 379 /* SRAM INIT EN */ 380 #define IFC_NAND_SRAM_INIT_EN 0x20000000 381 /* Addressing Mode-ROW0+n/COL0 */ 382 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 383 /* Addressing Mode-ROW0+n/COL0+n */ 384 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 385 /* Number of loop iterations of FIR sequences for multi page operations */ 386 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 387 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 388 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 389 /* Number of wait cycles */ 390 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 391 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 392 393 /* 394 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 395 */ 396 /* General purpose FCM flash command bytes CMD0-CMD7 */ 397 #define IFC_NAND_FCR0_CMD0 0xFF000000 398 #define IFC_NAND_FCR0_CMD0_SHIFT 24 399 #define IFC_NAND_FCR0_CMD1 0x00FF0000 400 #define IFC_NAND_FCR0_CMD1_SHIFT 16 401 #define IFC_NAND_FCR0_CMD2 0x0000FF00 402 #define IFC_NAND_FCR0_CMD2_SHIFT 8 403 #define IFC_NAND_FCR0_CMD3 0x000000FF 404 #define IFC_NAND_FCR0_CMD3_SHIFT 0 405 #define IFC_NAND_FCR1_CMD4 0xFF000000 406 #define IFC_NAND_FCR1_CMD4_SHIFT 24 407 #define IFC_NAND_FCR1_CMD5 0x00FF0000 408 #define IFC_NAND_FCR1_CMD5_SHIFT 16 409 #define IFC_NAND_FCR1_CMD6 0x0000FF00 410 #define IFC_NAND_FCR1_CMD6_SHIFT 8 411 #define IFC_NAND_FCR1_CMD7 0x000000FF 412 #define IFC_NAND_FCR1_CMD7_SHIFT 0 413 414 /* 415 * Flash ROW and COL Address Register (ROWn, COLn) 416 */ 417 /* Main/spare region locator */ 418 #define IFC_NAND_COL_MS 0x80000000 419 /* Column Address */ 420 #define IFC_NAND_COL_CA_MASK 0x00000FFF 421 422 /* 423 * NAND Flash Byte Count Register (NAND_BC) 424 */ 425 /* Byte Count for read/Write */ 426 #define IFC_NAND_BC 0x000001FF 427 428 /* 429 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 430 */ 431 /* NAND Machine specific opcodes OP0-OP14*/ 432 #define IFC_NAND_FIR0_OP0 0xFC000000 433 #define IFC_NAND_FIR0_OP0_SHIFT 26 434 #define IFC_NAND_FIR0_OP1 0x03F00000 435 #define IFC_NAND_FIR0_OP1_SHIFT 20 436 #define IFC_NAND_FIR0_OP2 0x000FC000 437 #define IFC_NAND_FIR0_OP2_SHIFT 14 438 #define IFC_NAND_FIR0_OP3 0x00003F00 439 #define IFC_NAND_FIR0_OP3_SHIFT 8 440 #define IFC_NAND_FIR0_OP4 0x000000FC 441 #define IFC_NAND_FIR0_OP4_SHIFT 2 442 #define IFC_NAND_FIR1_OP5 0xFC000000 443 #define IFC_NAND_FIR1_OP5_SHIFT 26 444 #define IFC_NAND_FIR1_OP6 0x03F00000 445 #define IFC_NAND_FIR1_OP6_SHIFT 20 446 #define IFC_NAND_FIR1_OP7 0x000FC000 447 #define IFC_NAND_FIR1_OP7_SHIFT 14 448 #define IFC_NAND_FIR1_OP8 0x00003F00 449 #define IFC_NAND_FIR1_OP8_SHIFT 8 450 #define IFC_NAND_FIR1_OP9 0x000000FC 451 #define IFC_NAND_FIR1_OP9_SHIFT 2 452 #define IFC_NAND_FIR2_OP10 0xFC000000 453 #define IFC_NAND_FIR2_OP10_SHIFT 26 454 #define IFC_NAND_FIR2_OP11 0x03F00000 455 #define IFC_NAND_FIR2_OP11_SHIFT 20 456 #define IFC_NAND_FIR2_OP12 0x000FC000 457 #define IFC_NAND_FIR2_OP12_SHIFT 14 458 #define IFC_NAND_FIR2_OP13 0x00003F00 459 #define IFC_NAND_FIR2_OP13_SHIFT 8 460 #define IFC_NAND_FIR2_OP14 0x000000FC 461 #define IFC_NAND_FIR2_OP14_SHIFT 2 462 463 /* 464 * Instruction opcodes to be programmed 465 * in FIR registers- 6bits 466 */ 467 enum ifc_nand_fir_opcodes { 468 IFC_FIR_OP_NOP, 469 IFC_FIR_OP_CA0, 470 IFC_FIR_OP_CA1, 471 IFC_FIR_OP_CA2, 472 IFC_FIR_OP_CA3, 473 IFC_FIR_OP_RA0, 474 IFC_FIR_OP_RA1, 475 IFC_FIR_OP_RA2, 476 IFC_FIR_OP_RA3, 477 IFC_FIR_OP_CMD0, 478 IFC_FIR_OP_CMD1, 479 IFC_FIR_OP_CMD2, 480 IFC_FIR_OP_CMD3, 481 IFC_FIR_OP_CMD4, 482 IFC_FIR_OP_CMD5, 483 IFC_FIR_OP_CMD6, 484 IFC_FIR_OP_CMD7, 485 IFC_FIR_OP_CW0, 486 IFC_FIR_OP_CW1, 487 IFC_FIR_OP_CW2, 488 IFC_FIR_OP_CW3, 489 IFC_FIR_OP_CW4, 490 IFC_FIR_OP_CW5, 491 IFC_FIR_OP_CW6, 492 IFC_FIR_OP_CW7, 493 IFC_FIR_OP_WBCD, 494 IFC_FIR_OP_RBCD, 495 IFC_FIR_OP_BTRD, 496 IFC_FIR_OP_RDSTAT, 497 IFC_FIR_OP_NWAIT, 498 IFC_FIR_OP_WFR, 499 IFC_FIR_OP_SBRD, 500 IFC_FIR_OP_UA, 501 IFC_FIR_OP_RB, 502 }; 503 504 /* 505 * NAND Chip Select Register (NAND_CSEL) 506 */ 507 #define IFC_NAND_CSEL 0x0C000000 508 #define IFC_NAND_CSEL_SHIFT 26 509 #define IFC_NAND_CSEL_CS0 0x00000000 510 #define IFC_NAND_CSEL_CS1 0x04000000 511 #define IFC_NAND_CSEL_CS2 0x08000000 512 #define IFC_NAND_CSEL_CS3 0x0C000000 513 514 /* 515 * NAND Operation Sequence Start (NANDSEQ_STRT) 516 */ 517 /* NAND Flash Operation Start */ 518 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 519 /* Automatic Erase */ 520 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 521 /* Automatic Program */ 522 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 523 /* Automatic Copyback */ 524 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 525 /* Automatic Read Operation */ 526 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 527 /* Automatic Status Read */ 528 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 529 530 /* 531 * NAND Event and Error Status Register (NAND_EVTER_STAT) 532 */ 533 /* Operation Complete */ 534 #define IFC_NAND_EVTER_STAT_OPC 0x80000000 535 /* Flash Timeout Error */ 536 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 537 /* Write Protect Error */ 538 #define IFC_NAND_EVTER_STAT_WPER 0x04000000 539 /* ECC Error */ 540 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 541 /* RCW Load Done */ 542 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 543 /* Boot Loadr Done */ 544 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 545 /* Bad Block Indicator search select */ 546 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 547 548 /* 549 * NAND Flash Page Read Completion Event Status Register 550 * (PGRDCMPL_EVT_STAT) 551 */ 552 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 553 /* Small Page 0-15 Done */ 554 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 555 /* Large Page(2K) 0-3 Done */ 556 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 557 /* Large Page(4K) 0-1 Done */ 558 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 559 560 /* 561 * NAND Event and Error Enable Register (NAND_EVTER_EN) 562 */ 563 /* Operation complete event enable */ 564 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 565 /* Page read complete event enable */ 566 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 567 /* Flash Timeout error enable */ 568 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 569 /* Write Protect error enable */ 570 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 571 /* ECC error logging enable */ 572 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 573 574 /* 575 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 576 */ 577 /* Enable interrupt for operation complete */ 578 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 579 /* Enable interrupt for Page read complete */ 580 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 581 /* Enable interrupt for Flash timeout error */ 582 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 583 /* Enable interrupt for Write protect error */ 584 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 585 /* Enable interrupt for ECC error*/ 586 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 587 588 /* 589 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 590 */ 591 #define IFC_NAND_ERATTR0_MASK 0x0C080000 592 /* Error on CS0-3 for NAND */ 593 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 594 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 595 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 596 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 597 /* Transaction type of error Read/Write */ 598 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 599 600 /* 601 * NAND Flash Status Register (NAND_FSR) 602 */ 603 /* First byte of data read from read status op */ 604 #define IFC_NAND_NFSR_RS0 0xFF000000 605 /* Second byte of data read from read status op */ 606 #define IFC_NAND_NFSR_RS1 0x00FF0000 607 608 /* 609 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 610 */ 611 /* Number of ECC errors on sector n (n = 0-15) */ 612 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 613 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 614 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 615 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 616 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 617 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 618 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 619 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 620 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 621 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 622 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 623 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 624 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 625 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 626 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 627 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 628 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 629 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 630 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 631 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 632 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 633 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 634 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 635 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 636 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 637 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 638 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 639 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 640 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 641 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 642 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 643 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 644 645 /* 646 * NAND Control Register (NANDCR) 647 */ 648 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 649 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 650 #define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 651 652 /* 653 * NAND_AUTOBOOT_TRGR 654 */ 655 /* Trigger RCW load */ 656 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 657 /* Trigget Auto Boot */ 658 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 659 660 /* 661 * NAND_MDR 662 */ 663 /* 1st read data byte when opcode SBRD */ 664 #define IFC_NAND_MDR_RDATA0 0xFF000000 665 /* 2nd read data byte when opcode SBRD */ 666 #define IFC_NAND_MDR_RDATA1 0x00FF0000 667 668 /* 669 * NOR Machine Specific Registers 670 */ 671 /* 672 * NOR Event and Error Status Register (NOR_EVTER_STAT) 673 */ 674 /* NOR Command Sequence Operation Complete */ 675 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 676 /* Write Protect Error */ 677 #define IFC_NOR_EVTER_STAT_WPER 0x04000000 678 /* Command Sequence Timeout Error */ 679 #define IFC_NOR_EVTER_STAT_STOER 0x01000000 680 681 /* 682 * NOR Event and Error Enable Register (NOR_EVTER_EN) 683 */ 684 /* NOR Command Seq complete event enable */ 685 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 686 /* Write Protect Error Checking Enable */ 687 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 688 /* Timeout Error Enable */ 689 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 690 691 /* 692 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 693 */ 694 /* Enable interrupt for OPC complete */ 695 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 696 /* Enable interrupt for write protect error */ 697 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 698 /* Enable interrupt for timeout error */ 699 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 700 701 /* 702 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 703 */ 704 /* Source ID for error transaction */ 705 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 706 /* AXI ID for error transation */ 707 #define IFC_NOR_ERATTR0_ERAID 0x000FF000 708 /* Chip select corresponds to NOR error */ 709 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 710 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 711 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 712 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 713 /* Type of transaction read/write */ 714 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 715 716 /* 717 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 718 */ 719 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 720 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 721 722 /* 723 * NOR Control Register (NORCR) 724 */ 725 #define IFC_NORCR_MASK 0x0F0F0000 726 /* No. of Address/Data Phase */ 727 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 728 #define IFC_NORCR_NUM_PHASE_SHIFT 24 729 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 730 /* Sequence Timeout Count */ 731 #define IFC_NORCR_STOCNT_MASK 0x000F0000 732 #define IFC_NORCR_STOCNT_SHIFT 16 733 #define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 734 735 /* 736 * GPCM Machine specific registers 737 */ 738 /* 739 * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 740 */ 741 /* Timeout error */ 742 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 743 /* Parity error */ 744 #define IFC_GPCM_EVTER_STAT_PER 0x01000000 745 746 /* 747 * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 748 */ 749 /* Timeout error enable */ 750 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 751 /* Parity error enable */ 752 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 753 754 /* 755 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 756 */ 757 /* Enable Interrupt for timeout error */ 758 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 759 /* Enable Interrupt for Parity error */ 760 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 761 762 /* 763 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 764 */ 765 /* Source ID for error transaction */ 766 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 767 /* AXI ID for error transaction */ 768 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 769 /* Chip select corresponds to GPCM error */ 770 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 771 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 772 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 773 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 774 /* Type of transaction read/Write */ 775 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 776 777 /* 778 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 779 */ 780 /* On which beat of address/data parity error is observed */ 781 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 782 /* Parity Error on byte */ 783 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 784 /* Parity Error reported in addr or data phase */ 785 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 786 787 /* 788 * GPCM Status Register (GPCM_STAT) 789 */ 790 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 791 792 #ifndef __ASSEMBLY__ 793 #include <asm/io.h> 794 795 extern void print_ifc_regs(void); 796 extern void init_early_memctl_regs(void); 797 void init_final_memctl_regs(void); 798 799 #define IFC_RREGS_4KOFFSET (4*1024) 800 #define IFC_RREGS_64KOFFSET (64*1024) 801 802 #define IFC_FCM_BASE_ADDR \ 803 ((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR) 804 805 #define get_ifc_cspr_ext(i) \ 806 ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext) 807 #define get_ifc_cspr(i) \ 808 ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr) 809 #define get_ifc_csor_ext(i) \ 810 ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext) 811 #define get_ifc_csor(i) \ 812 ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor) 813 #define get_ifc_amask(i) \ 814 ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask) 815 #define get_ifc_ftim(i, j) \ 816 ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]) 817 #define set_ifc_cspr_ext(i, v) \ 818 ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v) 819 #define set_ifc_cspr(i, v) \ 820 ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v) 821 #define set_ifc_csor_ext(i, v) \ 822 ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v) 823 #define set_ifc_csor(i, v) \ 824 ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v) 825 #define set_ifc_amask(i, v) \ 826 ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v) 827 #define set_ifc_ftim(i, j, v) \ 828 ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v) 829 830 enum ifc_chip_sel { 831 IFC_CS0, 832 IFC_CS1, 833 IFC_CS2, 834 IFC_CS3, 835 IFC_CS4, 836 IFC_CS5, 837 IFC_CS6, 838 IFC_CS7, 839 }; 840 841 enum ifc_ftims { 842 IFC_FTIM0, 843 IFC_FTIM1, 844 IFC_FTIM2, 845 IFC_FTIM3, 846 }; 847 848 /* 849 * IFC Controller NAND Machine registers 850 */ 851 struct fsl_ifc_nand { 852 u32 ncfgr; 853 u32 res1[0x4]; 854 u32 nand_fcr0; 855 u32 nand_fcr1; 856 u32 res2[0x8]; 857 u32 row0; 858 u32 res3; 859 u32 col0; 860 u32 res4; 861 u32 row1; 862 u32 res5; 863 u32 col1; 864 u32 res6; 865 u32 row2; 866 u32 res7; 867 u32 col2; 868 u32 res8; 869 u32 row3; 870 u32 res9; 871 u32 col3; 872 u32 res10[0x24]; 873 u32 nand_fbcr; 874 u32 res11; 875 u32 nand_fir0; 876 u32 nand_fir1; 877 u32 nand_fir2; 878 u32 res12[0x10]; 879 u32 nand_csel; 880 u32 res13; 881 u32 nandseq_strt; 882 u32 res14; 883 u32 nand_evter_stat; 884 u32 res15; 885 u32 pgrdcmpl_evt_stat; 886 u32 res16[0x2]; 887 u32 nand_evter_en; 888 u32 res17[0x2]; 889 u32 nand_evter_intr_en; 890 u32 nand_vol_addr_stat; 891 u32 res18; 892 u32 nand_erattr0; 893 u32 nand_erattr1; 894 u32 res19[0x10]; 895 u32 nand_fsr; 896 u32 res20[0x1]; 897 u32 nand_eccstat[8]; 898 u32 res21[0x1c]; 899 u32 nanndcr; 900 u32 res22[0x2]; 901 u32 nand_autoboot_trgr; 902 u32 res23; 903 u32 nand_mdr; 904 u32 res24[0x1c]; 905 u32 nand_dll_lowcfg0; 906 u32 nand_dll_lowcfg1; 907 u32 res25; 908 u32 nand_dll_lowstat; 909 u32 res26[0x3C]; 910 }; 911 912 /* 913 * IFC controller NOR Machine registers 914 */ 915 struct fsl_ifc_nor { 916 u32 nor_evter_stat; 917 u32 res1[0x2]; 918 u32 nor_evter_en; 919 u32 res2[0x2]; 920 u32 nor_evter_intr_en; 921 u32 res3[0x2]; 922 u32 nor_erattr0; 923 u32 nor_erattr1; 924 u32 nor_erattr2; 925 u32 res4[0x4]; 926 u32 norcr; 927 u32 res5[0xEF]; 928 }; 929 930 /* 931 * IFC controller GPCM Machine registers 932 */ 933 struct fsl_ifc_gpcm { 934 u32 gpcm_evter_stat; 935 u32 res1[0x2]; 936 u32 gpcm_evter_en; 937 u32 res2[0x2]; 938 u32 gpcm_evter_intr_en; 939 u32 res3[0x2]; 940 u32 gpcm_erattr0; 941 u32 gpcm_erattr1; 942 u32 gpcm_erattr2; 943 u32 gpcm_stat; 944 }; 945 946 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT 947 #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) 948 #define IFC_CSPR_REG_LEN 148 949 #define IFC_AMASK_REG_LEN 144 950 #define IFC_CSOR_REG_LEN 144 951 #define IFC_FTIM_REG_LEN 576 952 953 #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ 954 CONFIG_SYS_FSL_IFC_BANK_COUNT 955 #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ 956 CONFIG_SYS_FSL_IFC_BANK_COUNT 957 #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ 958 CONFIG_SYS_FSL_IFC_BANK_COUNT 959 #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ 960 CONFIG_SYS_FSL_IFC_BANK_COUNT 961 #else 962 #error IFC BANK count not vaild 963 #endif 964 #else 965 #error IFC BANK count not defined 966 #endif 967 968 struct fsl_ifc_cspr { 969 u32 cspr_ext; 970 u32 cspr; 971 u32 res; 972 }; 973 974 struct fsl_ifc_amask { 975 u32 amask; 976 u32 res[0x2]; 977 }; 978 979 struct fsl_ifc_csor { 980 u32 csor; 981 u32 csor_ext; 982 u32 res; 983 }; 984 985 struct fsl_ifc_ftim { 986 u32 ftim[4]; 987 u32 res[0x8]; 988 }; 989 990 /* 991 * IFC Controller Global Registers 992 * FCM - Flash control machine 993 */ 994 995 struct fsl_ifc_fcm { 996 u32 ifc_rev; 997 u32 res1[0x2]; 998 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 999 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; 1000 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 1001 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; 1002 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 1003 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; 1004 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 1005 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; 1006 u32 rb_stat; 1007 u32 rb_map; 1008 u32 wp_map; 1009 u32 ifc_gcr; 1010 u32 res7[0x2]; 1011 u32 cm_evter_stat; 1012 u32 res8[0x2]; 1013 u32 cm_evter_en; 1014 u32 res9[0x2]; 1015 u32 cm_evter_intr_en; 1016 u32 res10[0x2]; 1017 u32 cm_erattr0; 1018 u32 cm_erattr1; 1019 u32 res11[0x2]; 1020 u32 ifc_ccr; 1021 u32 ifc_csr; 1022 u32 ddr_ccr_low; 1023 }; 1024 1025 struct fsl_ifc_runtime { 1026 struct fsl_ifc_nand ifc_nand; 1027 struct fsl_ifc_nor ifc_nor; 1028 struct fsl_ifc_gpcm ifc_gpcm; 1029 }; 1030 1031 struct fsl_ifc { 1032 struct fsl_ifc_fcm *gregs; 1033 struct fsl_ifc_runtime *rregs; 1034 }; 1035 1036 struct ifc_regs { 1037 const char *name; 1038 u32 pr; 1039 u32 pr_ext; 1040 u32 amask; 1041 u32 or; 1042 u32 ftim[4]; 1043 u32 or_ext; 1044 u32 pr_final; 1045 u32 amask_final; 1046 }; 1047 1048 struct ifc_regs_info { 1049 struct ifc_regs *regs; 1050 u32 cs_size; 1051 }; 1052 1053 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1054 #undef CSPR_MSEL_NOR 1055 #define CSPR_MSEL_NOR CSPR_MSEL_GPCM 1056 #endif 1057 #endif /* CONFIG_FSL_IFC */ 1058 1059 #endif /* __ASSEMBLY__ */ 1060 #endif /* __FSL_IFC_H */ 1061