1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * hardware.h
4  *
5  * hardware specific header
6  *
7  * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
8  */
9 
10 #ifndef __AM33XX_HARDWARE_H
11 #define __AM33XX_HARDWARE_H
12 
13 #include <config.h>
14 #include <asm/arch/omap.h>
15 #ifdef CONFIG_AM33XX
16 #include <asm/arch/hardware_am33xx.h>
17 #elif defined(CONFIG_AM43XX)
18 #include <asm/arch/hardware_am43xx.h>
19 #endif
20 
21 /*
22  * Common hardware definitions
23  */
24 
25 /* DM Timer base addresses */
26 #define DM_TIMER0_BASE			0x4802C000
27 #define DM_TIMER1_BASE			0x4802E000
28 #define DM_TIMER2_BASE			0x48040000
29 #define DM_TIMER3_BASE			0x48042000
30 #define DM_TIMER4_BASE			0x48044000
31 #define DM_TIMER5_BASE			0x48046000
32 #define DM_TIMER6_BASE			0x48048000
33 #define DM_TIMER7_BASE			0x4804A000
34 
35 /* GPIO Base address */
36 #define GPIO0_BASE			0x48032000
37 #define GPIO1_BASE			0x4804C000
38 
39 /* BCH Error Location Module */
40 #define ELM_BASE			0x48080000
41 
42 /* EMIF Base address */
43 #define EMIF4_0_CFG_BASE		0x4C000000
44 #define EMIF4_1_CFG_BASE		0x4D000000
45 
46 /* DDR Base address */
47 #define DDR_CTRL_ADDR			0x44E10E04
48 #define DDR_CONTROL_BASE_ADDR		0x44E11404
49 
50 /* UART */
51 #if CONFIG_CONS_INDEX == 1
52 #	define DEFAULT_UART_BASE UART0_BASE
53 #elif CONFIG_CONS_INDEX == 2
54 #	define DEFAULT_UART_BASE UART1_BASE
55 #elif CONFIG_CONS_INDEX == 3
56 #	define DEFAULT_UART_BASE UART2_BASE
57 #elif CONFIG_CONS_INDEX == 4
58 #	define DEFAULT_UART_BASE UART3_BASE
59 #elif CONFIG_CONS_INDEX == 5
60 #	define DEFAULT_UART_BASE UART4_BASE
61 #elif CONFIG_CONS_INDEX == 6
62 #	define DEFAULT_UART_BASE UART5_BASE
63 #endif
64 
65 /* GPMC Base address */
66 #define GPMC_BASE			0x50000000
67 
68 /* CPSW Config space */
69 #define CPSW_BASE			0x4A100000
70 
71 /* Control status register */
72 #define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
73 #define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31
74 #define CTRL_CRYSTAL_FREQ_SELECTION_MASK	(0x3 << 29)
75 #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT	29
76 #define CTRL_SYSBOOT_15_14_MASK			(0x3 << 22)
77 #define CTRL_SYSBOOT_15_14_SHIFT		22
78 
79 #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT		0x0
80 #define CTRL_CRYSTAL_FREQ_SRC_EFUSE		0x1
81 
82 #define NUM_CRYSTAL_FREQ			0x4
83 
84 int clk_get(int clk);
85 #endif /* __AM33XX_HARDWARE_H */
86