1config ARCH_MAP_SYSMEM
2	depends on SANDBOX
3	def_bool y
4
5config CREATE_ARCH_SYMLINK
6	bool
7
8config HAVE_ARCH_IOREMAP
9	bool
10
11config HAVE_SETJMP
12	bool
13	help
14	 The architecture supports setjmp() and longjmp().
15
16config HAVE_INITJMP
17	bool
18	depends on HAVE_SETJMP
19	help
20	 The architecture supports initjmp(), a non-standard companion to
21	 setjmp() and longjmp().
22
23config SUPPORT_BIG_ENDIAN
24	bool
25
26config SUPPORT_LITTLE_ENDIAN
27	bool
28	default y if !SUPPORT_BIG_ENDIAN
29
30config SYS_CACHE_SHIFT_4
31	bool
32
33config SYS_CACHE_SHIFT_5
34	bool
35
36config SYS_CACHE_SHIFT_6
37	bool
38
39config SYS_CACHE_SHIFT_7
40	bool
41
42config 32BIT
43	bool
44
45config 64BIT
46	bool
47	help
48	  Indicates that U-Boot proper will be built for a 64 bit
49	  architecture.
50
51config SPL_64BIT
52	bool
53	help
54	  Indicates that SPL will be built for a 64 bit architecture.
55
56config SYS_CACHELINE_SIZE
57	int
58	default 128 if SYS_CACHE_SHIFT_7
59	default 64 if SYS_CACHE_SHIFT_6
60	default 32 if SYS_CACHE_SHIFT_5
61	default 16 if SYS_CACHE_SHIFT_4
62	# Fall-back for MIPS and RISC-V
63	default 64 if RISCV
64	default 32 if MIPS
65
66config SYS_DTC_PAD_BYTES
67	int "Size in bytes to pad device tree blob"
68	default 32768 if X86 && EFI_APP
69	default 4096 if ARC || ARM64 || M68K || MICROBLAZE || NIOS2 \
70		|| RISCV || SANDBOX || X86
71	default 0
72
73config LINKER_LIST_ALIGN
74	int
75	default 32 if SANDBOX
76	default 8 if ARM64 || X86
77	default 4
78	help
79	  Force the each linker list to be aligned to this boundary. This
80	  is required if ll_entry_get() is used, since otherwise the linker
81	  may add padding into the table, thus breaking it.
82	  See linker_lists.rst for full details.
83
84choice
85	prompt "Architecture select"
86	default SANDBOX
87
88config ARC
89	bool "ARC architecture"
90	select ARC_TIMER
91	select CLK
92	select DM
93	select HAVE_PRIVATE_LIBGCC
94	select SUPPORT_OF_CONTROL
95	select SYS_CACHE_SHIFT_7
96	select TIMER
97	select SUPPORT_BIG_ENDIAN
98	select SUPPORT_LITTLE_ENDIAN
99	select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
100	select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
101
102config ARM
103	bool "ARM architecture"
104	select HAVE_SETJMP
105	select HAVE_INITJMP
106	select ARCH_SUPPORTS_LTO
107	select CREATE_ARCH_SYMLINK
108	select HAVE_PRIVATE_LIBGCC if !ARM64
109	select SUPPORT_ACPI
110	select SUPPORT_LITTLE_ENDIAN
111	select SUPPORT_OF_CONTROL
112
113config M68K
114	bool "M68000 architecture"
115	select HAVE_PRIVATE_LIBGCC
116	select USE_PRIVATE_LIBGCC
117	select SYS_BOOT_GET_CMDLINE
118	select SYS_BOOT_GET_KBD
119	select SYS_CACHE_SHIFT_4
120	select SUPPORT_BIG_ENDIAN
121	select SUPPORT_OF_CONTROL
122
123config MICROBLAZE
124	bool "MicroBlaze architecture"
125	select SUPPORT_BIG_ENDIAN
126	select SUPPORT_LITTLE_ENDIAN
127	select SUPPORT_OF_CONTROL
128	imply CMD_TIMER
129	imply SPL_REGMAP if SPL
130	imply SPL_TIMER if SPL
131	imply TIMER
132	imply XILINX_TIMER
133
134config MIPS
135	bool "MIPS architecture"
136	select HAVE_ARCH_IOREMAP
137	select HAVE_PRIVATE_LIBGCC
138	select SUPPORT_OF_CONTROL
139	select SPL_SEPARATE_BSS if SPL
140
141config NIOS2
142	bool "Nios II architecture"
143	select CPU
144	select DM
145	select DM_EVENT
146	select OF_CONTROL
147	select SUPPORT_LITTLE_ENDIAN
148	select SUPPORT_OF_CONTROL
149	imply CMD_DM
150
151config PPC
152	bool "PowerPC architecture"
153	select HAVE_PRIVATE_LIBGCC
154	select SUPPORT_BIG_ENDIAN
155	select SUPPORT_OF_CONTROL
156	select SYS_BOOT_GET_CMDLINE
157	select SYS_BOOT_GET_KBD
158
159config RISCV
160	bool "RISC-V architecture"
161	select CREATE_ARCH_SYMLINK
162	select HAVE_SETJMP
163	select HAVE_INITJMP
164	select SUPPORT_ACPI
165	select SUPPORT_LITTLE_ENDIAN
166	select SUPPORT_OF_CONTROL
167	select OF_CONTROL
168	select DM
169	select DM_EVENT
170	imply SPL_SEPARATE_BSS if SPL
171	imply DM_SERIAL
172	imply DM_MMC
173	imply DM_SPI
174	imply DM_SPI_FLASH
175	imply BLK
176	imply CLK
177	imply MTD
178	imply TIMER
179	imply CMD_DM
180	imply SPL_DM
181	imply SPL_OF_CONTROL
182	imply SPL_LIBCOMMON_SUPPORT
183	imply SPL_LIBGENERIC_SUPPORT
184	imply SPL_SERIAL
185	imply SPL_TIMER
186
187config SANDBOX
188	bool "Sandbox"
189	select HAVE_SETJMP
190	select HAVE_INITJMP
191	select ARCH_SUPPORTS_LTO
192	select BOARD_LATE_INIT
193	select BZIP2
194	select CMD_POWEROFF if CMDLINE
195	select DM
196	select DM_EVENT
197	select DM_FUZZING_ENGINE
198	select DM_GPIO
199	select DM_I2C
200	select DM_KEYBOARD
201	select DM_SERIAL
202	select DM_SPI
203	select DM_SPI_FLASH
204	select GZIP_COMPRESSED
205	select IO_TRACE
206	select LZO
207	select MMC
208	select MTD
209	select OF_BOARD_SETUP
210	select PCI_ENDPOINT
211	select SPI
212	select SUPPORT_OF_CONTROL
213	select SUPPORT_BIG_ENDIAN
214	select SUPPORT_LITTLE_ENDIAN
215	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
216	select SYS_CACHE_SHIFT_4
217	select IRQ
218	select SUPPORT_EXTENSION_SCAN if CMDLINE
219	select SUPPORT_ACPI
220	imply BITREVERSE
221	select BLOBLIST
222	imply LTO
223	imply CMD_BOOTEFI_SELFTEST
224	imply CMD_DM
225	imply CMD_EXCEPTION
226	imply CMD_GETTIME
227	imply CMD_HASH
228	imply CMD_IO
229	imply CMD_IOTRACE
230	imply CMD_LZMADEC
231	imply CMD_SF
232	imply CMD_SF_TEST
233	imply CRC32_VERIFY
234	imply FAT_WRITE
235	imply FIRMWARE
236	imply FUZZING_ENGINE_SANDBOX
237	imply HASH_VERIFY
238	imply LZMA
239	imply TEE
240	imply AVB_VERIFY
241	imply LIBAVB
242	imply CMD_AVB
243	imply PARTITION_TYPE_GUID
244	imply SCP03
245	imply CMD_SCP03
246	imply UDP_FUNCTION_FASTBOOT
247	imply VIRTIO_MMIO
248	imply VIRTIO_PCI
249	imply VIRTIO_SANDBOX
250	# Re-enable this when fully implemented
251	# imply VIRTIO_BLK
252	imply VIRTIO_NET
253	imply DM_SOUND
254	imply PCI_SANDBOX_EP
255	imply PCH
256	imply PHYLIB
257	imply DM_MDIO
258	imply DM_MDIO_MUX
259	imply ACPI
260	imply ACPI_PMC
261	imply ACPI_PMC_SANDBOX
262	imply CMD_PMC
263	imply CMD_CLONE
264	imply SILENT_CONSOLE
265	imply BOOTARGS_SUBST
266	imply PHY_FIXED
267	imply DM_DSA
268	imply CMD_EXTENSION
269	imply KEYBOARD
270	imply PHYSMEM
271	imply GENERATE_ACPI_TABLE
272	imply BINMAN
273	imply CMD_MBR
274	imply CMD_MMC
275	imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
276	imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
277	imply CMD_SYSBOOT if BOOTSTD_FULL
278
279config SH
280	bool "SuperH architecture"
281	select SUPPORT_LITTLE_ENDIAN
282	select HAVE_PRIVATE_LIBGCC
283	select SUPPORT_OF_CONTROL
284
285config X86
286	bool "x86 architecture"
287	select HAVE_SETJMP
288	select SUPPORT_SPL
289	select SUPPORT_TPL
290	select SUPPORT_LITTLE_ENDIAN
291	select CREATE_ARCH_SYMLINK
292	select DM
293	select HAVE_ARCH_IOMAP
294	select HAVE_PRIVATE_LIBGCC
295	select OF_CONTROL
296	select PCI
297	select SUPPORT_ACPI
298	select SUPPORT_OF_CONTROL
299	select SYS_CACHE_SHIFT_6
300	select TIMER
301	select USE_PRIVATE_LIBGCC
302	select X86_TSC_TIMER
303	select IRQ
304	imply HAS_ROM if X86_RESET_VECTOR
305	imply BLK
306	imply CMD_DM
307	imply CMD_FPGA_LOADMK
308	imply CMD_GETTIME
309	imply CMD_IO
310	imply CMD_IRQ
311	imply CMD_PCI
312	imply CMD_SF
313	imply CMD_SF_TEST
314	imply DM_GPIO
315	imply DM_KEYBOARD
316	imply DM_MMC
317	imply DM_RTC
318	imply SCSI
319	imply DM_SERIAL
320	imply MTD
321	imply DM_SPI
322	imply DM_SPI_FLASH
323	imply DM_USB
324	imply LAST_STAGE_INIT
325	imply VIDEO
326	imply SYSRESET
327	imply SPL_SYSRESET
328	imply SYSRESET_X86
329	imply USB_ETHER_ASIX
330	imply USB_ETHER_SMSC95XX
331	imply USB_HOST_ETHER
332	imply PCH
333	imply PHYSMEM
334	imply RTC_MC146818
335	imply ACPI
336	imply ACPIGEN if !QEMU && !EFI_APP
337	imply SYSINFO if GENERATE_SMBIOS_TABLE
338	imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
339	imply TIMESTAMP
340
341	# Thing to enable for when SPL/TPL are enabled: SPL
342	imply SPL_DM
343	imply SPL_OF_LIBFDT
344	imply SPL_DRIVERS_MISC
345	imply SPL_GPIO
346	imply SPL_PINCTRL
347	imply SPL_LIBCOMMON_SUPPORT
348	imply SPL_LIBGENERIC_SUPPORT
349	imply SPL_SERIAL
350	imply SPL_SPI_FLASH_SUPPORT
351	imply SPL_SPI
352	imply SPL_OF_CONTROL
353	imply SPL_TIMER
354	imply SPL_REGMAP
355	imply SPL_SYSCON
356	# TPL
357	imply TPL_DM
358	imply TPL_DRIVERS_MISC
359	imply TPL_GPIO
360	imply TPL_PINCTRL
361	imply TPL_LIBCOMMON_SUPPORT
362	imply TPL_LIBGENERIC_SUPPORT
363	imply TPL_SERIAL
364	imply TPL_OF_CONTROL
365	imply TPL_TIMER
366	imply TPL_REGMAP
367	imply TPL_SYSCON
368
369config XTENSA
370	bool "Xtensa architecture"
371	select CREATE_ARCH_SYMLINK
372	select SUPPORT_LITTLE_ENDIAN
373	select SUPPORT_OF_CONTROL
374
375endchoice
376
377config SYS_ARCH
378	string
379	help
380	  This option should contain the architecture name to build the
381	  appropriate arch/<CONFIG_SYS_ARCH> directory.
382	  All the architectures should specify this option correctly.
383
384config SYS_CPU
385	string
386	help
387	  This option should contain the CPU name to build the correct
388	  arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
389
390	  This is optional.  For those targets without the CPU directory,
391	  leave this option empty.
392
393config SYS_SOC
394	string
395	help
396	  This option should contain the SoC name to build the directory
397	  arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
398
399	  This is optional.  For those targets without the SoC directory,
400	  leave this option empty.
401
402config SYS_VENDOR
403	string
404	help
405	  This option should contain the vendor name of the target board.
406	  If it is set and
407	  board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
408	  directory is compiled.
409	  If CONFIG_SYS_BOARD is also set, the sources under
410	  board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
411
412	  This is optional.  For those targets without the vendor directory,
413	  leave this option empty.
414
415config SYS_BOARD
416	string
417	help
418	  This option should contain the name of the target board.
419	  If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
420	  or board/<CONFIG_SYS_BOARD> directory is compiled depending on
421	  whether CONFIG_SYS_VENDOR is set or not.
422
423	  This is optional.  For those targets without the board directory,
424	  leave this option empty.
425
426config SYS_CONFIG_NAME
427	string "Board header file" if ARCH_MESON || ARCH_VERSAL || \
428		ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \
429		ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2
430	default "meson64" if ARCH_MESON
431	default "microblaze-generic" if MICROBLAZE
432	default "xilinx_versal" if ARCH_VERSAL
433	default "xilinx_versal_net" if ARCH_VERSAL_NET
434	default "xilinx_zynqmp" if ARCH_ZYNQMP
435	default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5
436	default "zynq-common" if ARCH_ZYNQ
437	help
438	  This option should contain the base name of board header file.
439	  The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
440	  should be included from include/config.h.
441
442config SYS_DISABLE_DCACHE_OPS
443	bool
444	help
445	 This option disables dcache flush and dcache invalidation
446	 operations. For example, on coherent systems where cache
447	 operatios are not required, enable this option to avoid them.
448	 Note that, its up to the individual architectures to implement
449	 this functionality.
450
451config SYS_IMMR
452	hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
453	depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
454	default 0xFF000000 if MPC8xx
455	default 0xF0000000 if ARCH_MPC8313
456	default 0xE0000000 if MPC83xx && !ARCH_MPC8313
457	default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
458	default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
459			      ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
460			      ARCH_P2020
461	default SYS_CCSRBAR_DEFAULT
462	help
463	  Address for the Internal Memory-Mapped Registers (IMMR) window used
464	  to configure the features of many Freescale / NXP SoCs.
465
466config MONITOR_IS_IN_RAM
467	bool "U-Boot is loaded in to RAM by a pre-loader"
468	depends on M68K || NIOS2
469
470menu "Skipping low level initialization functions"
471	depends on ARM || MIPS || RISCV
472
473config SKIP_LOWLEVEL_INIT
474	bool "Skip calls to certain low level initialization functions"
475	help
476	  If enabled, then certain low level initializations (like setting up
477	  the memory controller) are omitted and/or U-Boot does not relocate
478	  itself into RAM.
479	  Normally this variable MUST NOT be defined. The only exception is
480	  when U-Boot is loaded (to RAM) by some other boot loader or by a
481	  debugger which performs these initializations itself.
482
483config SPL_SKIP_LOWLEVEL_INIT
484	bool "Skip calls to certain low level initialization functions in SPL"
485	depends on SPL
486	help
487	  If enabled, then certain low level initializations (like setting up
488	  the memory controller) are omitted and/or U-Boot does not relocate
489	  itself into RAM.
490	  Normally this variable MUST NOT be defined. The only exception is
491	  when U-Boot is loaded (to RAM) by some other boot loader or by a
492	  debugger which performs these initializations itself.
493
494config TPL_SKIP_LOWLEVEL_INIT
495	bool "Skip calls to certain low level initialization functions in TPL"
496	depends on SPL && ARM
497	help
498	  If enabled, then certain low level initializations (like setting up
499	  the memory controller) are omitted and/or U-Boot does not relocate
500	  itself into RAM.
501	  Normally this variable MUST NOT be defined. The only exception is
502	  when U-Boot is loaded (to RAM) by some other boot loader or by a
503	  debugger which performs these initializations itself.
504
505config SKIP_LOWLEVEL_INIT_ONLY
506	bool "Skip call to lowlevel_init during early boot ONLY"
507	depends on ARM
508	help
509	  This allows just the call to lowlevel_init() to be skipped. The
510	  normal CP15 init (such as enabling the instruction cache) is still
511	  performed.
512
513config SPL_SKIP_LOWLEVEL_INIT_ONLY
514	bool "Skip call to lowlevel_init during early SPL boot ONLY"
515	depends on SPL && ARM
516	help
517	  This allows just the call to lowlevel_init() to be skipped. The
518	  normal CP15 init (such as enabling the instruction cache) is still
519	  performed.
520
521config TPL_SKIP_LOWLEVEL_INIT_ONLY
522	bool "Skip call to lowlevel_init during early TPL boot ONLY"
523	depends on TPL && ARM
524	help
525	  This allows just the call to lowlevel_init() to be skipped. The
526	  normal CP15 init (such as enabling the instruction cache) is still
527	  performed.
528
529endmenu
530
531config SYS_HAS_NONCACHED_MEMORY
532	bool "Enable reserving a non-cached memory area for drivers"
533	depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
534	help
535	  This is useful for drivers that would otherwise require a lot of
536	  explicit cache maintenance. For some drivers it's also impossible to
537	  properly maintain the cache. For example if the regions that need to
538	  be flushed are not a multiple of the cache-line size, *and* padding
539	  cannot be allocated between the regions to align them (i.e.  if the
540	  HW requires a contiguous array of regions, and the size of each
541	  region is not cache-aligned), then a flush of one region may result
542	  in overwriting data that hardware has written to another region in
543	  the same cache-line. This can happen for example in network drivers
544	  where descriptors for buffers are typically smaller than the CPU
545	  cache-line (e.g.  16 bytes vs. 32 or 64 bytes).
546
547config SYS_NONCACHED_MEMORY
548	hex "Size in bytes of the non-cached memory area"
549	depends on SYS_HAS_NONCACHED_MEMORY
550	default 0x100000
551	help
552	  Size of non-cached memory area. This area of memory will be typically
553	  located right below the malloc() area and mapped uncached in the MMU.
554
555source "arch/arc/Kconfig"
556source "arch/arm/Kconfig"
557source "arch/m68k/Kconfig"
558source "arch/microblaze/Kconfig"
559source "arch/mips/Kconfig"
560source "arch/nios2/Kconfig"
561source "arch/powerpc/Kconfig"
562source "arch/sandbox/Kconfig"
563source "arch/sh/Kconfig"
564source "arch/x86/Kconfig"
565source "arch/xtensa/Kconfig"
566source "arch/riscv/Kconfig"
567
568if ARM || M68K || PPC
569
570source "arch/Kconfig.nxp"
571
572endif
573
574source "board/keymile/Kconfig"
575
576choice
577	prompt "Endianness selection"
578	default SYS_BIG_ENDIAN if MIPS || MICROBLAZE
579	default SYS_LITTLE_ENDIAN
580	help
581	  Some boards can be configured for either little or big endian
582	  byte order. These modes require different U-Boot images. In general there
583	  is one preferred byteorder for a particular system but some systems are
584	  just as commonly used in the one or the other endianness.
585
586config SYS_BIG_ENDIAN
587	bool "Big endian"
588	depends on SUPPORT_BIG_ENDIAN
589
590config SYS_LITTLE_ENDIAN
591	bool "Little endian"
592	depends on SUPPORT_LITTLE_ENDIAN
593endchoice
594