1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef _MACH_STM32_H_ 7 #define _MACH_STM32_H_ 8 9 #include <linux/sizes.h> 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 13 enum boot_device { 14 BOOT_FLASH_SD = 0x10, 15 BOOT_FLASH_SD_1 = 0x11, 16 BOOT_FLASH_SD_2 = 0x12, 17 BOOT_FLASH_SD_3 = 0x13, 18 19 BOOT_FLASH_EMMC = 0x20, 20 BOOT_FLASH_EMMC_1 = 0x21, 21 BOOT_FLASH_EMMC_2 = 0x22, 22 BOOT_FLASH_EMMC_3 = 0x23, 23 24 BOOT_FLASH_NAND = 0x30, 25 BOOT_FLASH_NAND_FMC = 0x31, 26 27 BOOT_FLASH_NOR = 0x40, 28 BOOT_FLASH_NOR_QSPI = 0x41, 29 30 BOOT_SERIAL_UART = 0x50, 31 BOOT_SERIAL_UART_1 = 0x51, 32 BOOT_SERIAL_UART_2 = 0x52, 33 BOOT_SERIAL_UART_3 = 0x53, 34 BOOT_SERIAL_UART_4 = 0x54, 35 BOOT_SERIAL_UART_5 = 0x55, 36 BOOT_SERIAL_UART_6 = 0x56, 37 BOOT_SERIAL_UART_7 = 0x57, 38 BOOT_SERIAL_UART_8 = 0x58, 39 40 BOOT_SERIAL_USB = 0x60, 41 BOOT_SERIAL_USB_OTG = 0x62, 42 43 BOOT_FLASH_SPINAND = 0x70, 44 BOOT_FLASH_SPINAND_1 = 0x71, 45 46 BOOT_FLASH_HYPERFLASH = 0x80, 47 BOOT_FLASH_HYPERFLASH_1 = 0x81 48 }; 49 50 #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) 51 #define TAMP_BOOT_MODE_SHIFT 8 52 #define TAMP_BOOT_AUTH_MASK GENMASK(23, 16) 53 #define TAMP_BOOT_AUTH_SHIFT 16 54 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) 55 #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) 56 #define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4) 57 #define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0) 58 #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) 59 60 enum forced_boot_mode { 61 BOOT_NORMAL = 0x00, 62 BOOT_FASTBOOT = 0x01, 63 BOOT_RECOVERY = 0x02, 64 BOOT_STM32PROG = 0x03, 65 BOOT_UMS_MMC0 = 0x10, 66 BOOT_UMS_MMC1 = 0x11, 67 BOOT_UMS_MMC2 = 0x12, 68 }; 69 70 #endif 71 72 /* 73 * Peripheral memory map 74 * only address used before device tree parsing 75 */ 76 77 #if defined(CONFIG_STM32MP15X) || defined(CONFIG_STM32MP13X) 78 #define STM32_RCC_BASE 0x50000000 79 #define STM32_PWR_BASE 0x50001000 80 #define STM32_SYSCFG_BASE 0x50020000 81 #define STM32_DBGMCU_BASE 0x50081000 82 #define STM32_FMC2_BASE 0x58002000 83 #define STM32_IWDG2_BASE 0x5A002000 84 #define STM32_DDRCTRL_BASE 0x5A003000 85 #define STM32_DDRPHYC_BASE 0x5A004000 86 #define STM32_IWDG1_BASE 0x5C003000 87 #define STM32_TZC_BASE 0x5C006000 88 #define STM32_ETZPC_BASE 0x5C007000 89 #define STM32_STGEN_BASE 0x5C008000 90 #define STM32_TAMP_BASE 0x5C00A000 91 92 #ifdef CONFIG_STM32MP15X 93 #define STM32_USART1_BASE 0x5C000000 94 #define STM32_USART2_BASE 0x4000E000 95 #endif 96 #ifdef CONFIG_STM32MP13X 97 #define STM32_USART1_BASE 0x4c000000 98 #define STM32_USART2_BASE 0x4c001000 99 #endif 100 #define STM32_USART3_BASE 0x4000F000 101 #define STM32_UART4_BASE 0x40010000 102 #define STM32_UART5_BASE 0x40011000 103 #define STM32_USART6_BASE 0x44003000 104 #define STM32_UART7_BASE 0x40018000 105 #define STM32_UART8_BASE 0x40019000 106 107 #define STM32_SDMMC1_BASE 0x58005000 108 #define STM32_SDMMC2_BASE 0x58007000 109 #define STM32_SDMMC3_BASE 0x48004000 110 111 #ifdef CONFIG_STM32MP13X 112 #define STM32_SYSRAM_BASE 0x2FFE0000 113 #define STM32_SYSRAM_SIZE SZ_128K 114 #endif 115 116 #ifdef CONFIG_STM32MP15X 117 #define STM32_SYSRAM_BASE 0x2FFC0000 118 #define STM32_SYSRAM_SIZE SZ_256K 119 #endif 120 121 #define STM32_DDR_BASE 0xC0000000 122 #define STM32_DDR_SIZE SZ_1G 123 124 #ifndef __ASSEMBLY__ 125 /* 126 * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT 127 * - boot device = bit 8:4 128 * - boot instance = bit 3:0 129 */ 130 #define BOOT_TYPE_MASK 0xF0 131 #define BOOT_TYPE_SHIFT 4 132 #define BOOT_INSTANCE_MASK 0x0F 133 #define BOOT_INSTANCE_SHIFT 0 134 135 /* TAMP registers */ 136 #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) 137 138 #ifdef CONFIG_STM32MP15X 139 #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) 140 #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) 141 #define TAMP_FWU_BOOT_INFO_REG TAMP_BACKUP_REGISTER(10) 142 #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) 143 #define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) 144 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) 145 #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) 146 147 #define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) 148 149 #define TAMP_FWU_BOOT_IDX_OFFSET 0 150 #define TAMP_COPRO_STATE_OFF 0 151 #define TAMP_COPRO_STATE_INIT 1 152 #define TAMP_COPRO_STATE_CRUN 2 153 #define TAMP_COPRO_STATE_CSTOP 3 154 #define TAMP_COPRO_STATE_STANDBY 4 155 #define TAMP_COPRO_STATE_CRASH 5 156 #endif 157 158 #ifdef CONFIG_STM32MP13X 159 #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) 160 #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) 161 #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) 162 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) 163 #endif 164 165 #endif /* __ASSEMBLY__ */ 166 #endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ 167 168 #if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) 169 #define STM32_USART2_BASE 0x400E0000 170 #define STM32_USART3_BASE 0x400F0000 171 #define STM32_UART4_BASE 0x40100000 172 #define STM32_UART5_BASE 0x40110000 173 #define STM32_USART6_BASE 0x40220000 174 #define STM32_UART9_BASE 0x402C0000 175 #define STM32_USART1_BASE 0x40330000 176 #define STM32_UART7_BASE 0x40370000 177 #define STM32_UART8_BASE 0x40380000 178 #define STM32_RCC_BASE 0x44200000 179 #define STM32_TAMP_BASE 0x46010000 180 #define STM32_SDMMC1_BASE 0x48220000 181 #define STM32_SDMMC2_BASE 0x48230000 182 #define STM32_SDMMC3_BASE 0x48240000 183 184 #define STM32_DDR_BASE 0x80000000 185 186 #define STM32_DDR_SIZE SZ_4G 187 188 /* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */ 189 #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x)) 190 191 /* TAMP registers zone 3 RIF 1 (RW) at 96*/ 192 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) 193 #endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ 194 195 /* offset used for BSEC driver: misc_read and misc_write */ 196 #define STM32_BSEC_SHADOW_OFFSET 0x0 197 #define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4) 198 #define STM32_BSEC_OTP_OFFSET 0x80000000 199 #define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4) 200 #define STM32_BSEC_LOCK_OFFSET 0xC0000000 201 #define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4) 202 203 /* BSEC OTP index */ 204 #ifdef CONFIG_STM32MP15X 205 #define BSEC_OTP_RPN 1 206 #define BSEC_OTP_SERIAL 13 207 #define BSEC_OTP_PKG 16 208 #define BSEC_OTP_MAC 57 209 #define BSEC_OTP_BOARD 59 210 #endif 211 #ifdef CONFIG_STM32MP13X 212 #define BSEC_OTP_RPN 1 213 #define BSEC_OTP_SERIAL 13 214 #define BSEC_OTP_MAC 57 215 #define BSEC_OTP_BOARD 60 216 #endif 217 #if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) 218 #define BSEC_OTP_SERIAL 5 219 #define BSEC_OTP_RPN 9 220 #define BSEC_OTP_REVID 102 221 #define BSEC_OTP_PKG 122 222 #define BSEC_OTP_BOARD 246 223 #define BSEC_OTP_MAC 247 224 #endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ 225 226 #ifndef __ASSEMBLY__ 227 #include <asm/types.h> 228 229 /* enumerated used to identify the SYSCON driver instance */ 230 enum { 231 STM32MP_SYSCON_UNKNOWN, 232 STM32MP_SYSCON_SYSCFG, 233 }; 234 #endif /* __ASSEMBLY__*/ 235 236 #endif /* _MACH_STM32_H_ */ 237