1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
5 * Copyright (C) 2014-2019, Toradex AG
6 * copied from nitrogen6x
7 */
8
9 #include <config.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <image.h>
13 #include <init.h>
14 #include <net.h>
15 #include <asm/global_data.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18
19 #include <ahci.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/arch/imx-regs.h>
23 #include <asm/arch/mx6-ddr.h>
24 #include <asm/arch/mx6-pins.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/bootm.h>
28 #include <asm/gpio.h>
29 #include <asm/mach-imx/boot_mode.h>
30 #include <asm/mach-imx/iomux-v3.h>
31 #include <asm/mach-imx/sata.h>
32 #include <asm/mach-imx/video.h>
33 #include <asm/sections.h>
34 #include <dm/device-internal.h>
35 #include <dm/platform_data/serial_mxc.h>
36 #include <dwc_ahsata.h>
37 #include <env.h>
38 #include <fsl_esdhc_imx.h>
39 #include <i2c.h>
40 #include <imx_thermal.h>
41 #include <micrel.h>
42 #include <miiphy.h>
43 #include <netdev.h>
44
45 #include "../common/tdx-cfg-block.h"
46 #ifdef CONFIG_TDX_CMD_IMX_MFGR
47 #include "pf0100.h"
48 #endif
49
50 DECLARE_GLOBAL_DATA_PTR;
51
52 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
54 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
55
56 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
57 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
58 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
59
60 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
61 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
62 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
63
64 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
66
67 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
69 PAD_CTL_SRE_SLOW)
70
71 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
72 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
73 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
74
75 #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
76
77 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
78
79 #define APALIS_IMX6_SATA_INIT_RETRIES 10
80
81 #define I2C_PWR 1
82
dram_init(void)83 int dram_init(void)
84 {
85 /* use the DDR controllers configured size */
86 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
87 (ulong)imx_ddr_size());
88
89 return 0;
90 }
91
92 /* Apalis UART1 */
93 iomux_v3_cfg_t const uart1_pads_dce[] = {
94 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
95 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
96 };
97 iomux_v3_cfg_t const uart1_pads_dte[] = {
98 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
99 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
100 };
101
102 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD)
103 /* Apalis MMC1 */
104 iomux_v3_cfg_t const usdhc1_pads[] = {
105 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
113 MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
116 # define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
117 };
118
119 /* Apalis SD1 */
120 iomux_v3_cfg_t const usdhc2_pads[] = {
121 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
128 # define GPIO_SD_CD IMX_GPIO_NR(6, 14)
129 };
130
131 /* eMMC */
132 iomux_v3_cfg_t const usdhc3_pads[] = {
133 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
134 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
135 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
136 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
137 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
138 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
139 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
140 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
141 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
142 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
143 MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
144 };
145 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */
146
mx6_rgmii_rework(struct phy_device * phydev)147 int mx6_rgmii_rework(struct phy_device *phydev)
148 {
149 int tmp;
150
151 switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
152 case PHY_ID_KSZ9131:
153 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
154 tmp = ksz9031_phy_extended_read(phydev, 0x02,
155 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
156 MII_KSZ9031_MOD_DATA_NO_POST_INC);
157 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
158 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
159 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
160 ksz9031_phy_extended_write(phydev, 0x02,
161 MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
162 MII_KSZ9031_MOD_DATA_NO_POST_INC,
163 tmp);
164 /* read txc dll control - devaddr = 0x02, register = 0x4d */
165 tmp = ksz9031_phy_extended_read(phydev, 0x02,
166 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
167 MII_KSZ9031_MOD_DATA_NO_POST_INC);
168 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
169 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
170 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
171 ksz9031_phy_extended_write(phydev, 0x02,
172 MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
173 MII_KSZ9031_MOD_DATA_NO_POST_INC,
174 tmp);
175
176 /* control data pad skew - devaddr = 0x02, register = 0x04 */
177 ksz9031_phy_extended_write(phydev, 0x02,
178 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
179 MII_KSZ9031_MOD_DATA_NO_POST_INC,
180 0x007d);
181 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
182 ksz9031_phy_extended_write(phydev, 0x02,
183 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
184 MII_KSZ9031_MOD_DATA_NO_POST_INC,
185 0x7777);
186 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
187 ksz9031_phy_extended_write(phydev, 0x02,
188 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
189 MII_KSZ9031_MOD_DATA_NO_POST_INC,
190 0xdddd);
191 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
192 ksz9031_phy_extended_write(phydev, 0x02,
193 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
194 MII_KSZ9031_MOD_DATA_NO_POST_INC,
195 0x0007);
196 break;
197 case PHY_ID_KSZ9031:
198 default:
199 /* control data pad skew - devaddr = 0x02, register = 0x04 */
200 ksz9031_phy_extended_write(phydev, 0x02,
201 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
202 MII_KSZ9031_MOD_DATA_NO_POST_INC,
203 0x0000);
204 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
205 ksz9031_phy_extended_write(phydev, 0x02,
206 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
207 MII_KSZ9031_MOD_DATA_NO_POST_INC,
208 0x0000);
209 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
210 ksz9031_phy_extended_write(phydev, 0x02,
211 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
212 MII_KSZ9031_MOD_DATA_NO_POST_INC,
213 0x0000);
214 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
215 ksz9031_phy_extended_write(phydev, 0x02,
216 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
217 MII_KSZ9031_MOD_DATA_NO_POST_INC,
218 0x03FF);
219 break;
220 }
221
222 return 0;
223 }
224
225 iomux_v3_cfg_t const enet_pads[] = {
226 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
230 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
232 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
233 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
234 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
235 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
237 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
239 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
240 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
241 /* KSZ9031 PHY Reset */
242 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) |
243 MUX_MODE_SION,
244 # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
245 };
246
247 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
248 iomux_v3_cfg_t const gpio_pads[] = {
249 /* Apalis GPIO1 - GPIO8 */
250 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
251 MUX_MODE_SION,
252 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
253 MUX_MODE_SION,
254 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
255 MUX_MODE_SION,
256 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
257 MUX_MODE_SION,
258 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
259 MUX_MODE_SION,
260 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
261 MUX_MODE_SION,
262 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
263 MUX_MODE_SION,
264 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
265 MUX_MODE_SION,
266 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
267 MUX_MODE_SION,
268 };
269
setup_iomux_gpio(void)270 static void setup_iomux_gpio(void)
271 {
272 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
273 }
274
275 iomux_v3_cfg_t const usb_pads[] = {
276 /* USBH_EN */
277 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
278 # define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
279 /* USB_VBUS_DET */
280 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
281 # define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
282 /* USBO1_ID */
283 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
284 /* USBO1_EN */
285 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
286 # define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
287 };
288
289 /*
290 * UARTs are used in DTE mode, switch the mode on all UARTs before
291 * any pinmuxing connects a (DCE) output to a transceiver output.
292 */
293 #define UCR3 0x88 /* FIFO Control Register */
294 #define UCR3_RI BIT(8) /* RIDELT DTE mode */
295 #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
296 #define UFCR 0x90 /* FIFO Control Register */
297 #define UFCR_DCEDTE BIT(6) /* DCE=0 */
298
setup_dtemode_uart(void)299 static void setup_dtemode_uart(void)
300 {
301 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
302 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
303 setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
304 setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
305
306 clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
307 clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
308 clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
309 clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
310 }
311
setup_iomux_dte_uart(void)312 static void setup_iomux_dte_uart(void)
313 {
314 setup_dtemode_uart();
315 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
316 ARRAY_SIZE(uart1_pads_dte));
317 }
318
319 #ifdef CONFIG_USB_EHCI_MX6
board_ehci_hcd_init(int port)320 int board_ehci_hcd_init(int port)
321 {
322 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
323 return 0;
324 }
325 #endif
326
327 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_XPL_BUILD)
328 /* use the following sequence: eMMC, MMC1, SD1 */
329 struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
330 {USDHC3_BASE_ADDR},
331 {USDHC1_BASE_ADDR},
332 {USDHC2_BASE_ADDR},
333 };
334
board_mmc_getcd(struct mmc * mmc)335 int board_mmc_getcd(struct mmc *mmc)
336 {
337 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
338 int ret = true; /* default: assume inserted */
339
340 switch (cfg->esdhc_base) {
341 case USDHC1_BASE_ADDR:
342 gpio_request(GPIO_MMC_CD, "MMC_CD");
343 gpio_direction_input(GPIO_MMC_CD);
344 ret = !gpio_get_value(GPIO_MMC_CD);
345 break;
346 case USDHC2_BASE_ADDR:
347 gpio_request(GPIO_MMC_CD, "SD_CD");
348 gpio_direction_input(GPIO_SD_CD);
349 ret = !gpio_get_value(GPIO_SD_CD);
350 break;
351 }
352
353 return ret;
354 }
355
board_mmc_init(struct bd_info * bis)356 int board_mmc_init(struct bd_info *bis)
357 {
358 struct src *psrc = (struct src *)SRC_BASE_ADDR;
359 unsigned reg = readl(&psrc->sbmr1) >> 11;
360 /*
361 * Upon reading BOOT_CFG register the following map is done:
362 * Bit 11 and 12 of BOOT_CFG register can determine the current
363 * mmc port
364 * 0x1 SD1
365 * 0x2 SD2
366 * 0x3 SD4
367 */
368
369 switch (reg & 0x3) {
370 case 0x0:
371 imx_iomux_v3_setup_multiple_pads(
372 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
373 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
374 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
375 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
376 break;
377 case 0x1:
378 imx_iomux_v3_setup_multiple_pads(
379 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
380 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
381 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
382 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
383 break;
384 case 0x2:
385 imx_iomux_v3_setup_multiple_pads(
386 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
387 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
388 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
389 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
390 break;
391 default:
392 puts("MMC boot device not available");
393 }
394
395 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
396 }
397 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_XPL_BUILD */
398
board_phy_config(struct phy_device * phydev)399 int board_phy_config(struct phy_device *phydev)
400 {
401 mx6_rgmii_rework(phydev);
402 if (phydev->drv->config)
403 phydev->drv->config(phydev);
404
405 return 0;
406 }
407
408 static iomux_v3_cfg_t const pwr_intb_pads[] = {
409 /*
410 * the bootrom sets the iomux to vselect, potentially connecting
411 * two outputs. Set this back to GPIO
412 */
413 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
414 };
415
416 #if defined(CONFIG_VIDEO_IPUV3)
417
418 static iomux_v3_cfg_t const backlight_pads[] = {
419 /* Backlight on RGB connector: J15 */
420 MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
421 MUX_MODE_SION,
422 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
423 /* additional CPU pin on BKL_PWM, keep in tristate */
424 MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
425 /* Backlight PWM, used as GPIO in U-Boot */
426 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
427 MUX_MODE_SION,
428 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
429 /* buffer output enable 0: buffer enabled */
430 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
431 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
432 /* PSAVE# integrated VDAC */
433 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
434 MUX_MODE_SION,
435 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
436 };
437
438 static iomux_v3_cfg_t const rgb_pads[] = {
439 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
440 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
441 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
442 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
443 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
444 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
445 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
446 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
447 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
448 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
449 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
450 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
451 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
452 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
453 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
454 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
455 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
456 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
457 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
458 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
459 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
460 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
461 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
462 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
463 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
464 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
465 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
466 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
467 };
468
469 #ifdef CONFIG_IMX_HDMI
do_enable_hdmi(struct display_info_t const * dev)470 static void do_enable_hdmi(struct display_info_t const *dev)
471 {
472 imx_enable_hdmi_phy();
473 }
474 #endif
475
enable_lvds(struct display_info_t const * dev)476 static void enable_lvds(struct display_info_t const *dev)
477 {
478 struct iomuxc *iomux = (struct iomuxc *)
479 IOMUXC_BASE_ADDR;
480 u32 reg = readl(&iomux->gpr[2]);
481 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
482 writel(reg, &iomux->gpr[2]);
483 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
484 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
485 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
486 }
487
enable_rgb(struct display_info_t const * dev)488 static void enable_rgb(struct display_info_t const *dev)
489 {
490 imx_iomux_v3_setup_multiple_pads(
491 rgb_pads,
492 ARRAY_SIZE(rgb_pads));
493 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
494 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
495 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
496 }
497
detect_default(struct display_info_t const * dev)498 static int detect_default(struct display_info_t const *dev)
499 {
500 (void) dev;
501 return 1;
502 }
503
504 struct display_info_t const displays[] = {
505 #ifdef CONFIG_IMX_HDMI
506 {
507 .bus = -1,
508 .addr = 0,
509 .pixfmt = IPU_PIX_FMT_RGB24,
510 .detect = detect_hdmi,
511 .enable = do_enable_hdmi,
512 .mode = {
513 .name = "HDMI",
514 .refresh = 60,
515 .xres = 1024,
516 .yres = 768,
517 .pixclock = 15385,
518 .left_margin = 220,
519 .right_margin = 40,
520 .upper_margin = 21,
521 .lower_margin = 7,
522 .hsync_len = 60,
523 .vsync_len = 10,
524 .sync = FB_SYNC_EXT,
525 .vmode = FB_VMODE_NONINTERLACED
526 } },
527 #endif
528 {
529 .bus = -1,
530 .addr = 0,
531 .di = 1,
532 .pixfmt = IPU_PIX_FMT_RGB24,
533 .detect = detect_default,
534 .enable = enable_rgb,
535 .mode = {
536 .name = "vga-rgb",
537 .refresh = 60,
538 .xres = 640,
539 .yres = 480,
540 .pixclock = 33000,
541 .left_margin = 48,
542 .right_margin = 16,
543 .upper_margin = 31,
544 .lower_margin = 11,
545 .hsync_len = 96,
546 .vsync_len = 2,
547 .sync = 0,
548 .vmode = FB_VMODE_NONINTERLACED
549 } }, {
550 .bus = -1,
551 .addr = 0,
552 .di = 1,
553 .pixfmt = IPU_PIX_FMT_RGB24,
554 .enable = enable_rgb,
555 .mode = {
556 .name = "wvga-rgb",
557 .refresh = 60,
558 .xres = 800,
559 .yres = 480,
560 .pixclock = 25000,
561 .left_margin = 40,
562 .right_margin = 88,
563 .upper_margin = 33,
564 .lower_margin = 10,
565 .hsync_len = 128,
566 .vsync_len = 2,
567 .sync = 0,
568 .vmode = FB_VMODE_NONINTERLACED
569 } }, {
570 .bus = -1,
571 .addr = 0,
572 .pixfmt = IPU_PIX_FMT_LVDS666,
573 .enable = enable_lvds,
574 .mode = {
575 .name = "wsvga-lvds",
576 .refresh = 60,
577 .xres = 1024,
578 .yres = 600,
579 .pixclock = 15385,
580 .left_margin = 220,
581 .right_margin = 40,
582 .upper_margin = 21,
583 .lower_margin = 7,
584 .hsync_len = 60,
585 .vsync_len = 10,
586 .sync = FB_SYNC_EXT,
587 .vmode = FB_VMODE_NONINTERLACED
588 } } };
589 size_t display_count = ARRAY_SIZE(displays);
590
setup_display(void)591 static void setup_display(void)
592 {
593 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
594 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
595 int reg;
596
597 enable_ipu_clock();
598
599 #ifdef CONFIG_IMX_HDMI
600 imx_setup_hdmi();
601 #endif
602
603 /* Turn on LDB0,IPU,IPU DI0 clocks */
604 reg = __raw_readl(&mxc_ccm->CCGR3);
605 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
606 writel(reg, &mxc_ccm->CCGR3);
607
608 /* set LDB0, LDB1 clk select to 011/011 */
609 reg = readl(&mxc_ccm->cs2cdr);
610 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
611 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
612 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
613 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
614 writel(reg, &mxc_ccm->cs2cdr);
615
616 reg = readl(&mxc_ccm->cscmr2);
617 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
618 writel(reg, &mxc_ccm->cscmr2);
619
620 reg = readl(&mxc_ccm->chsccdr);
621 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
622 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
623 writel(reg, &mxc_ccm->chsccdr);
624
625 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
626 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
627 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
628 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
629 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
630 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
631 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
632 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
633 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
634 writel(reg, &iomux->gpr[2]);
635
636 reg = readl(&iomux->gpr[3]);
637 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
638 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
639 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
640 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
641 writel(reg, &iomux->gpr[3]);
642
643 /* backlight unconditionally on for now */
644 imx_iomux_v3_setup_multiple_pads(backlight_pads,
645 ARRAY_SIZE(backlight_pads));
646 /* use 0 for EDT 7", use 1 for LG fullHD panel */
647 gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
648 gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
649 gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
650 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
651 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
652 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
653 }
654
655 /*
656 * Backlight off before OS handover
657 */
board_preboot_os(void)658 void board_preboot_os(void)
659 {
660 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
661 gpio_direction_output(RGB_BACKLIGHT_GP, 0);
662 }
663 #endif /* defined(CONFIG_VIDEO_IPUV3) */
664
board_early_init_f(void)665 int board_early_init_f(void)
666 {
667 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
668 ARRAY_SIZE(pwr_intb_pads));
669 setup_iomux_dte_uart();
670
671 return 0;
672 }
673
674 /*
675 * Do not overwrite the console
676 * Use always serial for U-Boot console
677 */
overwrite_console(void)678 int overwrite_console(void)
679 {
680 return 1;
681 }
682
board_init(void)683 int board_init(void)
684 {
685 /* address of boot parameters */
686 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
687
688 #if defined(CONFIG_VIDEO_IPUV3)
689 setup_display();
690 #endif
691
692 #ifdef CONFIG_TDX_CMD_IMX_MFGR
693 (void) pmic_init();
694 #endif
695
696 #ifdef CONFIG_SATA
697 setup_sata();
698 #endif
699
700 setup_iomux_gpio();
701
702 return 0;
703 }
704
is_som_variant_1_2(void)705 static bool is_som_variant_1_2(void)
706 {
707 struct udevice *bus;
708 struct udevice *i2c_dev;
709 int ret;
710
711 ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PWR, &bus);
712 if (ret) {
713 printf("Failed to get I2C_PWR\n");
714 return false;
715 }
716
717 /* V1.2 uses the TLA2024 at 0x49 instead of the STMPE811 at 0x41 */
718 ret = dm_i2c_probe(bus, 0x49, 0, &i2c_dev);
719
720 return (bool)!ret;
721 }
722
select_dt_from_module_version(void)723 static void select_dt_from_module_version(void)
724 {
725 if (is_som_variant_1_2())
726 env_set("variant", "-v1.2");
727 else
728 env_set("variant", "");
729 }
730
731 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)732 int board_late_init(void)
733 {
734 #if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
735 char env_str[256];
736 u32 rev;
737
738 select_dt_from_module_version();
739
740 rev = get_board_revision();
741 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
742 env_set("board_rev", env_str);
743 #endif /* CONFIG_BOARD_LATE_INIT */
744
745 if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) {
746 env_set("bootdelay", "0");
747 if (IS_ENABLED(CONFIG_CMD_USB_SDP)) {
748 printf("Serial Downloader recovery mode, using sdp command\n");
749 env_set("bootcmd", "sdp 0");
750 } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) {
751 printf("Fastboot recovery mode, using fastboot command\n");
752 env_set("bootcmd", "fastboot usb 0");
753 }
754 }
755
756 return 0;
757 }
758 #endif /* CONFIG_BOARD_LATE_INIT */
759
760 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)761 int ft_board_setup(void *blob, struct bd_info *bd)
762 {
763 return ft_common_board_setup(blob, bd);
764 }
765 #endif
766
767 #ifdef CONFIG_CMD_BMODE
768 static const struct boot_mode board_boot_modes[] = {
769 /* 4-bit bus width */
770 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
771 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
772 {NULL, 0},
773 };
774 #endif
775
misc_init_r(void)776 int misc_init_r(void)
777 {
778 #ifdef CONFIG_CMD_BMODE
779 add_board_boot_modes(board_boot_modes);
780 #endif
781 return 0;
782 }
783
784 #ifdef CONFIG_LDO_BYPASS_CHECK
785 /* TODO, use external pmic, for now always ldo_enable */
ldo_mode_set(int ldo_bypass)786 void ldo_mode_set(int ldo_bypass)
787 {
788 return;
789 }
790 #endif
791
792 #ifdef CONFIG_XPL_BUILD
793 #include <spl.h>
794 #include <linux/libfdt.h>
795 #include "asm/arch/mx6q-ddr.h"
796 #include "asm/arch/iomux.h"
797 #include "asm/arch/crm_regs.h"
798
ccgr_init(void)799 static void ccgr_init(void)
800 {
801 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
802
803 writel(0x00C03F3F, &ccm->CCGR0);
804 writel(0x0030FC03, &ccm->CCGR1);
805 writel(0x0FFFFFF3, &ccm->CCGR2);
806 writel(0x3FF0300F, &ccm->CCGR3);
807 writel(0x00FFF300, &ccm->CCGR4);
808 writel(0x0F0000F3, &ccm->CCGR5);
809 writel(0x000003FF, &ccm->CCGR6);
810
811 /*
812 * Setup CCM_CCOSR register as follows:
813 *
814 * clko2_en = 1 --> CKO2 enabled
815 * clko2_div = 000 --> divide by 1
816 * clko2_sel = 01110 --> osc_clk (24MHz)
817 *
818 * clk_out_sel = 1 --> Output CKO2 to CKO1
819 *
820 * This sets both CLKO2/CLKO1 output to 24MHz,
821 * CLKO1 configuration not relevant because of clk_out_sel
822 * (CLKO1 set to default)
823 */
824 writel(0x010E0101, &ccm->ccosr);
825 }
826
827 #define PAD_CTL_INPUT_DDR BIT(17)
828
829 struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
830 /* Differential input, 40 ohm DSE */
831 .dram_sdclk_0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
832 .dram_sdclk_1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
833 .dram_cas = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
834 .dram_ras = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
835 .dram_reset = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
836
837 /* SDKE[0:1]: BIT(12) and BIT(13) are reserved and set at reset */
838 .dram_sdcke0 = 0x00003000,
839 .dram_sdcke1 = 0x00003000,
840
841 .dram_sdba2 = 0x00000000,
842
843 /* ODT[0:1]: 40 ohm DSE, BIT(12) and BIT(13) are reserved and set at reset */
844 .dram_sdodt0 = PAD_CTL_DSE_40ohm | 0x00003000,
845 .dram_sdodt1 = PAD_CTL_DSE_40ohm | 0x00003000,
846
847 /* SDQS[0:7]: 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
848 .dram_sdqs0 = PAD_CTL_DSE_40ohm,
849 .dram_sdqs1 = PAD_CTL_DSE_40ohm,
850 .dram_sdqs2 = PAD_CTL_DSE_40ohm,
851 .dram_sdqs3 = PAD_CTL_DSE_40ohm,
852 .dram_sdqs4 = PAD_CTL_DSE_40ohm,
853 .dram_sdqs5 = PAD_CTL_DSE_40ohm,
854 .dram_sdqs6 = PAD_CTL_DSE_40ohm,
855 .dram_sdqs7 = PAD_CTL_DSE_40ohm,
856
857 /* DQM[0:7]: Differential input, 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */
858 .dram_dqm0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
859 .dram_dqm1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
860 .dram_dqm2 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
861 .dram_dqm3 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
862 .dram_dqm4 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
863 .dram_dqm5 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
864 .dram_dqm6 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
865 .dram_dqm7 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR,
866 };
867
868 struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
869 /* DDR3 */
870 .grp_ddr_type = 0x000C0000,
871
872 /* SDQS[0:7]: Differential input */
873 .grp_ddrmode_ctl = PAD_CTL_INPUT_DDR,
874
875 /* DATA[0:63]: Pull/Keeper disabled */
876 .grp_ddrpke = 0,
877
878 /* ADDR[0:16], SDBA[0:1]: 40 ohm DSE */
879 .grp_addds = PAD_CTL_DSE_40ohm,
880
881 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm DSE */
882 .grp_ctlds = PAD_CTL_DSE_40ohm,
883
884 /* DATA[0:63]: Differential input */
885 .grp_ddrmode = PAD_CTL_INPUT_DDR,
886
887 /* DATA[0:63]: 40 ohm DSE */
888 .grp_b0ds = PAD_CTL_DSE_40ohm,
889 .grp_b1ds = PAD_CTL_DSE_40ohm,
890 .grp_b2ds = PAD_CTL_DSE_40ohm,
891 .grp_b3ds = PAD_CTL_DSE_40ohm,
892 .grp_b4ds = PAD_CTL_DSE_40ohm,
893 .grp_b5ds = PAD_CTL_DSE_40ohm,
894 .grp_b6ds = PAD_CTL_DSE_40ohm,
895 .grp_b7ds = PAD_CTL_DSE_40ohm,
896 };
897
898 struct mx6_ddr_sysinfo sysinfo = {
899 .dsize = 2, /* width of data bus: 2=64 */
900 .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */
901 .ncs = 1,
902 .cs1_mirror = 0,
903 .rtt_wr = 2, /* Dynamic ODT, RZQ/2 */
904 .rtt_nom = 0, /* Disabled */
905 .walat = 0, /* Write additional latency */
906 .ralat = 5, /* Read additional latency */
907 .mif3_mode = 3, /* Command prediction working mode */
908 .bi_on = 1, /* Bank interleaving enabled */
909 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
910 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
911 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
912 .ddr_type = DDR_TYPE_DDR3,
913 .refsel = 1, /* Refresh cycles at 32KHz */
914 .refr = 3, /* 4 refresh commands per refresh cycle */
915 };
916
917 static const struct mx6_mmdc_calibration mx6_mmdc_calib = {
918 .p0_mpwldectrl0 = 0x0009000E,
919 .p0_mpwldectrl1 = 0x0018000B,
920 .p1_mpwldectrl0 = 0x00060015,
921 .p1_mpwldectrl1 = 0x0006000E,
922 .p0_mpdgctrl0 = 0x432A0338,
923 .p0_mpdgctrl1 = 0x03260324,
924 .p1_mpdgctrl0 = 0x43340344,
925 .p1_mpdgctrl1 = 0x031E027C,
926 .p0_mprddlctl = 0x33272D2E,
927 .p1_mprddlctl = 0x2F312B37,
928 .p0_mpwrdlctl = 0x3A35433C,
929 .p1_mpwrdlctl = 0x4336453F,
930 };
931
932 static const struct mx6_ddr3_cfg ddr3_cfg = {
933 .mem_speed = 1066,
934 .density = 2,
935 .width = 16,
936 .banks = 8,
937 .rowaddr = 14,
938 .coladdr = 10,
939 .pagesz = 2,
940 .trcd = 1312,
941 .trcmin = 4812,
942 .trasmin = 3500,
943 .SRT = 0,
944 };
945
946 struct mx6_ddr_sysinfo sysinfo_it = {
947 .dsize = 2, /* width of data bus: 2=64 */
948 .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */
949 .ncs = 1,
950 .cs1_mirror = 0,
951 .rtt_wr = 1, /* Dynamic ODT, RZQ/4 */
952 .rtt_nom = 1, /* RZQ/4 */
953 .walat = 0, /* Write additional latency */
954 .ralat = 5, /* Read additional latency */
955 .mif3_mode = 3, /* Command prediction working mode */
956 .bi_on = 1, /* Bank interleaving enabled */
957 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
958 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
959 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
960 .ddr_type = DDR_TYPE_DDR3,
961 .refsel = 1, /* Refresh cycles at 32KHz */
962 .refr = 7, /* 8 refresh commands per refresh cycle */
963 };
964
965 static const struct mx6_mmdc_calibration mx6_mmdc_calib_it = {
966 .p0_mpwldectrl0 = 0x0009000E,
967 .p0_mpwldectrl1 = 0x0018000B,
968 .p1_mpwldectrl0 = 0x00060015,
969 .p1_mpwldectrl1 = 0x0006000E,
970 .p0_mpdgctrl0 = 0x03300338,
971 .p0_mpdgctrl1 = 0x03240324,
972 .p1_mpdgctrl0 = 0x03440350,
973 .p1_mpdgctrl1 = 0x032C0308,
974 .p0_mprddlctl = 0x40363C3E,
975 .p1_mprddlctl = 0x3C3E3C46,
976 .p0_mpwrdlctl = 0x403E463E,
977 .p1_mpwrdlctl = 0x4A384C46,
978 };
979
980 static const struct mx6_ddr3_cfg ddr3_cfg_it = {
981 .mem_speed = 1066,
982 .density = 4,
983 .width = 16,
984 .banks = 8,
985 .rowaddr = 15,
986 .coladdr = 10,
987 .pagesz = 2,
988 .trcd = 1312,
989 .trcmin = 4812,
990 .trasmin = 3500,
991 .SRT = 1,
992 };
993
994 /* Perform DDR DRAM calibration */
spl_dram_perform_cal(const struct mx6_ddr_sysinfo * ddr_sysinfo)995 static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo)
996 {
997 #ifdef CONFIG_MX6_DDRCAL
998 int err;
999
1000 err = mmdc_do_write_level_calibration(ddr_sysinfo);
1001 if (err)
1002 printf("error %d from write level calibration\n", err);
1003 err = mmdc_do_dqs_calibration(ddr_sysinfo);
1004 if (err)
1005 printf("error %d from dqs calibration\n", err);
1006 #endif
1007 }
1008
spl_dram_init(void)1009 static void spl_dram_init(void)
1010 {
1011 bool temp_grade_it;
1012
1013 switch (get_cpu_temp_grade(NULL, NULL)) {
1014 case TEMP_COMMERCIAL:
1015 case TEMP_EXTCOMMERCIAL:
1016 puts("Commercial temperature grade DDR3 timings.\n");
1017 temp_grade_it = false;
1018 break;
1019 case TEMP_INDUSTRIAL:
1020 case TEMP_AUTOMOTIVE:
1021 default:
1022 puts("Industrial temperature grade DDR3 timings.\n");
1023 temp_grade_it = true;
1024 break;
1025 };
1026
1027 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
1028
1029 if (temp_grade_it)
1030 mx6_dram_cfg(&sysinfo_it, &mx6_mmdc_calib_it, &ddr3_cfg_it);
1031 else
1032 mx6_dram_cfg(&sysinfo, &mx6_mmdc_calib, &ddr3_cfg);
1033
1034 udelay(100);
1035
1036 if (temp_grade_it)
1037 spl_dram_perform_cal(&sysinfo_it);
1038 else
1039 spl_dram_perform_cal(&sysinfo);
1040 }
1041
board_init_f(ulong dummy)1042 void board_init_f(ulong dummy)
1043 {
1044 /* setup AIPS and disable watchdog */
1045 arch_cpu_init();
1046
1047 ccgr_init();
1048 gpr_init();
1049
1050 /* iomux */
1051 board_early_init_f();
1052
1053 /* setup GP timer */
1054 timer_init();
1055
1056 /* UART clocks enabled and gd valid - init serial console */
1057 preloader_console_init();
1058
1059 /* Make sure we use dte mode */
1060 setup_dtemode_uart();
1061
1062 /* DDR initialization */
1063 spl_dram_init();
1064
1065 /* Clear the BSS. */
1066 memset(__bss_start, 0, __bss_end - __bss_start);
1067
1068 /* load/boot image from boot device */
1069 board_init_r(NULL, 0);
1070 }
1071
1072 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)1073 int board_fit_config_name_match(const char *name)
1074 {
1075 if (!strcmp(name, "imx6-apalis"))
1076 return 0;
1077
1078 return -1;
1079 }
1080 #endif
1081
reset_cpu(void)1082 void reset_cpu(void)
1083 {
1084 }
1085
1086 #endif /* CONFIG_XPL_BUILD */
1087
1088 static struct mxc_serial_plat mxc_serial_plat = {
1089 .reg = (struct mxc_uart *)UART1_BASE,
1090 .use_dte = true,
1091 };
1092
1093 U_BOOT_DRVINFO(mxc_serial) = {
1094 .name = "serial_mxc",
1095 .plat = &mxc_serial_plat,
1096 };
1097