1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 */
6
7 #include <clk.h>
8 #include <log.h>
9 #include <usb.h>
10 #include <errno.h>
11 #include <wait_bit.h>
12 #include <asm/global_data.h>
13 #include <linux/compiler.h>
14 #include <linux/delay.h>
15 #include <usb/ehci-ci.h>
16 #include <asm/io.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/sys_proto.h>
21 #include <dm.h>
22 #include <asm/mach-types.h>
23 #include <power/regulator.h>
24 #include <linux/usb/otg.h>
25 #include <linux/usb/phy.h>
26
27 #include "ehci.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #define USB_OTGREGS_OFFSET 0x000
32 #define USB_H1REGS_OFFSET 0x200
33 #define USB_H2REGS_OFFSET 0x400
34 #define USB_H3REGS_OFFSET 0x600
35 #define USB_OTHERREGS_OFFSET 0x800
36
37 #define USB_H1_CTRL_OFFSET 0x04
38
39 #define USBPHY_CTRL 0x00000030
40 #define USBPHY_CTRL_SET 0x00000034
41 #define USBPHY_CTRL_CLR 0x00000038
42 #define USBPHY_CTRL_TOG 0x0000003c
43
44 #define USBPHY_PWD 0x00000000
45 #define USBPHY_CTRL_SFTRST 0x80000000
46 #define USBPHY_CTRL_CLKGATE 0x40000000
47 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
48 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
49 #define USBPHY_CTRL_OTG_ID 0x08000000
50
51 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
52 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
53
54 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
55 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
56 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
57 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
58
59 #define USBNC_OFFSET 0x200
60 #define USBNC_PHY_STATUS_OFFSET 0x23C
61 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
62 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
63 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
64 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
65 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
66
67 /* USBCMD */
68 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
69 #define UCMD_RESET (1 << 1) /* controller reset */
70
71 /* If this is not defined, assume MX6/MX7/MX8M SoC default */
72 #ifndef CFG_MXC_USB_PORTSC
73 #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
74 #endif
75
76 /* Base address for this IP block is 0x02184800 */
77 struct usbnc_regs {
78 u32 ctrl[4]; /* otg/host1-3 */
79 u32 uh2_hsic_ctrl;
80 u32 uh3_hsic_ctrl;
81 u32 otg_phy_ctrl_0;
82 u32 uh1_phy_ctrl_0;
83 u32 reserve1[4];
84 u32 phy_cfg1;
85 u32 phy_cfg2;
86 u32 reserve2;
87 u32 phy_status;
88 u32 reserve3[4];
89 u32 adp_cfg1;
90 u32 adp_cfg2;
91 u32 adp_status;
92 };
93
94 #if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
usb_power_config_mx6(struct anatop_regs __iomem * anatop,int anatop_bits_index)95 static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
96 int anatop_bits_index)
97 {
98 void __iomem *chrg_detect;
99 void __iomem *pll_480_ctrl_clr;
100 void __iomem *pll_480_ctrl_set;
101
102 if (!is_mx6())
103 return;
104
105 switch (anatop_bits_index) {
106 case 0:
107 chrg_detect = &anatop->usb1_chrg_detect;
108 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
109 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
110 break;
111 case 1:
112 chrg_detect = &anatop->usb2_chrg_detect;
113 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
114 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
115 break;
116 default:
117 return;
118 }
119 /*
120 * Some phy and power's special controls
121 * 1. The external charger detector needs to be disabled
122 * or the signal at DP will be poor
123 * 2. The PLL's power and output to usb
124 * is totally controlled by IC, so the Software only needs
125 * to enable them at initializtion.
126 */
127 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
128 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
129 chrg_detect);
130
131 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
132 pll_480_ctrl_clr);
133
134 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
135 ANADIG_USB2_PLL_480_CTRL_POWER |
136 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
137 pll_480_ctrl_set);
138 }
139 #else
140 static void __maybe_unused
usb_power_config_mx6(void * anatop,int anatop_bits_index)141 usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
142 #endif
143
144 #if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
usb_power_config_mx7(struct usbnc_regs * usbnc)145 static void usb_power_config_mx7(struct usbnc_regs *usbnc)
146 {
147 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
148
149 if (!is_mx7())
150 return;
151
152 /*
153 * Clear the ACAENB to enable usb_otg_id detection,
154 * otherwise it is the ACA detection enabled.
155 */
156 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
157 }
158 #else
159 static void __maybe_unused
usb_power_config_mx7(void * usbnc)160 usb_power_config_mx7(void *usbnc) { }
161 #endif
162
163 #if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
usb_power_config_mx7ulp(struct usbphy_regs __iomem * usbphy)164 static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
165 {
166 if (!is_mx7ulp())
167 return;
168
169 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
170 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
171 &usbphy->usb1_chrg_detect);
172
173 scg_enable_usb_pll(true);
174 }
175 #else
176 static void __maybe_unused
usb_power_config_mx7ulp(void * usbphy)177 usb_power_config_mx7ulp(void *usbphy) { }
178 #endif
179
180 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
181 static const unsigned phy_bases[] = {
182 USB_PHY0_BASE_ADDR,
183 #if defined(USB_PHY1_BASE_ADDR)
184 USB_PHY1_BASE_ADDR,
185 #endif
186 };
187
188 #if !defined(CONFIG_PHY)
usb_internal_phy_clock_gate(void __iomem * phy_reg,int on)189 static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
190 {
191 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
192 writel(USBPHY_CTRL_CLKGATE, phy_reg);
193 }
194
195 /* Return 0 : host node, <>0 : device mode */
usb_phy_enable(struct usb_ehci * ehci,void __iomem * phy_reg)196 static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
197 {
198 void __iomem *phy_ctrl;
199 void __iomem *usb_cmd;
200 int ret;
201
202 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
203 usb_cmd = (void __iomem *)&ehci->usbcmd;
204
205 /* Stop then Reset */
206 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
207 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
208 if (ret)
209 return ret;
210
211 setbits_le32(usb_cmd, UCMD_RESET);
212 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
213 if (ret)
214 return ret;
215
216 /* Reset USBPHY module */
217 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
218 udelay(10);
219
220 /* Remove CLKGATE and SFTRST */
221 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
222 udelay(10);
223
224 /* Power up the PHY */
225 writel(0, phy_reg + USBPHY_PWD);
226 /* enable FS/LS device */
227 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
228 USBPHY_CTRL_ENUTMILEVEL3);
229
230 return 0;
231 }
232 #endif
233
usb_phy_mode(int port)234 int usb_phy_mode(int port)
235 {
236 void __iomem *phy_reg;
237 void __iomem *phy_ctrl;
238 u32 val;
239
240 phy_reg = (void __iomem *)phy_bases[port];
241 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
242
243 val = readl(phy_ctrl);
244
245 if (val & USBPHY_CTRL_OTG_ID)
246 return USB_INIT_DEVICE;
247 else
248 return USB_INIT_HOST;
249 }
250
251 #elif defined(CONFIG_MX7)
usb_phy_mode(int port)252 int usb_phy_mode(int port)
253 {
254 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
255 (0x10000 * port) + USBNC_OFFSET);
256 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
257 u32 val;
258
259 val = readl(status);
260
261 if (val & USBNC_PHYSTATUS_ID_DIG)
262 return USB_INIT_DEVICE;
263 else
264 return USB_INIT_HOST;
265 }
266 #endif
267
268 #if !defined(CONFIG_PHY)
269 /* Should be done in the MXS PHY driver */
usb_oc_config(struct usbnc_regs * usbnc,int index)270 static void usb_oc_config(struct usbnc_regs *usbnc, int index)
271 {
272 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
273
274 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
275
276 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
277
278 /* Set power polarity to high active */
279 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
280 setbits_le32(ctrl, UCTRL_PWR_POL);
281 #else
282 clrbits_le32(ctrl, UCTRL_PWR_POL);
283 #endif
284 }
285 #endif
286
287 #if !CONFIG_IS_ENABLED(DM_USB)
288 /**
289 * board_usb_phy_mode - override usb phy mode
290 * @port: usb host/otg port
291 *
292 * Target board specific, override usb_phy_mode.
293 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
294 * left disconnected in this case usb_phy_mode will not be able to identify
295 * the phy mode that usb port is used.
296 * Machine file overrides board_usb_phy_mode.
297 *
298 * Return: USB_INIT_DEVICE or USB_INIT_HOST
299 */
board_usb_phy_mode(int port)300 int __weak board_usb_phy_mode(int port)
301 {
302 return usb_phy_mode(port);
303 }
304
305 /**
306 * board_ehci_hcd_init - set usb vbus voltage
307 * @port: usb otg port
308 *
309 * Target board specific, setup iomux pad to setup supply vbus voltage
310 * for usb otg port. Machine board file overrides board_ehci_hcd_init
311 *
312 * Return: 0 Success
313 */
board_ehci_hcd_init(int port)314 int __weak board_ehci_hcd_init(int port)
315 {
316 return 0;
317 }
318
319 /**
320 * board_ehci_power - enables/disables usb vbus voltage
321 * @port: usb otg port
322 * @on: on/off vbus voltage
323 *
324 * Enables/disables supply vbus voltage for usb otg port.
325 * Machine board file overrides board_ehci_power
326 *
327 * Return: 0 Success
328 */
board_ehci_power(int port,int on)329 int __weak board_ehci_power(int port, int on)
330 {
331 return 0;
332 }
333
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)334 int ehci_hcd_init(int index, enum usb_init_type init,
335 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
336 {
337 enum usb_init_type type;
338 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
339 u32 controller_spacing = 0x200;
340 struct anatop_regs __iomem *anatop =
341 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
342 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
343 USB_OTHERREGS_OFFSET);
344 #elif defined(CONFIG_MX7)
345 u32 controller_spacing = 0x10000;
346 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
347 (0x10000 * index) + USBNC_OFFSET);
348 #elif defined(CONFIG_MX7ULP)
349 u32 controller_spacing = 0x10000;
350 struct usbphy_regs __iomem *usbphy =
351 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
352 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
353 (0x10000 * index) + USBNC_OFFSET);
354 #endif
355 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
356 (controller_spacing * index));
357 int ret;
358
359 if (index > 3)
360 return -EINVAL;
361
362 if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
363 if (usb_fused((ulong)ehci)) {
364 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
365 (ulong)ehci);
366 return -ENODEV;
367 }
368 }
369
370 enable_usboh3_clk(1);
371 mdelay(1);
372
373 /* Do board specific initialization */
374 ret = board_ehci_hcd_init(index);
375 if (ret) {
376 enable_usboh3_clk(0);
377 return ret;
378 }
379
380 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
381 usb_power_config_mx6(anatop, index);
382 #elif defined (CONFIG_MX7)
383 usb_power_config_mx7(usbnc);
384 #elif defined (CONFIG_MX7ULP)
385 usb_power_config_mx7ulp(usbphy);
386 #endif
387
388 usb_oc_config(usbnc, index);
389
390 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
391 if (index < ARRAY_SIZE(phy_bases)) {
392 usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
393 usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
394 }
395 #endif
396
397 type = board_usb_phy_mode(index);
398
399 if (hccr && hcor) {
400 *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
401 *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
402 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
403 }
404
405 if ((type == init) || (type == USB_INIT_DEVICE))
406 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
407 if (type != init)
408 return -ENODEV;
409 if (type == USB_INIT_DEVICE)
410 return 0;
411
412 setbits_le32(&ehci->usbmode, CM_HOST);
413 writel(CFG_MXC_USB_PORTSC, &ehci->portsc);
414 setbits_le32(&ehci->portsc, USB_EN);
415
416 mdelay(10);
417
418 return 0;
419 }
420
ehci_hcd_stop(int index)421 int ehci_hcd_stop(int index)
422 {
423 return 0;
424 }
425 #else
426 struct ehci_mx6_priv_data {
427 struct ehci_ctrl ctrl;
428 struct usb_ehci *ehci;
429 struct udevice *vbus_supply;
430 struct clk clk;
431 struct phy phy;
432 enum usb_init_type init_type;
433 enum usb_phy_interface phy_type;
434 #if !defined(CONFIG_PHY)
435 int portnr;
436 void __iomem *phy_addr;
437 void __iomem *misc_addr;
438 void __iomem *anatop_addr;
439 #endif
440 };
441
mx6_portsc(enum usb_phy_interface phy_type)442 static u32 mx6_portsc(enum usb_phy_interface phy_type)
443 {
444 switch (phy_type) {
445 case USBPHY_INTERFACE_MODE_UTMI:
446 return PORT_PTS_UTMI;
447 case USBPHY_INTERFACE_MODE_UTMIW:
448 return PORT_PTS_UTMI | PORT_PTS_PTW;
449 case USBPHY_INTERFACE_MODE_ULPI:
450 return PORT_PTS_ULPI;
451 case USBPHY_INTERFACE_MODE_SERIAL:
452 return PORT_PTS_SERIAL;
453 case USBPHY_INTERFACE_MODE_HSIC:
454 return PORT_PTS_HSIC;
455 default:
456 return CFG_MXC_USB_PORTSC;
457 }
458 }
459
mx6_init_after_reset(struct ehci_ctrl * dev)460 static int mx6_init_after_reset(struct ehci_ctrl *dev)
461 {
462 struct ehci_mx6_priv_data *priv = dev->priv;
463 enum usb_init_type type = priv->init_type;
464 struct usb_ehci *ehci = priv->ehci;
465
466 #if !defined(CONFIG_PHY)
467 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
468 usb_power_config_mx7(priv->misc_addr);
469 usb_power_config_mx7ulp(priv->phy_addr);
470
471 usb_oc_config(priv->misc_addr, priv->portnr);
472
473 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
474 usb_internal_phy_clock_gate(priv->phy_addr, 1);
475 usb_phy_enable(ehci, priv->phy_addr);
476 #endif
477 #endif
478
479 #if CONFIG_IS_ENABLED(DM_REGULATOR)
480 if (priv->vbus_supply) {
481 int ret;
482 ret = regulator_set_enable_if_allowed(priv->vbus_supply,
483 (type == USB_INIT_DEVICE) ?
484 false : true);
485 if (ret && ret != -ENOSYS) {
486 printf("Error enabling VBUS supply (ret=%i)\n", ret);
487 return ret;
488 }
489 }
490 #endif
491
492 if (type == USB_INIT_DEVICE)
493 return 0;
494
495 setbits_le32(&ehci->usbmode, CM_HOST);
496 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
497 setbits_le32(&ehci->portsc, USB_EN);
498
499 mdelay(10);
500
501 return 0;
502 }
503
504 static const struct ehci_ops mx6_ehci_ops = {
505 .init_after_reset = mx6_init_after_reset
506 };
507
ehci_usb_phy_mode(struct udevice * dev)508 static int ehci_usb_phy_mode(struct udevice *dev)
509 {
510 struct usb_plat *plat = dev_get_plat(dev);
511 void *__iomem addr = dev_read_addr_ptr(dev);
512 void *__iomem phy_ctrl, *__iomem phy_status;
513 const void *blob = gd->fdt_blob;
514 int offset = dev_of_offset(dev), phy_off;
515 u32 val;
516
517 /*
518 * About fsl,usbphy, Refer to
519 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
520 */
521 if (is_mx6() || is_mx7ulp() || is_imxrt()) {
522 phy_off = fdtdec_lookup_phandle(blob,
523 offset,
524 "fsl,usbphy");
525 if (phy_off < 0)
526 return -EINVAL;
527
528 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
529 "reg");
530 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
531 return -EINVAL;
532
533 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
534 val = readl(phy_ctrl);
535
536 if (val & USBPHY_CTRL_OTG_ID)
537 plat->init_type = USB_INIT_DEVICE;
538 else
539 plat->init_type = USB_INIT_HOST;
540 } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) {
541 phy_status = (void __iomem *)(addr +
542 USBNC_PHY_STATUS_OFFSET);
543 val = readl(phy_status);
544
545 if (val & USBNC_PHYSTATUS_ID_DIG)
546 plat->init_type = USB_INIT_DEVICE;
547 else
548 plat->init_type = USB_INIT_HOST;
549 } else {
550 return -EINVAL;
551 }
552
553 return 0;
554 }
555
ehci_usb_of_to_plat(struct udevice * dev)556 static int ehci_usb_of_to_plat(struct udevice *dev)
557 {
558 struct usb_plat *plat = dev_get_plat(dev);
559 enum usb_dr_mode dr_mode;
560
561 dr_mode = usb_get_dr_mode(dev_ofnode(dev));
562
563 switch (dr_mode) {
564 case USB_DR_MODE_HOST:
565 plat->init_type = USB_INIT_HOST;
566 break;
567 case USB_DR_MODE_PERIPHERAL:
568 plat->init_type = USB_INIT_DEVICE;
569 break;
570 default:
571 plat->init_type = USB_INIT_UNKNOWN;
572 };
573
574 return 0;
575 }
576
mx6_parse_dt_addrs(struct udevice * dev)577 static int mx6_parse_dt_addrs(struct udevice *dev)
578 {
579 #if !defined(CONFIG_PHY)
580 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
581 int phy_off, misc_off;
582 const void *blob = gd->fdt_blob;
583 int offset = dev_of_offset(dev);
584 void *__iomem addr;
585
586 phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
587 if (phy_off < 0) {
588 phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
589 if (phy_off < 0)
590 return -EINVAL;
591 }
592
593 misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
594 if (misc_off < 0)
595 return -EINVAL;
596
597 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
598 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
599 addr = NULL;
600
601 priv->phy_addr = addr;
602
603 addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
604 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
605 return -EINVAL;
606
607 priv->misc_addr = addr;
608
609 #if defined(CONFIG_MX6)
610 int anatop_off, ret, devnump;
611
612 ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
613 phy_off, &devnump);
614 if (ret < 0)
615 return ret;
616 priv->portnr = devnump;
617
618 /* Resolve ANATOP offset through USB PHY node */
619 anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
620 if (anatop_off < 0)
621 return -EINVAL;
622
623 addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
624 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
625 return -EINVAL;
626
627 priv->anatop_addr = addr;
628 #endif
629 #endif
630 return 0;
631 }
632
ehci_usb_probe(struct udevice * dev)633 static int ehci_usb_probe(struct udevice *dev)
634 {
635 struct usb_plat *plat = dev_get_plat(dev);
636 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
637 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
638 enum usb_init_type type = plat->init_type;
639 struct ehci_hccr *hccr;
640 struct ehci_hcor *hcor;
641 int ret;
642
643 if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
644 if (usb_fused((ulong)ehci)) {
645 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
646 (ulong)ehci);
647 return -ENODEV;
648 }
649 }
650
651 ret = mx6_parse_dt_addrs(dev);
652 if (ret)
653 return ret;
654
655 priv->ehci = ehci;
656 priv->init_type = type;
657 priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
658
659 #if CONFIG_IS_ENABLED(CLK)
660 ret = clk_get_by_index(dev, 0, &priv->clk);
661 if (ret < 0)
662 return ret;
663
664 ret = clk_enable(&priv->clk);
665 if (ret)
666 return ret;
667 #else
668 /* Compatibility with DM_USB and !CLK */
669 enable_usboh3_clk(1);
670 mdelay(1);
671 #endif
672
673 /*
674 * If the device tree didn't specify host or device,
675 * the default is USB_INIT_UNKNOWN, so we need to check
676 * the register. For imx8mm and imx8mn, the clocks need to be
677 * running first, so we defer the check until they are.
678 */
679 if (priv->init_type == USB_INIT_UNKNOWN) {
680 ret = ehci_usb_phy_mode(dev);
681 if (ret)
682 goto err_clk;
683 else
684 priv->init_type = plat->init_type;
685 }
686
687 #if CONFIG_IS_ENABLED(DM_REGULATOR)
688 ret = device_get_supply_regulator(dev, "vbus-supply",
689 &priv->vbus_supply);
690 if (ret)
691 debug("%s: No vbus supply\n", dev->name);
692 #endif
693
694 #if !defined(CONFIG_PHY)
695 usb_power_config_mx6(priv->anatop_addr, priv->portnr);
696 usb_power_config_mx7(priv->misc_addr);
697 usb_power_config_mx7ulp(priv->phy_addr);
698
699 usb_oc_config(priv->misc_addr, priv->portnr);
700
701 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
702 usb_internal_phy_clock_gate(priv->phy_addr, 1);
703 usb_phy_enable(ehci, priv->phy_addr);
704 #endif
705 #else
706 ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0);
707 if (ret)
708 goto err_regulator;
709 #endif
710
711 if (priv->init_type == USB_INIT_HOST) {
712 setbits_le32(&ehci->usbmode, CM_HOST);
713 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
714 setbits_le32(&ehci->portsc, USB_EN);
715 }
716
717 mdelay(10);
718
719 hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
720 hcor = (struct ehci_hcor *)((uintptr_t)hccr +
721 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
722
723 ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
724 if (ret)
725 goto err_phy;
726
727 return ret;
728
729 err_phy:
730 #if defined(CONFIG_PHY)
731 generic_shutdown_phy(&priv->phy);
732 err_regulator:
733 #endif
734 err_clk:
735 #if CONFIG_IS_ENABLED(CLK)
736 clk_disable(&priv->clk);
737 #else
738 /* Compatibility with DM_USB and !CLK */
739 enable_usboh3_clk(0);
740 #endif
741 return ret;
742 }
743
ehci_usb_remove(struct udevice * dev)744 int ehci_usb_remove(struct udevice *dev)
745 {
746 struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
747
748 ehci_deregister(dev);
749
750 #if defined(CONFIG_PHY)
751 generic_shutdown_phy(&priv->phy);
752 #endif
753
754 #if CONFIG_IS_ENABLED(DM_REGULATOR)
755 if (priv->vbus_supply)
756 regulator_set_enable(priv->vbus_supply, false);
757 #endif
758
759 #if CONFIG_IS_ENABLED(CLK)
760 clk_disable(&priv->clk);
761 #endif
762
763 return 0;
764 }
765
766 static const struct udevice_id mx6_usb_ids[] = {
767 { .compatible = "fsl,imx27-usb" },
768 { .compatible = "fsl,imx7d-usb" },
769 { .compatible = "fsl,imxrt-usb" },
770 { }
771 };
772
773 U_BOOT_DRIVER(usb_mx6) = {
774 .name = "ehci_mx6",
775 .id = UCLASS_USB,
776 .of_match = mx6_usb_ids,
777 .of_to_plat = ehci_usb_of_to_plat,
778 .probe = ehci_usb_probe,
779 .remove = ehci_usb_remove,
780 .ops = &ehci_usb_ops,
781 .plat_auto = sizeof(struct usb_plat),
782 .priv_auto = sizeof(struct ehci_mx6_priv_data),
783 .flags = DM_FLAG_ALLOC_PRIV_DMA,
784 };
785 #endif
786