| /drivers/mtd/spi/ |
| A D | spi-nor-ids.c | 22 #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument
37 #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument
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| /drivers/clk/sophgo/ |
| A D | clk-ip.h | 103 _flags) \ argument
117 _div_init, _flags) \ argument
136 _flags) \ argument
148 _div, _flags) \ argument
164 _flags) \ argument
177 _flags) \ argument
200 _flags) \ argument
220 _flags) \ argument
256 _flags) \ argument
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| A D | clk-pll.h | 38 _flags) \ argument
56 _flags) \ argument
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| /drivers/clk/mediatek/ |
| A D | clk-mtk.h | 106 #define FACTOR(_id, _parent, _mult, _div, _flags) { \ argument
127 #define PARENT(_id, _flags) { \ argument
167 _flags) { \ argument
182 #define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ argument
195 #define MUX_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ argument
210 _upd_ofs, _upd, _flags) { \ argument
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| A D | clk-mt7987.c | 594 #define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ argument
605 #define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ argument
616 #define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ argument
627 #define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ argument
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| A D | clk-mt7623.c | 44 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
775 #define GATE_INFRA_FLAGS(_id, _parent, _shift, _flags) { \ argument
890 #define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \ argument
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| A D | clk-mt7986.c | 417 #define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ argument
428 #define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ argument
439 #define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ argument
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| A D | clk-mt7988.c | 563 #define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ argument
574 #define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ argument
585 #define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ argument
596 #define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ argument
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| A D | clk-mt7981.c | 411 #define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ argument
422 #define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ argument
433 #define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ argument
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| A D | clk-mt7622.c | 32 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
449 #define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \ argument
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| A D | clk-mt8183.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ argument
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| A D | clk-mt8516.c | 20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt8365.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt8512.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt8518.c | 20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt7629.c | 32 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| /drivers/clk/stm32/ |
| A D | clk-stm32-core.h | 225 #define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \ argument
244 #define STM32_COMPOSITE(_id, _name, _flags, _sec_id, \ argument
259 #define STM32_COMPOSITE_NOMUX(_id, _name, _parent, _flags, _sec_id, \ argument
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| A D | clk-stm32mp13.c | 449 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table) \ argument
594 #define PCLK(_id, _name, _parent, _flags, _gate_id, _sec_id) \ argument
597 #define TIMER(_id, _name, _parent, _flags, _gate_id, _sec_id) \ argument
601 #define KCLK(_id, _name, _flags, _gate_id, _mux_id, _sec_id) \ argument
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| A D | clk-stm32mp25.c | 441 #define STM32_COMPOSITE_NODIV(_id, _name, _flags, _sec_id, _gate_id, _mux_id)\ argument
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| /drivers/clk/microchip/ |
| A D | mpfs_clk_cfg.c | 104 #define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \ argument
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| A D | mpfs_clk_msspll.c | 76 #define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \ argument
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| A D | mpfs_clk_periph.c | 107 #define CLK_PERIPH(_id, _name, _parent_id, _shift, _flags) { \ argument
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| /drivers/clk/thead/ |
| A D | clk-th1520-ap.c | 79 #define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
86 #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ argument
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| /drivers/pinctrl/ |
| A D | pinctrl-th1520.c | 115 #define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \ argument
|