Searched defs:_name (Results 1 – 25 of 48) sorted by relevance

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/drivers/clk/mediatek/
A D	clk-mt7987.c	22 #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ argument 25 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ argument 600 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument 602 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument 611 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument 613 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument 622 #define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ argument 624 #define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ argument 633 #define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ argument 635 #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ argument [all …]
A D	clk-mt7988.c	24 #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ argument 27 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ argument 569 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument 571 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument 580 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument 582 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument 591 #define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ argument 593 #define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ argument 602 #define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ argument 604 #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ argument [all …]
A D	clk-mt7986.c	26 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ argument 29 #define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ argument 32 #define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ argument 227 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ argument 364 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument 423 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument 425 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument 434 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument 436 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument 445 #define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ argument [all …]
A D	clk-mt7981.c	21 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ argument 24 #define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ argument 27 #define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ argument 231 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ argument 357 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument 417 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument 419 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument 428 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument 430 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument 439 #define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ argument [all …]
/drivers/mtd/spi/
A D	spi-nor-ids.c	16 #define INFO_NAME(_name) .name = _name, argument 18 #define INFO_NAME(_name) argument 22 #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument 37 #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ argument
/drivers/clk/renesas/
A D	rcar-gen3-cpg.h	59 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument 62 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument 75 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument 78 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ argument 82 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument 85 #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ argument 89 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ argument 93 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument 96 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument 104 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ argument [all …]
A D	rzg2l-cpg.h	137 #define DEF_TYPE(_name, _id, _type...) \ argument 139 #define DEF_BASE(_name, _id, _type, _parent...) \ argument 141 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument 143 #define DEF_INPUT(_name, _id) \ argument 145 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument 147 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ argument 155 #define DEF_MUX(_name, _id, _conf, _parent_names) \ argument 160 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ argument 169 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ argument 175 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ argument [all …]
A D	renesas-cpg-mssr.h	79 #define DEF_TYPE(_name, _id, _type...) \ argument 81 #define DEF_BASE(_name, _id, _type, _parent...) \ argument 84 #define DEF_INPUT(_name, _id) \ argument 86 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument 88 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument 90 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument 92 #define DEF_RATE(_name, _id, _rate) \ argument 109 #define DEF_MOD(_name, _mod, _parent...) \ argument
A D	r8a779a0-cpg-mssr.c	54 #define DEF_PLL(_name, _id, _offset) \ argument
/drivers/power/regulator/
A D	pfuze100.c	50 #define PFUZE100_FIXED_REG(_name, base, vol) \ argument 57 #define PFUZE100_SW_REG(_name, base, step) \ argument 68 #define PFUZE100_SWB_REG(_name, base, mask, step, voltages) \ argument 78 #define PFUZE100_SNVS_REG(_name, base, mask, voltages) \ argument 87 #define PFUZE100_VGEN_REG(_name, base, step) \ argument 98 #define PFUZE3000_VCC_REG(_name, base, step) \ argument 109 #define PFUZE3000_SW1_REG(_name, base, step) \ argument 120 #define PFUZE3000_SW2_REG(_name, base, step) \ argument 131 #define PFUZE3000_SW3_REG(_name, base, step) \ argument 211 #define MODE(_id, _val, _name) { \ argument
/drivers/clk/sophgo/
A D	clk-ip.h	101 #define CV1800B_GATE(_id, _name, _parent, \ argument 114 #define CV1800B_DIV(_id, _name, _parent, \ argument 131 #define CV1800B_BYPASS_DIV(_id, _name, _parent, \ argument 146 #define CV1800B_FIXED_DIV(_id, _name, _parent, \ argument 160 #define CV1800B_BYPASS_FIXED_DIV(_id, _name, _parent, \ argument 173 #define CV1800B_MUX(_id, _name, _parents, \ argument 194 #define CV1800B_BYPASS_MUX(_id, _name, _parents, \ argument 212 #define CV1800B_MMUX(_id, _name, _parents, \ argument 249 #define CV1800B_AUDIO(_id, _name, _parent, \ argument
A D	clk-pll.h	36 #define CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \ argument 52 #define CV1800B_FPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \ argument
/drivers/clk/meson/
A D	a1.c	105 #define CLK_MUX(_name, _reg, _shift, _width, ...) \ argument 118 #define CLK_DIV(_name, _reg, _shift, _width, _parent) \ argument 131 #define CLK_DIV_FIXED(_name, _div, _parent) \ argument 140 #define CLK_EXTERNAL(_name) \ argument 148 #define CLK_GATE(_name, _reg, _shift, _parent) \ argument 161 #define CLK_PLL(_name, _parent, ...) \ argument
/drivers/pinctrl/mtmips/
A D	pinctrl-mtmips-common.h	43 #define GRP(_name, _funcs, _reg, _shift, _mask) \ argument 47 #define GRP_PCONF(_name, _funcs, _reg, _shift, _mask, _pconf_reg, _pconf_shift) \ argument
/drivers/clk/starfive/
A D	clk.h	13 #define _JH7110_CLK_OPS(_name) \ argument
/drivers/clk/stm32/
A D	clk-stm32-core.h	225 #define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \ argument 244 #define STM32_COMPOSITE(_id, _name, _flags, _sec_id, \ argument 259 #define STM32_COMPOSITE_NOMUX(_id, _name, _parent, _flags, _sec_id, \ argument
/drivers/pinctrl/mvebu/
A D	pinctrl-armada-37xx.c	102 #define PIN_GRP_GPIO_0(_name, _start, _nr) \ argument 112 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ argument 122 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ argument 132 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ argument 142 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ argument
A D	pinctrl-armada-38x.c	26 #define MPP_MODE(_name, ...) \ argument 36 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
/drivers/pinctrl/nuvoton/
A D	pinctrl-npcm8xx.c	289 #define FUNC(_name, _reg, _bit, ...) \ argument 295 #define FUNC(_name, _reg, _bit, ...) \ argument 303 #define FUNC(_name, _reg, _bit, ...) { \ argument
/drivers/pinctrl/mediatek/
A D	pinctrl-mt7986.c	12 #define MT7986_TYPE0_PIN(_number, _name) \ argument 15 #define MT7986_TYPE1_PIN(_number, _name) \ argument
A D	pinctrl-mt7987.c	32 #define MT7987_TYPE0_PIN(_number, _name) \ argument 35 #define MT7987_TYPE1_PIN(_number, _name) \ argument
/drivers/clk/exynos/
A D	clk.h	16 #define _SAMSUNG_CLK_OPS(_name, _cmu) \ argument 198 #define PLL(_typ, _id, _name, _pname, _con) \ argument
/drivers/clk/microchip/
A D	mpfs_clk_cfg.c	104 #define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \ argument
A D	mpfs_clk_msspll.c	76 #define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \ argument
A D	mpfs_clk_periph.c	107 #define CLK_PERIPH(_id, _name, _parent_id, _shift, _flags) { \ argument

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Last Index update Fri Aug 22 02:48:31 CST 2025