| /drivers/ufs/ |
| A D | ufs-renesas.c | 42 #define PARAM_RESTORE(_reg, _index) \ argument
46 #define PARAM_SAVE(_reg, _mask, _index) \ argument
49 #define PARAM_POLL(_reg, _expected, _mask) \ argument
55 #define PARAM_WRITE(_reg, _val) \ argument
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| /drivers/clk/mediatek/ |
| A D | clk-mtk.h | 166 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ argument
179 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ argument
182 #define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ argument
192 #define MUX_MIXED(_id, _parents, _reg, _shift, _width) \ argument
195 #define MUX_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ argument
205 #define MUX(_id, _parents, _reg, _shift, _width) \ argument
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| A D | clk-mt7622.c | 32 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
430 #define PERI_MUX(_id, _parents, _reg, _shift, _width) \ argument
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| A D | clk-mt8183.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ argument
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| A D | clk-mt8516.c | 20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt8365.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt8512.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt8518.c | 20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt7629.c | 32 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt7623.c | 44 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
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| A D | clk-mt7986.c | 364 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
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| A D | clk-mt7981.c | 357 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
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| A D | clk-mt7987.c | 538 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
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| A D | clk-mt7988.c | 483 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
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| /drivers/reset/ |
| A D | sti-reset.c | 83 #define STIH407_SRST_CORE(_reg, _bit) \ argument
86 #define STIH407_SRST_SBC(_reg, _bit) \ argument
89 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| A D | reset-uniphier.c | 32 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
39 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
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| /drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 59 #define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit) \ argument
70 #define UNIPHIER_CLK_GATE_SIMPLE(_id, _reg, _bit) \ argument
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| /drivers/pinctrl/mtmips/ |
| A D | pinctrl-mtmips-common.h | 43 #define GRP(_name, _funcs, _reg, _shift, _mask) \ argument
47 #define GRP_PCONF(_name, _funcs, _reg, _shift, _mask, _pconf_reg, _pconf_shift) \ argument
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| /drivers/pinctrl/nuvoton/ |
| A D | pinctrl-npcm8xx.c | 289 #define FUNC(_name, _reg, _bit, ...) \ argument
295 #define FUNC(_name, _reg, _bit, ...) \ argument
303 #define FUNC(_name, _reg, _bit, ...) { \ argument
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| /drivers/clk/meson/ |
| A D | a1.c | 105 #define CLK_MUX(_name, _reg, _shift, _width, ...) \ argument
118 #define CLK_DIV(_name, _reg, _shift, _width, _parent) \ argument
148 #define CLK_GATE(_name, _reg, _shift, _parent) \ argument
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| A D | clk_meson.h | 19 #define MESON_GATE(id, _reg, _bit) \ argument
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| /drivers/clk/renesas/ |
| A D | rcar-cpg-lib.c | 34 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) argument
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| A D | r9a06g032-clocks.c | 45 #define RB(_reg, _bit) ((struct regbit) { \ argument
183 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \ argument
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| /drivers/power/regulator/ |
| A D | cpcap_regulator.c | 56 #define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask, \ argument
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| /drivers/net/ |
| A D | hifemac.c | 405 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) argument
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