1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * This file is part of the libpayload project. 4 * 5 * Copyright (C) 2008 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _COREBOOT_TABLES_H 9 #define _COREBOOT_TABLES_H 10 11 #include <linux/kernel.h> 12 #include <linux/types.h> 13 14 struct timestamp_entry { 15 u32 entry_id; 16 u64 entry_stamp; 17 } __packed; 18 19 struct timestamp_table { 20 u64 base_time; 21 u16 max_entries; 22 u16 tick_freq_mhz; 23 u32 num_entries; 24 struct timestamp_entry entries[0]; /* Variable number of entries */ 25 } __packed; 26 27 enum timestamp_id { 28 /* coreboot-specific timestamp IDs */ 29 TS_START_ROMSTAGE = 1, 30 TS_BEFORE_INITRAM = 2, 31 TS_AFTER_INITRAM = 3, 32 TS_END_ROMSTAGE = 4, 33 TS_START_VBOOT = 5, 34 TS_END_VBOOT = 6, 35 TS_START_COPYRAM = 8, 36 TS_END_COPYRAM = 9, 37 TS_START_RAMSTAGE = 10, 38 TS_START_BOOTBLOCK = 11, 39 TS_END_BOOTBLOCK = 12, 40 TS_START_COPYROM = 13, 41 TS_END_COPYROM = 14, 42 TS_START_ULZMA = 15, 43 TS_END_ULZMA = 16, 44 TS_START_ULZ4F = 17, 45 TS_END_ULZ4F = 18, 46 TS_DEVICE_ENUMERATE = 30, 47 TS_DEVICE_CONFIGURE = 40, 48 TS_DEVICE_ENABLE = 50, 49 TS_DEVICE_INITIALIZE = 60, 50 TS_DEVICE_DONE = 70, 51 TS_CBMEM_POST = 75, 52 TS_WRITE_TABLES = 80, 53 TS_FINALIZE_CHIPS = 85, 54 TS_LOAD_PAYLOAD = 90, 55 TS_ACPI_WAKE_JUMP = 98, 56 TS_SELFBOOT_JUMP = 99, 57 58 /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ 59 TS_START_COPYVER = 501, 60 TS_END_COPYVER = 502, 61 TS_START_TPMINIT = 503, 62 TS_END_TPMINIT = 504, 63 TS_START_VERIFY_SLOT = 505, 64 TS_END_VERIFY_SLOT = 506, 65 TS_START_HASH_BODY = 507, 66 TS_DONE_LOADING = 508, 67 TS_DONE_HASHING = 509, 68 TS_END_HASH_BODY = 510, 69 TS_START_COPYVPD = 550, 70 TS_END_COPYVPD_RO = 551, 71 TS_END_COPYVPD_RW = 552, 72 73 /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ 74 TS_ME_INFORM_DRAM_WAIT = 940, 75 TS_ME_INFORM_DRAM_DONE = 941, 76 77 /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ 78 TS_FSP_MEMORY_INIT_START = 950, 79 TS_FSP_MEMORY_INIT_END = 951, 80 TS_FSP_TEMP_RAM_EXIT_START = 952, 81 TS_FSP_TEMP_RAM_EXIT_END = 953, 82 TS_FSP_SILICON_INIT_START = 954, 83 TS_FSP_SILICON_INIT_END = 955, 84 TS_FSP_BEFORE_ENUMERATE = 956, 85 TS_FSP_AFTER_ENUMERATE = 957, 86 TS_FSP_BEFORE_FINALIZE = 958, 87 TS_FSP_AFTER_FINALIZE = 959, 88 TS_FSP_BEFORE_END_OF_FIRMWARE = 960, 89 TS_FSP_AFTER_END_OF_FIRMWARE = 961, 90 91 /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */ 92 93 /* U-Boot entry IDs start at 1000 */ 94 TS_U_BOOT_INITTED = 1000, /* This is where U-Boot starts */ 95 96 TS_RO_PARAMS_INIT = 1001, 97 TS_RO_VB_INIT = 1002, 98 TS_RO_VB_SELECT_FIRMWARE = 1003, 99 TS_RO_VB_SELECT_AND_LOAD_KERNEL = 1004, 100 101 TS_RW_VB_SELECT_AND_LOAD_KERNEL = 1010, 102 103 TS_VB_SELECT_AND_LOAD_KERNEL = 1020, 104 TS_VB_EC_VBOOT_DONE = 1030, 105 TS_VB_STORAGE_INIT_DONE = 1040, 106 TS_VB_READ_KERNEL_DONE = 1050, 107 TS_VB_VBOOT_DONE = 1100, 108 109 TS_START_KERNEL = 1101, 110 TS_KERNEL_DECOMPRESSION = 1102, 111 TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel */ 112 }; 113 114 struct memory_area; 115 116 struct cbuint64 { 117 u32 lo; 118 u32 hi; 119 }; 120 121 struct cb_header { 122 u8 signature[4]; 123 u32 header_bytes; 124 u32 header_checksum; 125 u32 table_bytes; 126 u32 table_checksum; 127 u32 table_entries; 128 }; 129 130 struct cb_record { 131 u32 tag; 132 u32 size; 133 }; 134 135 #define CB_TAG_UNUSED 0x0000 136 #define CB_TAG_MEMORY 0x0001 137 138 struct cb_memory_range { 139 struct cbuint64 start; 140 struct cbuint64 size; 141 u32 type; 142 }; 143 144 #define CB_MEM_RAM 1 145 #define CB_MEM_RESERVED 2 146 #define CB_MEM_ACPI 3 147 #define CB_MEM_NVS 4 148 #define CB_MEM_UNUSABLE 5 149 #define CB_MEM_VENDOR_RSVD 6 150 #define CB_MEM_TABLE 16 151 152 struct cb_memory { 153 u32 tag; 154 u32 size; 155 struct cb_memory_range map[0]; 156 }; 157 158 #define CB_TAG_HWRPB 0x0002 159 160 struct cb_hwrpb { 161 u32 tag; 162 u32 size; 163 u64 hwrpb; 164 }; 165 166 #define CB_TAG_MAINBOARD 0x0003 167 168 struct cb_mainboard { 169 u32 tag; 170 u32 size; 171 u8 vendor_idx; 172 u8 part_number_idx; 173 u8 strings[0]; 174 }; 175 176 #define CB_TAG_VERSION 0x0004 177 #define CB_TAG_EXTRA_VERSION 0x0005 178 #define CB_TAG_BUILD 0x0006 179 #define CB_TAG_COMPILE_TIME 0x0007 180 #define CB_TAG_COMPILE_BY 0x0008 181 #define CB_TAG_COMPILE_HOST 0x0009 182 #define CB_TAG_COMPILE_DOMAIN 0x000a 183 #define CB_TAG_COMPILER 0x000b 184 #define CB_TAG_LINKER 0x000c 185 #define CB_TAG_ASSEMBLER 0x000d 186 187 struct cb_string { 188 u32 tag; 189 u32 size; 190 u8 string[0]; 191 }; 192 193 #define CB_TAG_SERIAL 0x000f 194 195 struct cb_serial { 196 u32 tag; 197 u32 size; 198 #define CB_SERIAL_TYPE_IO_MAPPED 1 199 #define CB_SERIAL_TYPE_MEMORY_MAPPED 2 200 u32 type; 201 u32 baseaddr; 202 u32 baud; 203 u32 regwidth; 204 205 /* 206 * Crystal or input frequency to the chip containing the UART. 207 * Provide the board specific details to allow the payload to 208 * initialize the chip containing the UART and make independent 209 * decisions as to which dividers to select and their values 210 * to eventually arrive at the desired console baud-rate. 211 */ 212 u32 input_hertz; 213 214 /* 215 * UART PCI address: bus, device, function 216 * 1 << 31 - Valid bit, PCI UART in use 217 * Bus << 20 218 * Device << 15 219 * Function << 12 220 */ 221 u32 uart_pci_addr; 222 }; 223 224 #define CB_TAG_CONSOLE 0x0010 225 226 struct cb_console { 227 u32 tag; 228 u32 size; 229 u16 type; 230 }; 231 232 #define CB_TAG_CONSOLE_SERIAL8250 0 233 #define CB_TAG_CONSOLE_VGA 1 /* OBSOLETE */ 234 #define CB_TAG_CONSOLE_BTEXT 2 /* OBSOLETE */ 235 #define CB_TAG_CONSOLE_LOGBUF 3 236 #define CB_TAG_CONSOLE_SROM 4 /* OBSOLETE */ 237 #define CB_TAG_CONSOLE_EHCI 5 238 239 #define CB_TAG_FORWARD 0x0011 240 241 struct cb_forward { 242 u32 tag; 243 u32 size; 244 u64 forward; 245 }; 246 247 #define CB_TAG_FRAMEBUFFER 0x0012 248 249 struct cb_framebuffer { 250 u32 tag; 251 u32 size; 252 u64 physical_address; 253 u32 x_resolution; 254 u32 y_resolution; 255 u32 bytes_per_line; 256 u8 bits_per_pixel; 257 u8 red_mask_pos; 258 u8 red_mask_size; 259 u8 green_mask_pos; 260 u8 green_mask_size; 261 u8 blue_mask_pos; 262 u8 blue_mask_size; 263 u8 reserved_mask_pos; 264 u8 reserved_mask_size; 265 }; 266 267 #define CB_TAG_GPIO 0x0013 268 #define CB_GPIO_ACTIVE_LOW 0 269 #define CB_GPIO_ACTIVE_HIGH 1 270 #define CB_GPIO_MAX_NAME_LENGTH 16 271 struct cb_gpio { 272 u32 port; 273 u32 polarity; 274 u32 value; 275 u8 name[CB_GPIO_MAX_NAME_LENGTH]; 276 }; 277 278 struct cb_gpios { 279 u32 tag; 280 u32 size; 281 u32 count; 282 struct cb_gpio gpios[0]; 283 }; 284 285 #define CB_TAG_FDT 0x0014 286 287 struct cb_fdt { 288 u32 tag; 289 u32 size; /* size of the entire entry */ 290 /* the actual FDT gets placed here */ 291 }; 292 293 #define CB_TAG_VDAT 0x0015 294 295 struct cb_vdat { 296 u32 tag; 297 u32 size; /* size of the entire entry */ 298 void *vdat_addr; 299 u32 vdat_size; 300 }; 301 302 #define CB_TAG_TIMESTAMPS 0x0016 303 #define CB_TAG_CBMEM_CONSOLE 0x0017 304 305 #define CBMC_CURSOR_MASK ((1 << 28) - 1) 306 #define CBMC_OVERFLOW BIT(31) 307 308 /* 309 * struct cbmem_console - In-memory console buffer for coreboot 310 * 311 * Structure describing console buffer. It is overlaid on a flat memory area, 312 * with body covering the extent of the memory. Once the buffer is full, 313 * output will wrap back around to the start of the buffer. The high bit of the 314 * cursor field gets set to indicate that this happened. If the underlying 315 * storage allows this, the buffer will persist across multiple boots and append 316 * to the previous log. 317 */ 318 struct cbmem_console { 319 u32 size; 320 u32 cursor; 321 u8 body[0]; 322 }; 323 324 #define CB_TAG_MRC_CACHE 0x0018 325 326 struct cb_cbmem_tab { 327 u32 tag; 328 u32 size; 329 u64 cbmem_tab; 330 }; 331 332 #define CB_TAG_VBNV 0x0019 333 334 struct cb_vbnv { 335 u32 tag; 336 u32 size; 337 u32 vbnv_start; 338 u32 vbnv_size; 339 }; 340 341 #define CB_TAG_VBOOT_HANDOFF 0x0020 342 343 #define CB_TAG_X86_ROM_MTRR 0x0021 344 struct cb_x86_rom_mtrr { 345 u32 tag; 346 u32 size; 347 /* 348 * The variable range MTRR index covering the ROM. If one wants to 349 * enable caching the ROM, the variable MTRR needs to be set to 350 * write-protect. To disable the caching after enabling set the 351 * type to uncacheable 352 */ 353 u32 index; 354 }; 355 356 #define CB_TAG_DMA 0x0022 357 #define CB_TAG_RAM_OOPS 0x0023 358 #define CB_TAG_ACPI_GNVS 0x0024 359 360 #define CB_TAG_BOARD_ID 0x0025 361 struct cb_board_id { 362 u32 tag; 363 u32 size; 364 /* Board ID as retrieved from the board revision GPIOs. */ 365 u32 board_id; 366 }; 367 368 #define CB_TAG_MAC_ADDRS 0x0026 369 struct mac_address { 370 u8 mac_addr[6]; 371 u8 pad[2]; /* Pad it to 8 bytes to keep it simple. */ 372 }; 373 374 struct cb_macs { 375 u32 tag; 376 u32 size; 377 u32 count; 378 struct mac_address mac_addrs[0]; 379 }; 380 381 #define CB_TAG_WIFI_CALIBRATION 0x0027 382 383 #define CB_TAG_RAM_CODE 0x0028 384 struct cb_ram_code { 385 u32 tag; 386 u32 size; 387 u32 ram_code; 388 }; 389 390 #define CB_TAG_SPI_FLASH 0x0029 391 struct cb_spi_flash { 392 u32 tag; 393 u32 size; 394 u32 flash_size; 395 u32 sector_size; 396 u32 erase_cmd; 397 }; 398 399 #define CB_TAG_MTC 0x002b 400 #define CB_TAG_VPD 0x002c 401 struct lb_range { 402 u32 tag; 403 u32 size; 404 u64 range_start; 405 u32 range_size; 406 }; 407 408 #define CB_TAG_BOOT_MEDIA_PARAMS 0x0030 409 struct cb_boot_media_params { 410 u32 tag; 411 u32 size; 412 /* offsets are relative to start of boot media */ 413 u64 fmap_offset; 414 u64 cbfs_offset; 415 u64 cbfs_size; 416 u64 boot_media_size; 417 }; 418 419 #define CB_TAG_CBMEM_ENTRY 0x0031 420 #define CBMEM_ID_SMBIOS 0x534d4254 421 422 struct cb_cbmem_entry { 423 u32 tag; 424 u32 size; 425 u64 address; 426 u32 entry_size; 427 u32 id; 428 }; 429 430 #define CB_TAG_TSC_INFO 0x0032 431 struct cb_tsc_info { 432 u32 tag; 433 u32 size; 434 435 u32 freq_khz; 436 }; 437 438 #define CB_TAG_SERIALNO 0x002a 439 #define CB_MAX_SERIALNO_LENGTH 32 440 441 #define CB_TAG_ACPI_RSDP 0x0043 442 443 #define CB_TAG_CMOS_OPTION_TABLE 0x00c8 444 445 struct cb_cmos_option_table { 446 u32 tag; 447 u32 size; 448 u32 header_length; 449 /* entries follow after this header */ 450 }; 451 452 #define CB_TAG_OPTION 0x00c9 453 454 #define CB_CMOS_MAX_NAME_LENGTH 32 455 456 struct cb_cmos_entries { 457 u32 tag; 458 u32 size; 459 u32 bit; 460 u32 length; 461 u32 config; 462 u32 config_id; 463 u8 name[CB_CMOS_MAX_NAME_LENGTH]; 464 }; 465 466 #define CB_TAG_OPTION_ENUM 0x00ca 467 #define CB_CMOS_MAX_TEXT_LENGTH 32 468 struct cb_cmos_enums { 469 u32 tag; 470 u32 size; 471 u32 config_id; 472 u32 value; 473 u8 text[CB_CMOS_MAX_TEXT_LENGTH]; 474 }; 475 476 #define CB_TAG_OPTION_DEFAULTS 0x00cb 477 #define CB_CMOS_IMAGE_BUFFER_SIZE 128 478 479 struct cb_cmos_defaults { 480 u32 tag; 481 u32 size; 482 u32 name_length; 483 u8 name[CB_CMOS_MAX_NAME_LENGTH]; 484 u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE]; 485 }; 486 487 #define CB_TAG_OPTION_CHECKSUM 0x00cc 488 #define CB_CHECKSUM_NONE 0 489 #define CB_CHECKSUM_PCBIOS 1 490 491 struct cb_cmos_checksum { 492 u32 tag; 493 u32 size; 494 u32 range_start; 495 u32 range_end; 496 u32 location; 497 u32 type; 498 }; 499 500 /* Helpful macros */ 501 502 #define MEM_RANGE_COUNT(_rec) \ 503 (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0])) 504 505 #define MEM_RANGE_PTR(_rec, _idx) \ 506 (((u8 *) (_rec)) + sizeof(*(_rec)) \ 507 + (sizeof((_rec)->map[0]) * (_idx))) 508 509 #define MB_VENDOR_STRING(_mb) \ 510 (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) 511 512 #define MB_PART_STRING(_mb) \ 513 (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) 514 515 #define UNPACK_CB64(_in) \ 516 ((((u64) _in.hi) << 32) | _in.lo) 517 518 #define CBMEM_TOC_RESERVED 512 519 #define MAX_CBMEM_ENTRIES 16 520 #define CBMEM_MAGIC 0x434f5245 521 522 struct cbmem_entry { 523 u32 magic; 524 u32 id; 525 u64 base; 526 u64 size; 527 } __packed; 528 529 #define CBMEM_ID_FREESPACE 0x46524545 530 #define CBMEM_ID_GDT 0x4c474454 531 #define CBMEM_ID_ACPI 0x41435049 532 #define CBMEM_ID_CBTABLE 0x43425442 533 #define CBMEM_ID_PIRQ 0x49525154 534 #define CBMEM_ID_MPTABLE 0x534d5054 535 #define CBMEM_ID_RESUME 0x5245534d 536 #define CBMEM_ID_RESUME_SCRATCH 0x52455343 537 #define CBMEM_ID_SMBIOS 0x534d4254 538 #define CBMEM_ID_TIMESTAMP 0x54494d45 539 #define CBMEM_ID_MRCDATA 0x4d524344 540 #define CBMEM_ID_CONSOLE 0x434f4e53 541 #define CBMEM_ID_NONE 0x00000000 542 543 /** 544 * high_table_reserve() - reserve configuration table in high memory 545 * 546 * This reserves configuration table in high memory. 547 * 548 * @return: always 0 549 */ 550 int high_table_reserve(void); 551 552 /** 553 * high_table_malloc() - allocate configuration table in high memory 554 * 555 * This allocates configuration table in high memory. 556 * 557 * @bytes: size of configuration table to be allocated 558 * @return: pointer to configuration table in high memory 559 */ 560 void *high_table_malloc(size_t bytes); 561 562 /** 563 * write_coreboot_table() - write coreboot table 564 * 565 * This writes coreboot table at a given address. 566 * 567 * @addr: start address to write coreboot table 568 * @cfg_tables: pointer to configuration table memory area 569 */ 570 void write_coreboot_table(u32 addr, struct memory_area *cfg_tables); 571 572 /** 573 * locate_coreboot_table() - Try to find coreboot tables at standard locations 574 * 575 * Return: address of table that was found, or -ve error number 576 */ 577 long locate_coreboot_table(void); 578 579 #endif 580