1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <log.h>
7 #include <asm/io.h>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/gp_padctrl.h>
10 #include <asm/arch/pinmux.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/scu.h>
15 #include <linux/delay.h>
16 #include "cpu.h"
17
get_num_cpus(void)18 int get_num_cpus(void)
19 {
20 struct apb_misc_gp_ctlr *gp;
21 uint rev;
22 debug("%s entry\n", __func__);
23
24 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
25 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
26
27 switch (rev) {
28 case CHIPID_TEGRA20:
29 return 2;
30 break;
31 case CHIPID_TEGRA30:
32 case CHIPID_TEGRA114:
33 case CHIPID_TEGRA124:
34 case CHIPID_TEGRA210:
35 default:
36 return 4;
37 break;
38 }
39 }
40
41 /*
42 * Timing tables for each SOC for all four oscillator options.
43 */
44 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
45 /*
46 * T20: 1 GHz
47 *
48 * Register Field Bits Width
49 * ------------------------------
50 * PLLX_BASE p 22:20 3
51 * PLLX_BASE n 17: 8 10
52 * PLLX_BASE m 4: 0 5
53 * PLLX_MISC cpcon 11: 8 4
54 */
55 {
56 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
57 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
58 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
60 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
62 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
63 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
64 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
65 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
66 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
67 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
68 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
69 },
70 /*
71 * T25: 1.2 GHz
72 *
73 * Register Field Bits Width
74 * ------------------------------
75 * PLLX_BASE p 22:20 3
76 * PLLX_BASE n 17: 8 10
77 * PLLX_BASE m 4: 0 5
78 * PLLX_MISC cpcon 11: 8 4
79 */
80 {
81 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
82 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
83 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
84 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
85 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
86 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
87 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
88 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
89 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
90 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
91 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
92 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
93 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
94 },
95 /*
96 * T30: 600 MHz
97 *
98 * Register Field Bits Width
99 * ------------------------------
100 * PLLX_BASE p 22:20 3
101 * PLLX_BASE n 17: 8 10
102 * PLLX_BASE m 4: 0 5
103 * PLLX_MISC cpcon 11: 8 4
104 */
105 {
106 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
107 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 16.8 MHz */
108 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
109 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
110 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
111 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 38.4 MHz */
112 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
113 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
114 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
115 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 48.0 MHz */
116 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
117 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
118 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
119 },
120 /*
121 * T114: 700 MHz
122 *
123 * Register Field Bits Width
124 * ------------------------------
125 * PLLX_BASE p 23:20 4
126 * PLLX_BASE n 15: 8 8
127 * PLLX_BASE m 7: 0 8
128 */
129 {
130 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
131 { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
132 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
133 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
134 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
135 { .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
136 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
137 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
138 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
139 { .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
140 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
141 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
142 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
143 },
144
145 /*
146 * T124: 700 MHz
147 *
148 * Register Field Bits Width
149 * ------------------------------
150 * PLLX_BASE p 23:20 4
151 * PLLX_BASE n 15: 8 8
152 * PLLX_BASE m 7: 0 8
153 */
154 {
155 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
156 { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
157 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
158 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
159 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
160 { .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
161 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
162 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
163 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
164 { .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
165 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
166 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
167 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
168 },
169
170 /*
171 * T210: 700 MHz
172 *
173 * Register Field Bits Width
174 * ------------------------------
175 * PLLX_BASE p 24:20 5
176 * PLLX_BASE n 15: 8 8
177 * PLLX_BASE m 7: 0 8
178 */
179 {
180 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz */
181 { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.0 MHz = 702 MHz */
182 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
183 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
184 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz */
185 { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
186 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
187 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
188 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz */
189 { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
190 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
191 { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
192 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz */
193 },
194 };
195
pllx_set_iddq(void)196 static inline void pllx_set_iddq(void)
197 {
198 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
199 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
200 u32 reg;
201 debug("%s entry\n", __func__);
202
203 /* Disable IDDQ */
204 reg = readl(&clkrst->crc_pllx_misc3);
205 reg &= ~PLLX_IDDQ_MASK;
206 writel(reg, &clkrst->crc_pllx_misc3);
207 udelay(2);
208 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
209 readl(&clkrst->crc_pllx_misc3));
210 #endif
211 }
212
pllx_set_rate(struct clk_pll_simple * pll,u32 divn,u32 divm,u32 divp,u32 cpcon)213 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
214 u32 divp, u32 cpcon)
215 {
216 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
217 int chip = tegra_get_chip();
218 u32 reg;
219 debug("%s entry\n", __func__);
220
221 /* If PLLX is already enabled, just return */
222 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
223 debug("%s: PLLX already enabled, returning\n", __func__);
224 return 0;
225 }
226
227 pllx_set_iddq();
228
229 /* Set BYPASS, m, n and p to PLLX_BASE */
230 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
231 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
232 writel(reg, &pll->pll_base);
233
234 /* Set cpcon to PLLX_MISC */
235 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
236 reg = (cpcon << pllinfo->kcp_shift);
237 else
238 reg = 0;
239
240 /*
241 * TODO(twarren@nvidia.com) Check which SoCs use DCCON
242 * and add to pllinfo table if needed!
243 */
244 /* Set dccon to PLLX_MISC if freq > 600MHz */
245 if (divn > 600)
246 reg |= (1 << PLL_DCCON_SHIFT);
247 writel(reg, &pll->pll_misc);
248
249 /* Disable BYPASS */
250 reg = readl(&pll->pll_base);
251 reg &= ~PLL_BYPASS_MASK;
252 writel(reg, &pll->pll_base);
253 debug("%s: base = 0x%08X\n", __func__, reg);
254
255 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
256 reg = readl(&pll->pll_misc);
257 if (pllinfo->lock_ena < 32)
258 reg |= (1 << pllinfo->lock_ena);
259 writel(reg, &pll->pll_misc);
260 debug("%s: misc = 0x%08X\n", __func__, reg);
261
262 /* Enable PLLX last, once it's all configured */
263 reg = readl(&pll->pll_base);
264 reg |= PLL_ENABLE_MASK;
265 writel(reg, &pll->pll_base);
266 debug("%s: base final = 0x%08X\n", __func__, reg);
267
268 return 0;
269 }
270
init_pllx(void)271 void init_pllx(void)
272 {
273 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
274 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
275 int soc_type, sku_info, chip_sku;
276 enum clock_osc_freq osc;
277 struct clk_pll_table *sel;
278 debug("%s entry\n", __func__);
279
280 /* get SOC (chip) type */
281 soc_type = tegra_get_chip();
282 debug("%s: SoC = 0x%02X\n", __func__, soc_type);
283
284 /* get SKU info */
285 sku_info = tegra_get_sku_info();
286 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
287
288 /* get chip SKU, combo of the above info */
289 chip_sku = tegra_get_chip_sku();
290 debug("%s: Chip SKU = %d\n", __func__, chip_sku);
291
292 /* get osc freq */
293 osc = clock_get_osc_freq();
294 debug("%s: osc = %d\n", __func__, osc);
295
296 /* set pllx */
297 sel = &tegra_pll_x_table[chip_sku][osc];
298 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
299 }
300
enable_cpu_clock(int enable)301 void enable_cpu_clock(int enable)
302 {
303 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
304 u32 clk;
305 debug("%s entry\n", __func__);
306
307 /*
308 * NOTE:
309 * Regardless of whether the request is to enable or disable the CPU
310 * clock, every processor in the CPU complex except the master (CPU 0)
311 * will have it's clock stopped because the AVP only talks to the
312 * master.
313 */
314
315 if (enable) {
316 /* Initialize PLLX */
317 init_pllx();
318
319 /* Wait until all clocks are stable */
320 udelay(PLL_STABILIZATION_DELAY);
321
322 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
323 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
324 }
325
326 /*
327 * Read the register containing the individual CPU clock enables and
328 * always stop the clocks to CPUs > 0.
329 */
330 clk = readl(&clkrst->crc_clk_cpu_cmplx);
331 clk |= 1 << CPU1_CLK_STP_SHIFT;
332 if (get_num_cpus() == 4)
333 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
334
335 /* Stop/Unstop the CPU clock */
336 clk &= ~CPU0_CLK_STP_MASK;
337 clk |= !enable << CPU0_CLK_STP_SHIFT;
338 writel(clk, &clkrst->crc_clk_cpu_cmplx);
339
340 clock_enable(PERIPH_ID_CPU);
341 }
342
is_cpu_powered(void)343 static int is_cpu_powered(void)
344 {
345 return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
346 pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
347 }
348
remove_cpu_io_clamps(void)349 static void remove_cpu_io_clamps(void)
350 {
351 u32 reg;
352 debug("%s entry\n", __func__);
353
354 /* Remove the clamps on the CPU I/O signals */
355 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
356 reg |= CPU_CLMP;
357 tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
358
359 /* Give I/O signals time to stabilize */
360 udelay(IO_STABILIZATION_DELAY);
361 }
362
powerup_cpu(void)363 void powerup_cpu(void)
364 {
365 u32 reg;
366 int timeout = IO_STABILIZATION_DELAY;
367 debug("%s entry\n", __func__);
368
369 if (!is_cpu_powered()) {
370 /* Toggle the CPU power state (OFF -> ON) */
371 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
372 pmc_pwrgate_toggle));
373 reg &= PARTID_CP;
374 reg |= START_CP;
375 tegra_pmc_writel(reg,
376 offsetof(struct pmc_ctlr,
377 pmc_pwrgate_toggle));
378
379 /* Wait for the power to come up */
380 while (!is_cpu_powered()) {
381 if (timeout-- == 0)
382 printf("CPU failed to power up!\n");
383 else
384 udelay(10);
385 }
386
387 /*
388 * Remove the I/O clamps from CPU power partition.
389 * Recommended only on a Warm boot, if the CPU partition gets
390 * power gated. Shouldn't cause any harm when called after a
391 * cold boot according to HW, probably just redundant.
392 */
393 remove_cpu_io_clamps();
394 }
395 }
396
reset_A9_cpu(int reset)397 void reset_A9_cpu(int reset)
398 {
399 /*
400 * NOTE: Regardless of whether the request is to hold the CPU in reset
401 * or take it out of reset, every processor in the CPU complex
402 * except the master (CPU 0) will be held in reset because the
403 * AVP only talks to the master. The AVP does not know that there
404 * are multiple processors in the CPU complex.
405 */
406 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
407 int num_cpus = get_num_cpus();
408 int cpu;
409
410 debug("%s entry\n", __func__);
411 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
412 for (cpu = 1; cpu < num_cpus; cpu++)
413 reset_cmplx_set_enable(cpu, mask, 1);
414 reset_cmplx_set_enable(0, mask, reset);
415
416 /* Enable/Disable master CPU reset */
417 reset_set_enable(PERIPH_ID_CPU, reset);
418 }
419
clock_enable_coresight(int enable)420 void clock_enable_coresight(int enable)
421 {
422 u32 rst, src = 2;
423
424 debug("%s entry\n", __func__);
425 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
426 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
427
428 if (enable) {
429 /*
430 * Put CoreSight on PLLP_OUT0 and divide it down as per
431 * PLLP base frequency based on SoC type (T20/T30+).
432 * Clock divider request would setup CSITE clock as 144MHz
433 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
434 */
435 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
436 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
437
438 /* Unlock the CPU CoreSight interfaces */
439 rst = CORESIGHT_UNLOCK;
440 writel(rst, CSITE_CPU_DBG0_LAR);
441 writel(rst, CSITE_CPU_DBG1_LAR);
442 if (get_num_cpus() == 4) {
443 writel(rst, CSITE_CPU_DBG2_LAR);
444 writel(rst, CSITE_CPU_DBG3_LAR);
445 }
446 }
447 }
448
halt_avp(void)449 void halt_avp(void)
450 {
451 debug("%s entry\n", __func__);
452
453 for (;;) {
454 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
455 FLOW_CTLR_HALT_COP_EVENTS);
456 }
457 }
458