1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016 Atmel Corporation 4 * Wenyou.Yang <wenyou.yang@atmel.com> 5 */ 6 7 #ifndef __AT91_PMC_H__ 8 #define __AT91_PMC_H__ 9 10 #include <linux/bitops.h> 11 #include <linux/io.h> 12 13 /* Keep a range of 256 available clocks for every clock type. */ 14 #define AT91_TO_CLK_ID(_t, _i) (((_t) << 8) | ((_i) & 0xff)) 15 #define AT91_CLK_ID_TO_DID(_i) ((_i) & 0xff) 16 17 struct clk_range { 18 unsigned long min; 19 unsigned long max; 20 }; 21 22 struct clk_master_layout { 23 u32 offset; 24 u32 mask; 25 u8 pres_shift; 26 }; 27 28 extern const struct clk_master_layout at91rm9200_master_layout; 29 extern const struct clk_master_layout at91sam9x5_master_layout; 30 31 struct clk_master_characteristics { 32 struct clk_range output; 33 u32 divisors[5]; 34 u8 have_div3_pres; 35 }; 36 37 struct clk_pll_characteristics { 38 struct clk_range input; 39 int num_output; 40 const struct clk_range *output; 41 const struct clk_range *core_output; 42 u16 *icpll; 43 u8 *out; 44 u8 upll : 1; 45 }; 46 47 struct clk_pll_layout { 48 u32 pllr_mask; 49 u32 mul_mask; 50 u32 frac_mask; 51 u32 div_mask; 52 u32 endiv_mask; 53 u8 mul_shift; 54 u8 frac_shift; 55 u8 div_shift; 56 u8 endiv_shift; 57 u8 div2; 58 }; 59 60 struct clk_programmable_layout { 61 u8 pres_mask; 62 u8 pres_shift; 63 u8 css_mask; 64 u8 have_slck_mck; 65 u8 is_pres_direct; 66 }; 67 68 struct clk_pcr_layout { 69 u32 offset; 70 u32 cmd; 71 u32 div_mask; 72 u32 gckcss_mask; 73 u32 pid_mask; 74 }; 75 76 struct clk_usbck_layout { 77 u32 offset; 78 u32 usbs_mask; 79 u32 usbdiv_mask; 80 }; 81 82 /** 83 * Clock setup description 84 * @cid: clock id corresponding to clock subsystem 85 * @pid: parent clock id corresponding to clock subsystem 86 * @rate: clock rate 87 * @prate: parent rate 88 */ 89 struct pmc_clk_setup { 90 unsigned int cid; 91 unsigned int pid; 92 unsigned long rate; 93 unsigned long prate; 94 }; 95 96 extern const struct clk_programmable_layout at91rm9200_programmable_layout; 97 extern const struct clk_programmable_layout at91sam9g45_programmable_layout; 98 extern const struct clk_programmable_layout at91sam9x5_programmable_layout; 99 100 extern const struct clk_ops at91_clk_ops; 101 102 struct clk *at91_clk_main_rc(void __iomem *reg, const char *name, 103 const char *parent_name); 104 struct clk *at91_clk_main_osc(void __iomem *reg, const char *name, 105 const char *parent_name, bool bypass); 106 struct clk *at91_clk_rm9200_main(void __iomem *reg, const char *name, 107 const char *parent_name); 108 struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name, 109 const char * const *parent_names, int num_parents, 110 const u32 *mux_table, int type); 111 struct clk * 112 sam9x60_clk_register_usb(void __iomem *base, const char *name, 113 const char * const *parent_names, u8 num_parents, 114 const struct clk_usbck_layout *usbck_layout, 115 const u32 *clk_mux_table, const u32 *mux_table, u8 id); 116 struct clk * 117 sam9x60_clk_register_div_pll(void __iomem *base, const char *name, 118 const char *parent_name, u8 id, 119 const struct clk_pll_characteristics *characteristics, 120 const struct clk_pll_layout *layout, bool critical); 121 struct clk * 122 sam9x60_clk_register_frac_pll(void __iomem *base, const char *name, 123 const char *parent_name, u8 id, 124 const struct clk_pll_characteristics *characteristics, 125 const struct clk_pll_layout *layout, bool critical); 126 struct clk * 127 at91_clk_register_master_pres(void __iomem *base, const char *name, 128 const char * const *parent_names, int num_parents, 129 const struct clk_master_layout *layout, 130 const struct clk_master_characteristics *characteristics, 131 const u32 *mux_table); 132 struct clk * 133 at91_clk_register_master_div(void __iomem *base, 134 const char *name, const char *parent_name, 135 const struct clk_master_layout *layout, 136 const struct clk_master_characteristics *characteristics); 137 struct clk * 138 at91_clk_sama7g5_register_master(void __iomem *base, const char *name, 139 const char * const *parent_names, int num_parents, 140 const u32 *mux_table, const u32 *clk_mux_table, 141 bool critical, u8 id); 142 struct clk * 143 at91_clk_register_utmi(void __iomem *base, struct udevice *dev, 144 const char *name, const char *parent_name); 145 struct clk * 146 at91_clk_sama7g5_register_utmi(void __iomem *base, const char *name, 147 const char *parent_name); 148 struct clk * 149 at91_clk_register_programmable(void __iomem *base, const char *name, 150 const char * const *parent_names, u8 num_parents, u8 id, 151 const struct clk_programmable_layout *layout, 152 const u32 *clk_mux_table, const u32 *mux_table); 153 struct clk * 154 at91_clk_register_system(void __iomem *base, const char *name, 155 const char *parent_name, u8 id); 156 struct clk * 157 at91_clk_register_peripheral(void __iomem *base, const char *name, 158 const char *parent_name, u32 id); 159 struct clk * 160 at91_clk_register_sam9x5_peripheral(void __iomem *base, 161 const struct clk_pcr_layout *layout, 162 const char *name, const char *parent_name, 163 u32 id, const struct clk_range *range); 164 struct clk * 165 at91_clk_register_generic(void __iomem *base, 166 const struct clk_pcr_layout *layout, const char *name, 167 const char * const *parent_names, 168 const u32 *clk_mux_table, const u32 *mux_table, 169 u8 num_parents, u8 id, const struct clk_range *range); 170 171 int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val); 172 int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index); 173 174 void pmc_read(void __iomem *base, unsigned int off, unsigned int *val); 175 void pmc_write(void __iomem *base, unsigned int off, unsigned int val); 176 void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask, 177 unsigned int bits); 178 179 int at91_clk_setup(const struct pmc_clk_setup *setup, int size); 180 181 #endif 182