1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * HW data initialization for OMAP5
5 *
6 * (C) Copyright 2013
7 * Texas Instruments, <www.ti.com>
8 *
9 * Sricharan R <r.sricharan@ti.com>
10 */
11 #include <palmas.h>
12 #include <asm/arch/omap.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/omap_common.h>
15 #include <asm/arch/clock.h>
16 #include <asm/omap_gpio.h>
17 #include <asm/io.h>
18 #include <asm/emif.h>
19
20 struct prcm_regs const **prcm =
21 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
22 struct dplls const **dplls_data =
23 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
24 struct vcores_data const **omap_vcores =
25 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
26 struct omap_sys_ctrl_regs const **ctrl =
27 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
28
29 /* OPP NOM FREQUENCY for ES1.0 */
30 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
31 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
32 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
33 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
34 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
35 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
36 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
37 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
38 };
39
40 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
41 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
42 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
43 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
44 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
45 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
46 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
47 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
48 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
49 };
50
51 static const struct dpll_params
52 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
53 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
54 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
55 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
56 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
57 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
58 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
59 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
60 };
61
62 static const struct dpll_params
63 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
64 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
65 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
66 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
67 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
68 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
69 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
70 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
71 };
72
73 static const struct dpll_params
74 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
75 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
76 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
77 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
78 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
79 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
80 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
81 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
82 };
83
84 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
85 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
86 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
87 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
88 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
89 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
90 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
91 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
92 };
93
94 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
95 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
96 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
97 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
98 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
99 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
101 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
102 };
103
104 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
105 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
106 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
107 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
108 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
109 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
110 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
111 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
112 };
113
114 static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
115 {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
116 {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
117 {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
118 {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
119 {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
120 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
121 {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
122 };
123
124 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
125 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
127 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
128 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
129 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
130 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
131 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
132 };
133
134 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
135 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
136 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
137 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
138 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
139 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
140 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
141 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
142 };
143
144 /* ABE M & N values with sys_clk as source */
145 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
146 static const struct dpll_params
147 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
148 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
149 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
150 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
151 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
152 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
154 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
155 };
156 #endif
157
158 /* ABE M & N values with 32K clock as source */
159 #ifndef CONFIG_SYS_OMAP_ABE_SYSCK
160 static const struct dpll_params abe_dpll_params_32k_196608khz = {
161 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
162 };
163 #endif
164
165 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
166 static const struct dpll_params
167 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
168 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
169 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
170 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
171 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
172 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
174 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
175 };
176
177 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
178 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
179 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
180 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
181 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
182 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
183 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
184 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
185 };
186
187 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
188 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
189 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
190 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
191 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
192 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
193 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
194 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
195 };
196
197 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
198 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
199 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
200 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
201 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
202 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
203 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
204 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
205 };
206
207 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
208 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
209 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
210 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
211 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
212 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
214 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
215 };
216
217 struct dplls omap5_dplls_es1 = {
218 .mpu = mpu_dpll_params_800mhz,
219 .core = core_dpll_params_2128mhz_ddr532,
220 .per = per_dpll_params_768mhz,
221 .iva = iva_dpll_params_2330mhz,
222 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
223 .abe = abe_dpll_params_sysclk_196608khz,
224 #else
225 .abe = &abe_dpll_params_32k_196608khz,
226 #endif
227 .usb = usb_dpll_params_1920mhz,
228 .ddr = NULL
229 };
230
231 struct dplls omap5_dplls_es2 = {
232 .mpu = mpu_dpll_params_1ghz,
233 .core = core_dpll_params_2128mhz_ddr532_es2,
234 .per = per_dpll_params_768mhz_es2,
235 .iva = iva_dpll_params_2330mhz,
236 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
237 .abe = abe_dpll_params_sysclk_196608khz,
238 #else
239 .abe = &abe_dpll_params_32k_196608khz,
240 #endif
241 .usb = usb_dpll_params_1920mhz,
242 .ddr = NULL
243 };
244
245 struct dplls dra76x_dplls = {
246 .mpu = mpu_dpll_params_1ghz,
247 .core = core_dpll_params_2128mhz_dra7xx,
248 .per = per_dpll_params_768mhz_dra76x,
249 .abe = abe_dpll_params_sysclk2_361267khz,
250 .iva = iva_dpll_params_2330mhz_dra7xx,
251 .usb = usb_dpll_params_1920mhz,
252 .ddr = ddr_dpll_params_2664mhz,
253 .gmac = gmac_dpll_params_2000mhz,
254 };
255
256 struct dplls dra7xx_dplls = {
257 .mpu = mpu_dpll_params_1ghz,
258 .core = core_dpll_params_2128mhz_dra7xx,
259 .per = per_dpll_params_768mhz_dra7xx,
260 .abe = abe_dpll_params_sysclk2_361267khz,
261 .iva = iva_dpll_params_2330mhz_dra7xx,
262 .usb = usb_dpll_params_1920mhz,
263 .ddr = ddr_dpll_params_2128mhz,
264 .gmac = gmac_dpll_params_2000mhz,
265 };
266
267 struct dplls dra72x_dplls = {
268 .mpu = mpu_dpll_params_1ghz,
269 .core = core_dpll_params_2128mhz_dra7xx,
270 .per = per_dpll_params_768mhz_dra7xx,
271 .abe = abe_dpll_params_sysclk2_361267khz,
272 .iva = iva_dpll_params_2330mhz_dra7xx,
273 .usb = usb_dpll_params_1920mhz,
274 .ddr = ddr_dpll_params_2664mhz,
275 .gmac = gmac_dpll_params_2000mhz,
276 };
277
278 struct pmic_data palmas = {
279 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
280 .step = 10000, /* 10 mV represented in uV */
281 /*
282 * Offset codes 1-6 all give the base voltage in Palmas
283 * Offset code 0 switches OFF the SMPS
284 */
285 .start_code = 6,
286 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
287 .pmic_bus_init = sri2c_init,
288 .pmic_write = omap_vc_bypass_send_value,
289 .gpio_en = 0,
290 };
291
292 /* The TPS659038 and TPS65917 are software-compatible, use common struct */
293 struct pmic_data tps659038 = {
294 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
295 .step = 10000, /* 10 mV represented in uV */
296 /*
297 * Offset codes 1-6 all give the base voltage in Palmas
298 * Offset code 0 switches OFF the SMPS
299 */
300 .start_code = 6,
301 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
302 .pmic_bus_init = gpi2c_init,
303 .pmic_write = palmas_i2c_write_u8,
304 .gpio_en = 0,
305 };
306
307 /* The LP87565*/
308 struct pmic_data lp87565 = {
309 .base_offset = LP873X_BUCK_BASE_VOLT_UV,
310 .step = 5000, /* 5 mV represented in uV */
311 /*
312 * Offset codes 0 - 0x13 Invalid.
313 * Offset codes 0x14 0x17 give 10mV steps
314 * Offset codes 0x17 through 0x9D give 5mV steps
315 * So let us start with our operating range from .73V
316 */
317 .start_code = 0x17,
318 .i2c_slave_addr = 0x60,
319 .pmic_bus_init = gpi2c_init,
320 .pmic_write = palmas_i2c_write_u8,
321 };
322
323 /* The LP8732 and LP8733 are software-compatible, use common struct */
324 struct pmic_data lp8733 = {
325 .base_offset = LP873X_BUCK_BASE_VOLT_UV,
326 .step = 5000, /* 5 mV represented in uV */
327 /*
328 * Offset codes 0 - 0x13 Invalid.
329 * Offset codes 0x14 0x17 give 10mV steps
330 * Offset codes 0x17 through 0x9D give 5mV steps
331 * So let us start with our operating range from .73V
332 */
333 .start_code = 0x17,
334 .i2c_slave_addr = 0x60,
335 .pmic_bus_init = gpi2c_init,
336 .pmic_write = palmas_i2c_write_u8,
337 };
338
339 struct vcores_data omap5430_volts = {
340 .mpu.value[OPP_NOM] = VDD_MPU,
341 .mpu.addr = SMPS_REG_ADDR_12_MPU,
342 .mpu.pmic = &palmas,
343
344 .core.value[OPP_NOM] = VDD_CORE,
345 .core.addr = SMPS_REG_ADDR_8_CORE,
346 .core.pmic = &palmas,
347
348 .mm.value[OPP_NOM] = VDD_MM,
349 .mm.addr = SMPS_REG_ADDR_45_IVA,
350 .mm.pmic = &palmas,
351 };
352
353 struct vcores_data omap5430_volts_es2 = {
354 .mpu.value[OPP_NOM] = VDD_MPU_ES2,
355 .mpu.addr = SMPS_REG_ADDR_12_MPU,
356 .mpu.pmic = &palmas,
357 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
358
359 .core.value[OPP_NOM] = VDD_CORE_ES2,
360 .core.addr = SMPS_REG_ADDR_8_CORE,
361 .core.pmic = &palmas,
362
363 .mm.value[OPP_NOM] = VDD_MM_ES2,
364 .mm.addr = SMPS_REG_ADDR_45_IVA,
365 .mm.pmic = &palmas,
366 .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
367
368 .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN,
369 .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
370
371 .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN,
372 .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
373
374 .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN,
375 .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
376 };
377
378 /*
379 * Enable IPU1 clock domains, modules and
380 * do some additional special settings needed
381 */
enable_ipu1_clocks(void)382 void enable_ipu1_clocks(void)
383 {
384 if (!IS_ENABLED(CONFIG_DRA7XX) ||
385 !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
386 return;
387
388 u32 const clk_domains[] = {
389 (*prcm)->cm_ipu_clkstctrl,
390 (*prcm)->cm_ipu1_clkstctrl,
391 0
392 };
393
394 u32 const clk_modules_hw_auto_essential[] = {
395 (*prcm)->cm_ipu1_ipu1_clkctrl,
396 0
397 };
398
399 u32 const clk_modules_explicit_en_essential[] = {
400 (*prcm)->cm_l4per_gptimer11_clkctrl,
401 (*prcm)->cm1_abe_timer7_clkctrl,
402 (*prcm)->cm1_abe_timer8_clkctrl,
403 0
404 };
405 do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
406 clk_modules_explicit_en_essential, 0);
407
408 /* Enable optional additional functional clock for IPU1 */
409 setbits_le32((*prcm)->cm_ipu1_ipu1_clkctrl,
410 IPU1_CLKCTRL_CLKSEL_MASK);
411 /* Enable optional additional functional clock for IPU1 */
412 setbits_le32((*prcm)->cm1_abe_timer7_clkctrl,
413 IPU1_CLKCTRL_CLKSEL_MASK);
414 /* Enable optional additional functional clock for IPU1 */
415 setbits_le32((*prcm)->cm1_abe_timer8_clkctrl,
416 IPU1_CLKCTRL_CLKSEL_MASK);
417 }
418
419 /*
420 * Enable IPU2 clock domains, modules and
421 * do some additional special settings needed
422 */
enable_ipu2_clocks(void)423 void enable_ipu2_clocks(void)
424 {
425 if (!IS_ENABLED(CONFIG_DRA7XX) ||
426 !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
427 return;
428
429 u32 const clk_domains[] = {
430 (*prcm)->cm_ipu_clkstctrl,
431 (*prcm)->cm_ipu2_clkstctrl,
432 0
433 };
434
435 u32 const clk_modules_hw_auto_essential[] = {
436 (*prcm)->cm_ipu2_ipu2_clkctrl,
437 0
438 };
439
440 u32 const clk_modules_explicit_en_essential[] = {
441 (*prcm)->cm_l4per_gptimer3_clkctrl,
442 (*prcm)->cm_l4per_gptimer4_clkctrl,
443 (*prcm)->cm_l4per_gptimer9_clkctrl,
444 0
445 };
446 do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
447 clk_modules_explicit_en_essential, 0);
448
449 /* Enable optional additional functional clock for IPU2 */
450 setbits_le32((*prcm)->cm_l4per_gptimer4_clkctrl,
451 IPU1_CLKCTRL_CLKSEL_MASK);
452 /* Enable optional additional functional clock for IPU2 */
453 setbits_le32((*prcm)->cm_l4per_gptimer9_clkctrl,
454 IPU1_CLKCTRL_CLKSEL_MASK);
455 }
456
457 /*
458 * Enable essential clock domains, modules and
459 * do some additional special settings needed
460 */
enable_basic_clocks(void)461 void enable_basic_clocks(void)
462 {
463 u32 const clk_domains_essential[] = {
464 (*prcm)->cm_l4per_clkstctrl,
465 (*prcm)->cm_l3init_clkstctrl,
466 (*prcm)->cm_memif_clkstctrl,
467 (*prcm)->cm_l4cfg_clkstctrl,
468 #ifdef CONFIG_DRIVER_TI_CPSW
469 (*prcm)->cm_gmac_clkstctrl,
470 #endif
471 0
472 };
473
474 u32 const clk_modules_hw_auto_essential[] = {
475 (*prcm)->cm_l3_gpmc_clkctrl,
476 (*prcm)->cm_memif_emif_1_clkctrl,
477 (*prcm)->cm_memif_emif_2_clkctrl,
478 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
479 (*prcm)->cm_wkup_gpio1_clkctrl,
480 (*prcm)->cm_l4per_gpio2_clkctrl,
481 (*prcm)->cm_l4per_gpio3_clkctrl,
482 (*prcm)->cm_l4per_gpio4_clkctrl,
483 (*prcm)->cm_l4per_gpio5_clkctrl,
484 (*prcm)->cm_l4per_gpio6_clkctrl,
485 (*prcm)->cm_l4per_gpio7_clkctrl,
486 (*prcm)->cm_l4per_gpio8_clkctrl,
487 0
488 };
489
490 u32 const clk_modules_explicit_en_essential[] = {
491 (*prcm)->cm_wkup_gptimer1_clkctrl,
492 (*prcm)->cm_l3init_hsmmc1_clkctrl,
493 (*prcm)->cm_l3init_hsmmc2_clkctrl,
494 (*prcm)->cm_l4per_gptimer2_clkctrl,
495 (*prcm)->cm_wkup_wdtimer2_clkctrl,
496 (*prcm)->cm_l4per_uart1_clkctrl,
497 (*prcm)->cm_l4per_uart3_clkctrl,
498 (*prcm)->cm_l4per_i2c1_clkctrl,
499 #ifdef CONFIG_DRIVER_TI_CPSW
500 (*prcm)->cm_gmac_gmac_clkctrl,
501 #endif
502
503 #ifdef CONFIG_TI_QSPI
504 (*prcm)->cm_l4per_qspi_clkctrl,
505 #endif
506 0
507 };
508
509 /* Enable optional additional functional clock for GPIO4 */
510 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
511 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
512
513 /* Enable 192 MHz clock for MMC1 & MMC2 */
514 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
515 HSMMC_CLKCTRL_CLKSEL_MASK);
516 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
517 HSMMC_CLKCTRL_CLKSEL_MASK);
518
519 /* Set the correct clock dividers for mmc */
520 clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
521 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
522 clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
523 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
524
525 /* Select 32KHz clock as the source of GPTIMER1 */
526 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
527 GPTIMER1_CLKCTRL_CLKSEL_MASK);
528
529 do_enable_clocks(clk_domains_essential,
530 clk_modules_hw_auto_essential,
531 clk_modules_explicit_en_essential,
532 1);
533
534 #ifdef CONFIG_TI_QSPI
535 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
536 #endif
537
538 /* Enable SCRM OPT clocks for PER and CORE dpll */
539 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
540 OPTFCLKEN_SCRM_PER_MASK);
541 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
542 OPTFCLKEN_SCRM_CORE_MASK);
543 }
544
enable_basic_uboot_clocks(void)545 void enable_basic_uboot_clocks(void)
546 {
547 u32 cm_ipu_clkstctrl = 0;
548
549 if (IS_ENABLED(CONFIG_DRA7XX) &&
550 !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
551 cm_ipu_clkstctrl = (*prcm)->cm_ipu_clkstctrl;
552
553 u32 const clk_domains_essential[] = {cm_ipu_clkstctrl, 0};
554
555 u32 const clk_modules_hw_auto_essential[] = {
556 (*prcm)->cm_l3init_hsusbtll_clkctrl,
557 0
558 };
559
560 u32 const clk_modules_explicit_en_essential[] = {
561 (*prcm)->cm_l4per_mcspi1_clkctrl,
562 (*prcm)->cm_l4per_i2c2_clkctrl,
563 (*prcm)->cm_l4per_i2c3_clkctrl,
564 (*prcm)->cm_l4per_i2c4_clkctrl,
565 #if defined(CONFIG_DRA7XX)
566 (*prcm)->cm_ipu_i2c5_clkctrl,
567 #else
568 (*prcm)->cm_l4per_i2c5_clkctrl,
569 #endif
570 (*prcm)->cm_l3init_hsusbhost_clkctrl,
571 (*prcm)->cm_l3init_fsusb_clkctrl,
572 0
573 };
574 do_enable_clocks(clk_domains_essential,
575 clk_modules_hw_auto_essential,
576 clk_modules_explicit_en_essential,
577 1);
578 }
579
580 #ifdef CONFIG_TI_EDMA3
enable_edma3_clocks(void)581 void enable_edma3_clocks(void)
582 {
583 u32 const clk_domains_edma3[] = {
584 0
585 };
586
587 u32 const clk_modules_hw_auto_edma3[] = {
588 (*prcm)->cm_l3main1_tptc1_clkctrl,
589 (*prcm)->cm_l3main1_tptc2_clkctrl,
590 0
591 };
592
593 u32 const clk_modules_explicit_en_edma3[] = {
594 0
595 };
596
597 do_enable_clocks(clk_domains_edma3,
598 clk_modules_hw_auto_edma3,
599 clk_modules_explicit_en_edma3,
600 1);
601 }
602
disable_edma3_clocks(void)603 void disable_edma3_clocks(void)
604 {
605 u32 const clk_domains_edma3[] = {
606 0
607 };
608
609 u32 const clk_modules_disable_edma3[] = {
610 (*prcm)->cm_l3main1_tptc1_clkctrl,
611 (*prcm)->cm_l3main1_tptc2_clkctrl,
612 0
613 };
614
615 do_disable_clocks(clk_domains_edma3,
616 clk_modules_disable_edma3,
617 1);
618 }
619 #endif
620
621 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
enable_usb_clocks(int index)622 void enable_usb_clocks(int index)
623 {
624 u32 cm_l3init_usb_otg_ss_clkctrl = 0;
625
626 if (index == 0) {
627 cm_l3init_usb_otg_ss_clkctrl =
628 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
629 /* Enable 960 MHz clock for dwc3 */
630 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
631 OPTFCLKEN_REFCLK960M);
632
633 /* Enable 32 KHz clock for USB_PHY1 */
634 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
635 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
636
637 /* Enable 32 KHz clock for USB_PHY3 */
638 if (is_dra7xx())
639 setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
640 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
641 } else if (index == 1) {
642 cm_l3init_usb_otg_ss_clkctrl =
643 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
644 /* Enable 960 MHz clock for dwc3 */
645 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
646 OPTFCLKEN_REFCLK960M);
647
648 /* Enable 32 KHz clock for dwc3 */
649 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
650 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
651
652 /* Enable 60 MHz clock for USB2PHY2 */
653 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
654 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
655 }
656
657 u32 const clk_domains_usb[] = {
658 0
659 };
660
661 u32 const clk_modules_hw_auto_usb[] = {
662 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
663 cm_l3init_usb_otg_ss_clkctrl,
664 0
665 };
666
667 u32 const clk_modules_explicit_en_usb[] = {
668 0
669 };
670
671 do_enable_clocks(clk_domains_usb,
672 clk_modules_hw_auto_usb,
673 clk_modules_explicit_en_usb,
674 1);
675 }
676
disable_usb_clocks(int index)677 void disable_usb_clocks(int index)
678 {
679 u32 cm_l3init_usb_otg_ss_clkctrl = 0;
680
681 if (index == 0) {
682 cm_l3init_usb_otg_ss_clkctrl =
683 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
684 /* Disable 960 MHz clock for dwc3 */
685 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
686 OPTFCLKEN_REFCLK960M);
687
688 /* Disable 32 KHz clock for USB_PHY1 */
689 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
690 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
691
692 /* Disable 32 KHz clock for USB_PHY3 */
693 if (is_dra7xx())
694 clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
695 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
696 } else if (index == 1) {
697 cm_l3init_usb_otg_ss_clkctrl =
698 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
699 /* Disable 960 MHz clock for dwc3 */
700 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
701 OPTFCLKEN_REFCLK960M);
702
703 /* Disable 32 KHz clock for dwc3 */
704 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
705 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
706
707 /* Disable 60 MHz clock for USB2PHY2 */
708 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
709 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
710 }
711
712 u32 const clk_domains_usb[] = {
713 0
714 };
715
716 u32 const clk_modules_disable[] = {
717 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
718 cm_l3init_usb_otg_ss_clkctrl,
719 0
720 };
721
722 do_disable_clocks(clk_domains_usb,
723 clk_modules_disable,
724 1);
725 }
726 #endif
727
728 const struct ctrl_ioregs ioregs_omap5430 = {
729 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
730 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
731 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
732 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
733 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
734 };
735
736 const struct ctrl_ioregs ioregs_omap5432_es1 = {
737 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
738 .ctrl_lpddr2ch = 0x0,
739 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
740 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
741 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
742 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
743 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
744 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
745 };
746
747 const struct ctrl_ioregs ioregs_omap5432_es2 = {
748 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
749 .ctrl_lpddr2ch = 0x0,
750 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
751 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
752 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
753 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
754 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
755 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
756 };
757
758 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
759 .ctrl_ddrch = 0x40404040,
760 .ctrl_lpddr2ch = 0x40404040,
761 .ctrl_ddr3ch = 0x80808080,
762 .ctrl_ddrio_0 = 0x00094A40,
763 .ctrl_ddrio_1 = 0x04A52000,
764 .ctrl_ddrio_2 = 0x84210000,
765 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
766 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
767 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
768 };
769
770 const struct ctrl_ioregs ioregs_dra72x_es1 = {
771 .ctrl_ddrch = 0x40404040,
772 .ctrl_lpddr2ch = 0x40404040,
773 .ctrl_ddr3ch = 0x60606080,
774 .ctrl_ddrio_0 = 0x00094A40,
775 .ctrl_ddrio_1 = 0x04A52000,
776 .ctrl_ddrio_2 = 0x84210000,
777 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
778 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
779 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
780 };
781
782 const struct ctrl_ioregs ioregs_dra72x_es2 = {
783 .ctrl_ddrch = 0x40404040,
784 .ctrl_lpddr2ch = 0x40404040,
785 .ctrl_ddr3ch = 0x60606060,
786 .ctrl_ddrio_0 = 0x00094A40,
787 .ctrl_ddrio_1 = 0x00000000,
788 .ctrl_ddrio_2 = 0x00000000,
789 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
790 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
791 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
792 };
793
hw_data_init(void)794 void __weak hw_data_init(void)
795 {
796 u32 omap_rev = omap_revision();
797
798 switch (omap_rev) {
799
800 case OMAP5430_ES1_0:
801 case OMAP5432_ES1_0:
802 *prcm = &omap5_es1_prcm;
803 *dplls_data = &omap5_dplls_es1;
804 *omap_vcores = &omap5430_volts;
805 *ctrl = &omap5_ctrl;
806 break;
807
808 case OMAP5430_ES2_0:
809 case OMAP5432_ES2_0:
810 *prcm = &omap5_es2_prcm;
811 *dplls_data = &omap5_dplls_es2;
812 *omap_vcores = &omap5430_volts_es2;
813 *ctrl = &omap5_ctrl;
814 break;
815
816 case DRA762_ABZ_ES1_0:
817 case DRA762_ACD_ES1_0:
818 case DRA762_ES1_0:
819 *prcm = &dra7xx_prcm;
820 *dplls_data = &dra76x_dplls;
821 *ctrl = &dra7xx_ctrl;
822 break;
823
824 case DRA752_ES1_0:
825 case DRA752_ES1_1:
826 case DRA752_ES2_0:
827 *prcm = &dra7xx_prcm;
828 *dplls_data = &dra7xx_dplls;
829 *ctrl = &dra7xx_ctrl;
830 break;
831
832 case DRA722_ES1_0:
833 case DRA722_ES2_0:
834 case DRA722_ES2_1:
835 *prcm = &dra7xx_prcm;
836 *dplls_data = &dra72x_dplls;
837 *ctrl = &dra7xx_ctrl;
838 break;
839
840 default:
841 printf("\n INVALID OMAP REVISION ");
842 }
843 }
844
get_ioregs(const struct ctrl_ioregs ** regs)845 void get_ioregs(const struct ctrl_ioregs **regs)
846 {
847 u32 omap_rev = omap_revision();
848
849 switch (omap_rev) {
850 case OMAP5430_ES1_0:
851 case OMAP5430_ES2_0:
852 *regs = &ioregs_omap5430;
853 break;
854 case OMAP5432_ES1_0:
855 *regs = &ioregs_omap5432_es1;
856 break;
857 case OMAP5432_ES2_0:
858 *regs = &ioregs_omap5432_es2;
859 break;
860 case DRA752_ES1_0:
861 case DRA752_ES1_1:
862 case DRA752_ES2_0:
863 case DRA762_ES1_0:
864 case DRA762_ACD_ES1_0:
865 case DRA762_ABZ_ES1_0:
866 *regs = &ioregs_dra7xx_es1;
867 break;
868 case DRA722_ES1_0:
869 *regs = &ioregs_dra72x_es1;
870 break;
871 case DRA722_ES2_0:
872 case DRA722_ES2_1:
873 *regs = &ioregs_dra72x_es2;
874 break;
875
876 default:
877 printf("\n INVALID OMAP REVISION ");
878 }
879 }
880