1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
7 #define _TEGRA_XUSB_PADCTL_COMMON_H_
8
9 #include <fdtdec.h>
10 #include <dm/ofnode.h>
11
12 #include <asm/io.h>
13 #include <asm/arch-tegra/xusb-padctl.h>
14 #include <linux/ioport.h>
15
16 struct tegra_xusb_padctl_lane {
17 const char *name;
18
19 unsigned int offset;
20 unsigned int shift;
21 unsigned int mask;
22 unsigned int iddq;
23
24 const unsigned int *funcs;
25 unsigned int num_funcs;
26 };
27
28 struct tegra_xusb_phy_ops {
29 int (*prepare)(struct tegra_xusb_phy *phy);
30 int (*enable)(struct tegra_xusb_phy *phy);
31 int (*disable)(struct tegra_xusb_phy *phy);
32 int (*unprepare)(struct tegra_xusb_phy *phy);
33 };
34
35 struct tegra_xusb_phy {
36 unsigned int type;
37 const struct tegra_xusb_phy_ops *ops;
38 struct tegra_xusb_padctl *padctl;
39 };
40
41 struct tegra_xusb_padctl_pin {
42 const struct tegra_xusb_padctl_lane *lane;
43
44 unsigned int func;
45 int iddq;
46 };
47
48 #define MAX_GROUPS 5
49 #define MAX_PINS 7
50
51 struct tegra_xusb_padctl_group {
52 const char *name;
53
54 const char *pins[MAX_PINS];
55 unsigned int num_pins;
56
57 const char *func;
58 int iddq;
59 };
60
61 struct tegra_xusb_padctl_soc {
62 const struct tegra_xusb_padctl_lane *lanes;
63 unsigned int num_lanes;
64 const char *const *functions;
65 unsigned int num_functions;
66 struct tegra_xusb_phy *phys;
67 unsigned int num_phys;
68 };
69
70 struct tegra_xusb_padctl_config {
71 const char *name;
72
73 struct tegra_xusb_padctl_group groups[MAX_GROUPS];
74 unsigned int num_groups;
75 };
76
77 struct tegra_xusb_padctl {
78 const struct tegra_xusb_padctl_soc *socdata;
79 struct tegra_xusb_padctl_config config;
80 struct resource regs;
81 unsigned int enable;
82
83 };
84 extern struct tegra_xusb_padctl padctl;
85
padctl_readl(struct tegra_xusb_padctl * padctl,unsigned long offset)86 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
87 unsigned long offset)
88 {
89 return readl(padctl->regs.start + offset);
90 }
91
padctl_writel(struct tegra_xusb_padctl * padctl,u32 value,unsigned long offset)92 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
93 u32 value, unsigned long offset)
94 {
95 writel(value, padctl->regs.start + offset);
96 }
97
98 int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
99 const struct tegra_xusb_padctl_soc *socdata);
100
101 #endif
102