1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <config.h>
7 #include <errno.h>
8 #include <imx_container.h>
9 #include <log.h>
10 #include <malloc.h>
11 #include <asm/io.h>
12 #include <mmc.h>
13 #include <spi_flash.h>
14 #include <spl.h>
15 #include <nand.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/boot_mode.h>
18
19 #define MMC_DEV 0
20 #define QSPI_DEV 1
21 #define NAND_DEV 2
22 #define QSPI_NOR_DEV 3
23 #define ROM_API_DEV 4
24
25 /* The unit of second image offset number which provision by the fuse bits */
26 #define SND_IMG_OFF_UNIT (0x100000UL)
27
28 /*
29 * If num = 0, off = (2 ^ 2) * 1MB
30 * else If num = 2, off = (2 ^ 0) * 1MB
31 * else off = (2 ^ num) * 1MB
32 */
33 #define SND_IMG_NUM_TO_OFF(num) \
34 ((1UL << ((0 == (num)) ? 2 : (2 == (num)) ? 0 : (num))) * SND_IMG_OFF_UNIT)
35
36 #define GET_SND_IMG_NUM(fuse) (((fuse) >> 24) & 0x1F)
37
38 #if defined(CONFIG_IMX8QM)
39 #define FUSE_IMG_SET_OFF_WORD 464
40 #elif defined(CONFIG_IMX8QXP)
41 #define FUSE_IMG_SET_OFF_WORD 720
42 #endif
43
44 #define MAX_V2X_CTNR_IMG_NUM (4)
45 #define MIN_V2X_CTNR_IMG_NUM (2)
46
47 #define IMG_FLAGS_IMG_TYPE_SHIFT (0u)
48 #define IMG_FLAGS_IMG_TYPE_MASK (0xfU)
49 #define IMG_FLAGS_IMG_TYPE(x) (((x) & IMG_FLAGS_IMG_TYPE_MASK) >> \
50 IMG_FLAGS_IMG_TYPE_SHIFT)
51
52 #define IMG_FLAGS_CORE_ID_SHIFT (4u)
53 #define IMG_FLAGS_CORE_ID_MASK (0xf0U)
54 #define IMG_FLAGS_CORE_ID(x) (((x) & IMG_FLAGS_CORE_ID_MASK) >> \
55 IMG_FLAGS_CORE_ID_SHIFT)
56
57 #define IMG_TYPE_V2X_PRI_FW (0x0Bu) /* Primary V2X FW */
58 #define IMG_TYPE_V2X_SND_FW (0x0Cu) /* Secondary V2X FW */
59
60 #define CORE_V2X_PRI 9
61 #define CORE_V2X_SND 10
62
is_v2x_fw_container(ulong addr)63 static bool is_v2x_fw_container(ulong addr)
64 {
65 struct container_hdr *phdr;
66 struct boot_img_t *img_entry;
67
68 phdr = (struct container_hdr *)addr;
69 if ((phdr->tag != 0x87 && phdr->tag != 0x82) || phdr->version != 0x0) {
70 debug("Wrong container header\n");
71 return false;
72 }
73
74 if (phdr->num_images >= MIN_V2X_CTNR_IMG_NUM && phdr->num_images <= MAX_V2X_CTNR_IMG_NUM) {
75 img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr));
76
77 if (IMG_FLAGS_IMG_TYPE(img_entry->hab_flags) == IMG_TYPE_V2X_PRI_FW &&
78 IMG_FLAGS_CORE_ID(img_entry->hab_flags) == CORE_V2X_PRI) {
79 img_entry++;
80
81 if (IMG_FLAGS_IMG_TYPE(img_entry->hab_flags) == IMG_TYPE_V2X_SND_FW &&
82 IMG_FLAGS_CORE_ID(img_entry->hab_flags) == CORE_V2X_SND)
83 return true;
84 }
85 }
86
87 return false;
88 }
89
get_container_size(ulong addr,u16 * header_length)90 int get_container_size(ulong addr, u16 *header_length)
91 {
92 struct container_hdr *phdr;
93 struct boot_img_t *img_entry;
94 struct signature_block_hdr *sign_hdr;
95 u8 i = 0;
96 u32 max_offset = 0, img_end;
97
98 phdr = (struct container_hdr *)addr;
99 if (!valid_container_hdr(phdr)) {
100 debug("Wrong container header\n");
101 return -EFAULT;
102 }
103
104 max_offset = phdr->length_lsb + (phdr->length_msb << 8);
105 if (header_length)
106 *header_length = max_offset;
107
108 img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr));
109 for (i = 0; i < phdr->num_images; i++) {
110 img_end = img_entry->offset + img_entry->size;
111 if (img_end > max_offset)
112 max_offset = img_end;
113
114 debug("img[%u], end = 0x%x\n", i, img_end);
115
116 img_entry++;
117 }
118
119 if (phdr->sig_blk_offset != 0) {
120 sign_hdr = (struct signature_block_hdr *)(addr + phdr->sig_blk_offset);
121 u16 len = sign_hdr->length_lsb + (sign_hdr->length_msb << 8);
122
123 if (phdr->sig_blk_offset + len > max_offset)
124 max_offset = phdr->sig_blk_offset + len;
125
126 debug("sigblk, end = 0x%x\n", phdr->sig_blk_offset + len);
127 }
128
129 return max_offset;
130 }
131
get_dev_container_size(void * dev,int dev_type,unsigned long offset,u16 * header_length,bool * v2x_cntr)132 static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length, bool *v2x_cntr)
133 {
134 u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT);
135 int ret = 0;
136
137 if (!buf) {
138 printf("Malloc buffer failed\n");
139 return -ENOMEM;
140 }
141
142 #ifdef CONFIG_SPL_MMC
143 if (dev_type == MMC_DEV) {
144 unsigned long count = 0;
145 struct mmc *mmc = (struct mmc *)dev;
146
147 count = blk_dread(mmc_get_blk_desc(mmc),
148 offset / mmc->read_bl_len,
149 CONTAINER_HDR_ALIGNMENT / mmc->read_bl_len,
150 buf);
151 if (count == 0) {
152 printf("Read container image from MMC/SD failed\n");
153 return -EIO;
154 }
155 }
156 #endif
157
158 #ifdef CONFIG_SPL_SPI_LOAD
159 if (dev_type == QSPI_DEV) {
160 struct spi_flash *flash = (struct spi_flash *)dev;
161
162 ret = spi_flash_read(flash, offset,
163 CONTAINER_HDR_ALIGNMENT, buf);
164 if (ret != 0) {
165 printf("Read container image from QSPI failed\n");
166 return -EIO;
167 }
168 }
169 #endif
170
171 #ifdef CONFIG_SPL_NAND_SUPPORT
172 if (dev_type == NAND_DEV) {
173 ret = nand_spl_load_image(offset, CONTAINER_HDR_ALIGNMENT,
174 buf);
175 if (ret != 0) {
176 printf("Read container image from NAND failed\n");
177 return -EIO;
178 }
179 }
180 #endif
181
182 #ifdef CONFIG_SPL_NOR_SUPPORT
183 if (dev_type == QSPI_NOR_DEV)
184 memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT);
185 #endif
186
187 #ifdef CONFIG_SPL_BOOTROM_SUPPORT
188 if (dev_type == ROM_API_DEV) {
189 ret = spl_romapi_raw_seekable_read(offset, CONTAINER_HDR_ALIGNMENT, buf);
190 if (!ret) {
191 printf("Read container image from ROM API failed\n");
192 return -EIO;
193 }
194 }
195 #endif
196
197 ret = get_container_size((ulong)buf, header_length);
198
199 if (v2x_cntr)
200 *v2x_cntr = is_v2x_fw_container((ulong)buf);
201
202 free(buf);
203
204 return ret;
205 }
206
check_secondary_cnt_set(unsigned long * set_off)207 static bool check_secondary_cnt_set(unsigned long *set_off)
208 {
209 #if IS_ENABLED(CONFIG_ARCH_IMX8)
210 int ret;
211 u8 set_id = 1;
212 u32 fuse_val = 0;
213
214 if (!(is_imx8qxp() && is_soc_rev(CHIP_REV_B))) {
215 ret = sc_misc_get_boot_container(-1, &set_id);
216 if (ret)
217 return false;
218 /* Secondary boot */
219 if (set_id == 2) {
220 ret = sc_misc_otp_fuse_read(-1, FUSE_IMG_SET_OFF_WORD, &fuse_val);
221 if (!ret) {
222 if (set_off)
223 *set_off = SND_IMG_NUM_TO_OFF(GET_SND_IMG_NUM(fuse_val));
224 return true;
225 }
226 }
227 }
228 #endif
229
230 return false;
231 }
232
get_boot_device_offset(void * dev,int dev_type)233 static unsigned long get_boot_device_offset(void *dev, int dev_type)
234 {
235 unsigned long offset = 0, sec_set_off = 0;
236 bool sec_boot = false;
237
238 if (dev_type == ROM_API_DEV) {
239 offset = (unsigned long)dev;
240 return offset;
241 }
242
243 sec_boot = check_secondary_cnt_set(&sec_set_off);
244 if (sec_boot)
245 printf("Secondary set selected\n");
246 else
247 printf("Primary set selected\n");
248
249 if (dev_type == MMC_DEV) {
250 struct mmc *mmc = (struct mmc *)dev;
251
252 if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
253 offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
254 } else {
255 u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
256
257 if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) {
258 if (is_imx8qxp() && is_soc_rev(CHIP_REV_B))
259 offset = CONTAINER_HDR_MMCSD_OFFSET;
260 else
261 offset = CONTAINER_HDR_EMMC_OFFSET;
262 } else {
263 offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
264 }
265 }
266 } else if (dev_type == QSPI_DEV) {
267 offset = sec_boot ? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) :
268 CONTAINER_HDR_QSPI_OFFSET;
269 } else if (dev_type == NAND_DEV) {
270 offset = sec_boot ? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) :
271 CONTAINER_HDR_NAND_OFFSET;
272 } else if (dev_type == QSPI_NOR_DEV) {
273 offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
274 } else {
275 printf("Not supported dev_type: %d\n", dev_type);
276 }
277
278 debug("container set offset 0x%lx\n", offset);
279
280 return offset;
281 }
282
get_imageset_end(void * dev,int dev_type)283 static ulong get_imageset_end(void *dev, int dev_type)
284 {
285 unsigned long offset[3] = {};
286 int value_container[3] = {};
287 u16 hdr_length;
288 bool v2x_fw = false;
289
290 offset[0] = get_boot_device_offset(dev, dev_type);
291
292 value_container[0] = get_dev_container_size(dev, dev_type, offset[0], &hdr_length, NULL);
293 if (value_container[0] < 0) {
294 printf("Parse seco container failed %d\n", value_container[0]);
295 return 0;
296 }
297
298 debug("seco container size 0x%x\n", value_container[0]);
299
300 if (is_imx95()) {
301 offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
302
303 value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw);
304 if (value_container[1] < 0) {
305 printf("Parse v2x container failed %d\n", value_container[1]);
306 return value_container[0] + offset[0]; /* return seco container total size */
307 }
308
309 if (v2x_fw) {
310 debug("v2x container size 0x%x\n", value_container[1]);
311 offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[1];
312 } else {
313 printf("no v2x container included\n");
314 offset[2] = offset[1];
315 }
316 } else {
317 /* Skip offset[1] */
318 offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
319 }
320
321 value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL);
322 if (value_container[2] < 0) {
323 debug("Parse scu container image failed %d, only seco container\n", value_container[2]);
324 if (is_imx95())
325 return value_container[1] + offset[1]; /* return seco + v2x container total size */
326 else
327 return value_container[0] + offset[0]; /* return seco container total size */
328 }
329
330 debug("scu container size 0x%x\n", value_container[2]);
331
332 return value_container[2] + offset[2];
333 }
334
335 #ifdef CONFIG_SPL_SPI_LOAD
spl_spi_get_uboot_offs(struct spi_flash * flash)336 unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
337 {
338 ulong end;
339
340 end = get_imageset_end(flash, QSPI_DEV);
341 end = ROUND(end, SZ_1K);
342
343 printf("Load image from QSPI 0x%lx\n", end);
344
345 return end;
346 }
347 #endif
348
349 #ifdef CONFIG_SPL_MMC
arch_spl_mmc_get_uboot_raw_sector(struct mmc * mmc,unsigned long raw_sect)350 unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
351 unsigned long raw_sect)
352 {
353 ulong end;
354
355 end = get_imageset_end(mmc, MMC_DEV);
356 end = ROUND(end, SZ_1K);
357
358 printf("Load image from MMC/SD 0x%lx\n", end);
359
360 return end / mmc->read_bl_len;
361 }
362
spl_mmc_emmc_boot_partition(struct mmc * mmc)363 int spl_mmc_emmc_boot_partition(struct mmc *mmc)
364 {
365 int part;
366
367 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
368 if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) {
369 unsigned long sec_set_off = 0;
370 bool sec_boot = false;
371
372 sec_boot = check_secondary_cnt_set(&sec_set_off);
373 if (sec_boot)
374 part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1;
375 } else if (part == EMMC_BOOT_PART_USER) {
376 part = EMMC_HWPART_DEFAULT;
377 }
378
379 return part;
380 }
381 #endif
382
383 #ifdef CONFIG_SPL_NAND_SUPPORT
spl_nand_get_uboot_raw_page(void)384 uint32_t spl_nand_get_uboot_raw_page(void)
385 {
386 ulong end;
387
388 end = get_imageset_end((void *)NULL, NAND_DEV);
389 end = ROUND(end, SZ_16K);
390
391 printf("Load image from NAND 0x%lx\n", end);
392
393 return end;
394 }
395 #endif
396
397 #ifdef CONFIG_SPL_NOR_SUPPORT
spl_nor_get_uboot_base(void)398 unsigned long spl_nor_get_uboot_base(void)
399 {
400 ulong end;
401
402 /* Calculate the image set end,
403 * if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
404 * we use CFG_SYS_UBOOT_BASE
405 * Otherwise, use the calculated address
406 */
407 end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
408 if (end <= CFG_SYS_UBOOT_BASE)
409 end = CFG_SYS_UBOOT_BASE;
410 else
411 end = ROUND(end, SZ_1K);
412
413 printf("Load image from NOR 0x%lx\n", end);
414
415 return end;
416 }
417 #endif
418
419 #ifdef CONFIG_SPL_BOOTROM_SUPPORT
spl_arch_boot_image_offset(u32 image_offset,u32 rom_bt_dev)420 u32 __weak spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
421 {
422 return image_offset;
423 }
424
spl_romapi_get_uboot_base(u32 image_offset,u32 rom_bt_dev)425 ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
426 {
427 ulong end;
428
429 image_offset = spl_arch_boot_image_offset(image_offset, rom_bt_dev);
430
431 end = get_imageset_end((void *)(ulong)image_offset, ROM_API_DEV);
432 end = ROUND(end, SZ_1K);
433
434 printf("Load image from 0x%lx by ROM_API\n", end);
435
436 return end;
437 }
438 #endif
439