1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <malloc.h>
7 #include <net.h>
8 #include <vesa.h>
9 #include <acpi/acpi_s3.h>
10 #include <asm/coreboot_tables.h>
11 #include <asm/e820.h>
12 #include <asm/global_data.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
high_table_reserve(void)16 int high_table_reserve(void)
17 {
18 /* adjust stack pointer to reserve space for configuration tables */
19 gd->arch.high_table_limit = gd->start_addr_sp;
20 gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
21 gd->arch.high_table_ptr = gd->start_addr_sp;
22
23 /* clear the memory */
24 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
25 gd->arch.prev_sleep_state != ACPI_S3) {
26 memset((void *)gd->arch.high_table_ptr, 0,
27 CONFIG_HIGH_TABLE_SIZE);
28 }
29
30 gd->start_addr_sp &= ~0xf;
31
32 return 0;
33 }
34
high_table_malloc(size_t bytes)35 void *high_table_malloc(size_t bytes)
36 {
37 u32 new_ptr;
38 void *ptr;
39
40 new_ptr = gd->arch.high_table_ptr + bytes;
41 if (new_ptr >= gd->arch.high_table_limit)
42 return NULL;
43 ptr = (void *)gd->arch.high_table_ptr;
44 gd->arch.high_table_ptr = new_ptr;
45
46 return ptr;
47 }
48
49 /**
50 * cb_table_init() - initialize a coreboot table header
51 *
52 * This fills in the coreboot table header signature and the header bytes.
53 * Other fields are set to zero.
54 *
55 * @cbh: coreboot table header address
56 */
cb_table_init(struct cb_header * cbh)57 static void cb_table_init(struct cb_header *cbh)
58 {
59 memset(cbh, 0, sizeof(struct cb_header));
60 memcpy(cbh->signature, "LBIO", 4);
61 cbh->header_bytes = sizeof(struct cb_header);
62 }
63
64 /**
65 * cb_table_add_entry() - add a coreboot table entry
66 *
67 * This increases the coreboot table entry size with added table entry length
68 * and increases entry count by 1.
69 *
70 * @cbh: coreboot table header address
71 * @cbr: to be added table entry address
72 * @return: pointer to next table entry address
73 */
cb_table_add_entry(struct cb_header * cbh,struct cb_record * cbr)74 static u32 cb_table_add_entry(struct cb_header *cbh, struct cb_record *cbr)
75 {
76 cbh->table_bytes += cbr->size;
77 cbh->table_entries++;
78
79 return (u32)cbr + cbr->size;
80 }
81
82 /**
83 * cb_table_finalize() - finalize the coreboot table
84 *
85 * This calculates the checksum for all coreboot table entries as well as
86 * the checksum for the coreboot header itself.
87 *
88 * @cbh: coreboot table header address
89 */
cb_table_finalize(struct cb_header * cbh)90 static void cb_table_finalize(struct cb_header *cbh)
91 {
92 struct cb_record *cbr = (struct cb_record *)(cbh + 1);
93
94 cbh->table_checksum = compute_ip_checksum(cbr, cbh->table_bytes);
95 cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes);
96 }
97
write_coreboot_table(u32 addr,struct memory_area * cfg_tables)98 void write_coreboot_table(u32 addr, struct memory_area *cfg_tables)
99 {
100 struct cb_header *cbh = (struct cb_header *)addr;
101 struct cb_record *cbr;
102 struct cb_memory *mem;
103 struct cb_memory_range *map;
104 struct e820_entry e820[32];
105 struct cb_framebuffer *fb;
106 struct vesa_mode_info *vesa;
107 int i, num;
108
109 cb_table_init(cbh);
110 cbr = (struct cb_record *)(cbh + 1);
111
112 /*
113 * Two type of coreboot table entries are generated by us.
114 * They are 'struct cb_memory' and 'struct cb_framebuffer'.
115 */
116
117 /* populate memory map table */
118 mem = (struct cb_memory *)cbr;
119 mem->tag = CB_TAG_MEMORY;
120 map = mem->map;
121
122 /* first install e820 defined memory maps */
123 num = install_e820_map(ARRAY_SIZE(e820), e820);
124 for (i = 0; i < num; i++) {
125 map->start.lo = e820[i].addr & 0xffffffff;
126 map->start.hi = e820[i].addr >> 32;
127 map->size.lo = e820[i].size & 0xffffffff;
128 map->size.hi = e820[i].size >> 32;
129 map->type = e820[i].type;
130 map++;
131 }
132
133 /* then install all configuration tables */
134 while (cfg_tables->size) {
135 map->start.lo = cfg_tables->start & 0xffffffff;
136 map->start.hi = cfg_tables->start >> 32;
137 map->size.lo = cfg_tables->size & 0xffffffff;
138 map->size.hi = cfg_tables->size >> 32;
139 map->type = CB_MEM_TABLE;
140 map++;
141 num++;
142 cfg_tables++;
143 }
144 mem->size = num * sizeof(struct cb_memory_range) +
145 sizeof(struct cb_record);
146 cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
147
148 /* populate framebuffer table if we have sane vesa info */
149 vesa = &mode_info.vesa;
150 if (vesa->x_resolution && vesa->y_resolution) {
151 fb = (struct cb_framebuffer *)cbr;
152 fb->tag = CB_TAG_FRAMEBUFFER;
153 fb->size = sizeof(struct cb_framebuffer);
154
155 fb->x_resolution = vesa->x_resolution;
156 fb->y_resolution = vesa->y_resolution;
157 fb->bits_per_pixel = vesa->bits_per_pixel;
158 fb->bytes_per_line = vesa->bytes_per_scanline;
159 fb->physical_address = vesa->phys_base_ptr;
160 fb->red_mask_size = vesa->red_mask_size;
161 fb->red_mask_pos = vesa->red_mask_pos;
162 fb->green_mask_size = vesa->green_mask_size;
163 fb->green_mask_pos = vesa->green_mask_pos;
164 fb->blue_mask_size = vesa->blue_mask_size;
165 fb->blue_mask_pos = vesa->blue_mask_pos;
166 fb->reserved_mask_size = vesa->reserved_mask_size;
167 fb->reserved_mask_pos = vesa->reserved_mask_pos;
168
169 cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
170 }
171
172 cb_table_finalize(cbh);
173 }
174