1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2016 Google, Inc
4  */
5 
6 #include <bios_emul.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <log.h>
11 #include <pci_rom.h>
12 #include <vesa.h>
13 #include <video.h>
14 #include <asm/global_data.h>
15 #include <asm/intel_regs.h>
16 #include <asm/io.h>
17 #include <asm/mtrr.h>
18 #include <asm/pci.h>
19 #include <asm/arch/pch.h>
20 #include <asm/arch/sandybridge.h>
21 #include <linux/delay.h>
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 struct gt_powermeter {
26 	u16 reg;
27 	u32 value;
28 };
29 
30 /* These are magic values - unfortunately the meaning is unknown */
31 static const struct gt_powermeter snb_pm_gt1[] = {
32 	{ 0xa200, 0xcc000000 },
33 	{ 0xa204, 0x07000040 },
34 	{ 0xa208, 0x0000fe00 },
35 	{ 0xa20c, 0x00000000 },
36 	{ 0xa210, 0x17000000 },
37 	{ 0xa214, 0x00000021 },
38 	{ 0xa218, 0x0817fe19 },
39 	{ 0xa21c, 0x00000000 },
40 	{ 0xa220, 0x00000000 },
41 	{ 0xa224, 0xcc000000 },
42 	{ 0xa228, 0x07000040 },
43 	{ 0xa22c, 0x0000fe00 },
44 	{ 0xa230, 0x00000000 },
45 	{ 0xa234, 0x17000000 },
46 	{ 0xa238, 0x00000021 },
47 	{ 0xa23c, 0x0817fe19 },
48 	{ 0xa240, 0x00000000 },
49 	{ 0xa244, 0x00000000 },
50 	{ 0xa248, 0x8000421e },
51 	{ 0 }
52 };
53 
54 static const struct gt_powermeter snb_pm_gt2[] = {
55 	{ 0xa200, 0x330000a6 },
56 	{ 0xa204, 0x402d0031 },
57 	{ 0xa208, 0x00165f83 },
58 	{ 0xa20c, 0xf1000000 },
59 	{ 0xa210, 0x00000000 },
60 	{ 0xa214, 0x00160016 },
61 	{ 0xa218, 0x002a002b },
62 	{ 0xa21c, 0x00000000 },
63 	{ 0xa220, 0x00000000 },
64 	{ 0xa224, 0x330000a6 },
65 	{ 0xa228, 0x402d0031 },
66 	{ 0xa22c, 0x00165f83 },
67 	{ 0xa230, 0xf1000000 },
68 	{ 0xa234, 0x00000000 },
69 	{ 0xa238, 0x00160016 },
70 	{ 0xa23c, 0x002a002b },
71 	{ 0xa240, 0x00000000 },
72 	{ 0xa244, 0x00000000 },
73 	{ 0xa248, 0x8000421e },
74 	{ 0 }
75 };
76 
77 static const struct gt_powermeter ivb_pm_gt1[] = {
78 	{ 0xa800, 0x00000000 },
79 	{ 0xa804, 0x00021c00 },
80 	{ 0xa808, 0x00000403 },
81 	{ 0xa80c, 0x02001700 },
82 	{ 0xa810, 0x05000200 },
83 	{ 0xa814, 0x00000000 },
84 	{ 0xa818, 0x00690500 },
85 	{ 0xa81c, 0x0000007f },
86 	{ 0xa820, 0x01002501 },
87 	{ 0xa824, 0x00000300 },
88 	{ 0xa828, 0x01000331 },
89 	{ 0xa82c, 0x0000000c },
90 	{ 0xa830, 0x00010016 },
91 	{ 0xa834, 0x01100101 },
92 	{ 0xa838, 0x00010103 },
93 	{ 0xa83c, 0x00041300 },
94 	{ 0xa840, 0x00000b30 },
95 	{ 0xa844, 0x00000000 },
96 	{ 0xa848, 0x7f000000 },
97 	{ 0xa84c, 0x05000008 },
98 	{ 0xa850, 0x00000001 },
99 	{ 0xa854, 0x00000004 },
100 	{ 0xa858, 0x00000007 },
101 	{ 0xa85c, 0x00000000 },
102 	{ 0xa860, 0x00010000 },
103 	{ 0xa248, 0x0000221e },
104 	{ 0xa900, 0x00000000 },
105 	{ 0xa904, 0x00001c00 },
106 	{ 0xa908, 0x00000000 },
107 	{ 0xa90c, 0x06000000 },
108 	{ 0xa910, 0x09000200 },
109 	{ 0xa914, 0x00000000 },
110 	{ 0xa918, 0x00590000 },
111 	{ 0xa91c, 0x00000000 },
112 	{ 0xa920, 0x04002501 },
113 	{ 0xa924, 0x00000100 },
114 	{ 0xa928, 0x03000410 },
115 	{ 0xa92c, 0x00000000 },
116 	{ 0xa930, 0x00020000 },
117 	{ 0xa934, 0x02070106 },
118 	{ 0xa938, 0x00010100 },
119 	{ 0xa93c, 0x00401c00 },
120 	{ 0xa940, 0x00000000 },
121 	{ 0xa944, 0x00000000 },
122 	{ 0xa948, 0x10000e00 },
123 	{ 0xa94c, 0x02000004 },
124 	{ 0xa950, 0x00000001 },
125 	{ 0xa954, 0x00000004 },
126 	{ 0xa960, 0x00060000 },
127 	{ 0xaa3c, 0x00001c00 },
128 	{ 0xaa54, 0x00000004 },
129 	{ 0xaa60, 0x00060000 },
130 	{ 0 }
131 };
132 
133 static const struct gt_powermeter ivb_pm_gt2_17w[] = {
134 	{ 0xa800, 0x20000000 },
135 	{ 0xa804, 0x000e3800 },
136 	{ 0xa808, 0x00000806 },
137 	{ 0xa80c, 0x0c002f00 },
138 	{ 0xa810, 0x0c000800 },
139 	{ 0xa814, 0x00000000 },
140 	{ 0xa818, 0x00d20d00 },
141 	{ 0xa81c, 0x000000ff },
142 	{ 0xa820, 0x03004b02 },
143 	{ 0xa824, 0x00000600 },
144 	{ 0xa828, 0x07000773 },
145 	{ 0xa82c, 0x00000000 },
146 	{ 0xa830, 0x00020032 },
147 	{ 0xa834, 0x1520040d },
148 	{ 0xa838, 0x00020105 },
149 	{ 0xa83c, 0x00083700 },
150 	{ 0xa840, 0x000016ff },
151 	{ 0xa844, 0x00000000 },
152 	{ 0xa848, 0xff000000 },
153 	{ 0xa84c, 0x0a000010 },
154 	{ 0xa850, 0x00000002 },
155 	{ 0xa854, 0x00000008 },
156 	{ 0xa858, 0x0000000f },
157 	{ 0xa85c, 0x00000000 },
158 	{ 0xa860, 0x00020000 },
159 	{ 0xa248, 0x0000221e },
160 	{ 0xa900, 0x00000000 },
161 	{ 0xa904, 0x00003800 },
162 	{ 0xa908, 0x00000000 },
163 	{ 0xa90c, 0x0c000000 },
164 	{ 0xa910, 0x12000800 },
165 	{ 0xa914, 0x00000000 },
166 	{ 0xa918, 0x00b20000 },
167 	{ 0xa91c, 0x00000000 },
168 	{ 0xa920, 0x08004b02 },
169 	{ 0xa924, 0x00000300 },
170 	{ 0xa928, 0x01000820 },
171 	{ 0xa92c, 0x00000000 },
172 	{ 0xa930, 0x00030000 },
173 	{ 0xa934, 0x15150406 },
174 	{ 0xa938, 0x00020300 },
175 	{ 0xa93c, 0x00903900 },
176 	{ 0xa940, 0x00000000 },
177 	{ 0xa944, 0x00000000 },
178 	{ 0xa948, 0x20001b00 },
179 	{ 0xa94c, 0x0a000010 },
180 	{ 0xa950, 0x00000000 },
181 	{ 0xa954, 0x00000008 },
182 	{ 0xa960, 0x00110000 },
183 	{ 0xaa3c, 0x00003900 },
184 	{ 0xaa54, 0x00000008 },
185 	{ 0xaa60, 0x00110000 },
186 	{ 0 }
187 };
188 
189 static const struct gt_powermeter ivb_pm_gt2_35w[] = {
190 	{ 0xa800, 0x00000000 },
191 	{ 0xa804, 0x00030400 },
192 	{ 0xa808, 0x00000806 },
193 	{ 0xa80c, 0x0c002f00 },
194 	{ 0xa810, 0x0c000300 },
195 	{ 0xa814, 0x00000000 },
196 	{ 0xa818, 0x00d20d00 },
197 	{ 0xa81c, 0x000000ff },
198 	{ 0xa820, 0x03004b02 },
199 	{ 0xa824, 0x00000600 },
200 	{ 0xa828, 0x07000773 },
201 	{ 0xa82c, 0x00000000 },
202 	{ 0xa830, 0x00020032 },
203 	{ 0xa834, 0x1520040d },
204 	{ 0xa838, 0x00020105 },
205 	{ 0xa83c, 0x00083700 },
206 	{ 0xa840, 0x000016ff },
207 	{ 0xa844, 0x00000000 },
208 	{ 0xa848, 0xff000000 },
209 	{ 0xa84c, 0x0a000010 },
210 	{ 0xa850, 0x00000001 },
211 	{ 0xa854, 0x00000008 },
212 	{ 0xa858, 0x00000008 },
213 	{ 0xa85c, 0x00000000 },
214 	{ 0xa860, 0x00020000 },
215 	{ 0xa248, 0x0000221e },
216 	{ 0xa900, 0x00000000 },
217 	{ 0xa904, 0x00003800 },
218 	{ 0xa908, 0x00000000 },
219 	{ 0xa90c, 0x0c000000 },
220 	{ 0xa910, 0x12000800 },
221 	{ 0xa914, 0x00000000 },
222 	{ 0xa918, 0x00b20000 },
223 	{ 0xa91c, 0x00000000 },
224 	{ 0xa920, 0x08004b02 },
225 	{ 0xa924, 0x00000300 },
226 	{ 0xa928, 0x01000820 },
227 	{ 0xa92c, 0x00000000 },
228 	{ 0xa930, 0x00030000 },
229 	{ 0xa934, 0x15150406 },
230 	{ 0xa938, 0x00020300 },
231 	{ 0xa93c, 0x00903900 },
232 	{ 0xa940, 0x00000000 },
233 	{ 0xa944, 0x00000000 },
234 	{ 0xa948, 0x20001b00 },
235 	{ 0xa94c, 0x0a000010 },
236 	{ 0xa950, 0x00000000 },
237 	{ 0xa954, 0x00000008 },
238 	{ 0xa960, 0x00110000 },
239 	{ 0xaa3c, 0x00003900 },
240 	{ 0xaa54, 0x00000008 },
241 	{ 0xaa60, 0x00110000 },
242 	{ 0 }
243 };
244 
gtt_read(void * bar,u32 reg)245 static inline u32 gtt_read(void *bar, u32 reg)
246 {
247 	return readl(bar + reg);
248 }
249 
gtt_write(void * bar,u32 reg,u32 data)250 static inline void gtt_write(void *bar, u32 reg, u32 data)
251 {
252 	writel(data, bar + reg);
253 }
254 
gtt_write_powermeter(void * bar,const struct gt_powermeter * pm)255 static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
256 {
257 	for (; pm && pm->reg; pm++)
258 		gtt_write(bar, pm->reg, pm->value);
259 }
260 
261 #define GTT_RETRY 1000
gtt_poll(void * bar,u32 reg,u32 mask,u32 value)262 static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
263 {
264 	unsigned try = GTT_RETRY;
265 	u32 data;
266 
267 	while (try--) {
268 		data = gtt_read(bar, reg);
269 		if ((data & mask) == value)
270 			return 1;
271 		udelay(10);
272 	}
273 
274 	printf("GT init timeout\n");
275 	return 0;
276 }
277 
gma_pm_init_pre_vbios(void * gtt_bar,int rev)278 static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
279 {
280 	u32 reg32;
281 
282 	debug("GT Power Management Init, silicon = %#x\n", rev);
283 
284 	if (rev < IVB_STEP_C0) {
285 		/* 1: Enable force wake */
286 		gtt_write(gtt_bar, 0xa18c, 0x00000001);
287 		gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
288 	} else {
289 		gtt_write(gtt_bar, 0xa180, 1 << 5);
290 		gtt_write(gtt_bar, 0xa188, 0xffff0001);
291 		gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
292 	}
293 
294 	if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
295 		/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
296 		reg32 = gtt_read(gtt_bar, 0x42004);
297 		reg32 |= (1 << 14) | (1 << 15);
298 		gtt_write(gtt_bar, 0x42004, reg32);
299 	}
300 
301 	if (rev >= IVB_STEP_A0) {
302 		/* Display Reset Acknowledge Settings */
303 		reg32 = gtt_read(gtt_bar, 0x45010);
304 		reg32 |= (1 << 1) | (1 << 0);
305 		gtt_write(gtt_bar, 0x45010, reg32);
306 	}
307 
308 	/* 2: Get GT SKU from GTT+0x911c[13] */
309 	reg32 = gtt_read(gtt_bar, 0x911c);
310 	if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
311 		if (reg32 & (1 << 13)) {
312 			debug("SNB GT1 Power Meter Weights\n");
313 			gtt_write_powermeter(gtt_bar, snb_pm_gt1);
314 		} else {
315 			debug("SNB GT2 Power Meter Weights\n");
316 			gtt_write_powermeter(gtt_bar, snb_pm_gt2);
317 		}
318 	} else {
319 		u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
320 
321 		if (reg32 & (1 << 13)) {
322 			/* GT1 SKU */
323 			debug("IVB GT1 Power Meter Weights\n");
324 			gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
325 		} else {
326 			/* GT2 SKU */
327 			u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
328 			tdp /= (1 << unit);
329 
330 			if (tdp <= 17) {
331 				/* <=17W ULV */
332 				debug("IVB GT2 17W Power Meter Weights\n");
333 				gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
334 			} else if ((tdp >= 25) && (tdp <= 35)) {
335 				/* 25W-35W */
336 				debug("IVB GT2 25W-35W Power Meter Weights\n");
337 				gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
338 			} else {
339 				/* All others */
340 				debug("IVB GT2 35W Power Meter Weights\n");
341 				gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
342 			}
343 		}
344 	}
345 
346 	/* 3: Gear ratio map */
347 	gtt_write(gtt_bar, 0xa004, 0x00000010);
348 
349 	/* 4: GFXPAUSE */
350 	gtt_write(gtt_bar, 0xa000, 0x00070020);
351 
352 	/* 5: Dynamic EU trip control */
353 	gtt_write(gtt_bar, 0xa080, 0x00000004);
354 
355 	/* 6: ECO bits */
356 	reg32 = gtt_read(gtt_bar, 0xa180);
357 	reg32 |= (1 << 26) | (1 << 31);
358 	/* (bit 20=1 for SNB step D1+ / IVB A0+) */
359 	if (rev >= SNB_STEP_D1)
360 		reg32 |= (1 << 20);
361 	gtt_write(gtt_bar, 0xa180, reg32);
362 
363 	/* 6a: for SnB step D2+ only */
364 	if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
365 	    (rev >= SNB_STEP_D2)) {
366 		reg32 = gtt_read(gtt_bar, 0x9400);
367 		reg32 |= (1 << 7);
368 		gtt_write(gtt_bar, 0x9400, reg32);
369 
370 		reg32 = gtt_read(gtt_bar, 0x941c);
371 		reg32 &= 0xf;
372 		reg32 |= (1 << 1);
373 		gtt_write(gtt_bar, 0x941c, reg32);
374 		gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
375 	}
376 
377 	if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
378 		reg32 = gtt_read(gtt_bar, 0x907c);
379 		reg32 |= (1 << 16);
380 		gtt_write(gtt_bar, 0x907c, reg32);
381 
382 		/* 6b: Clocking reset controls */
383 		gtt_write(gtt_bar, 0x9424, 0x00000001);
384 	} else {
385 		/* 6b: Clocking reset controls */
386 		gtt_write(gtt_bar, 0x9424, 0x00000000);
387 	}
388 
389 	/* 7 */
390 	if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
391 		gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
392 		/* Mailbox Cmd for RC6 VID */
393 		gtt_write(gtt_bar, 0x138124, 0x80000004);
394 		if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
395 			gtt_write(gtt_bar, 0x138124, 0x8000000a);
396 		gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
397 	}
398 
399 	/* 8 */
400 	gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
401 	gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
402 	gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
403 	gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
404 	gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
405 	gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
406 
407 	/* 9 */
408 	gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
409 	gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
410 	gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
411 
412 	/* 10 */
413 	gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
414 	gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
415 	gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
416 	gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
417 	gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
418 
419 	/* 11 */
420 	gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
421 	gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
422 	gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
423 	gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
424 	gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
425 	gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
426 	gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
427 
428 	/* 11a: Enable Render Standby (RC6) */
429 	if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
430 		/*
431 		 * IvyBridge should also support DeepRenderStandby.
432 		 *
433 		 * Unfortunately it does not work reliably on all SKUs so
434 		 * disable it here and it can be enabled by the kernel.
435 		 */
436 		gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
437 	} else {
438 		gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
439 	}
440 
441 	/* 12: Normal Frequency Request */
442 	/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
443 	reg32 = readl(MCHBAR_REG(0x5998));
444 	reg32 >>= 16;
445 	reg32 &= 0xef;
446 	reg32 <<= 25;
447 	gtt_write(gtt_bar, 0xa008, reg32);
448 
449 	/* 13: RP Control */
450 	gtt_write(gtt_bar, 0xa024, 0x00000592);
451 
452 	/* 14: Enable PM Interrupts */
453 	gtt_write(gtt_bar, 0x4402c, 0x03000076);
454 
455 	/* Clear 0x6c024 [8:6] */
456 	reg32 = gtt_read(gtt_bar, 0x6c024);
457 	reg32 &= ~0x000001c0;
458 	gtt_write(gtt_bar, 0x6c024, reg32);
459 
460 	return 0;
461 }
462 
gma_pm_init_post_vbios(struct udevice * dev,int rev,void * gtt_bar)463 static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
464 {
465 	const void *blob = gd->fdt_blob;
466 	int node = dev_of_offset(dev);
467 	u32 reg32, cycle_delay;
468 
469 	debug("GT Power Management Init (post VBIOS)\n");
470 
471 	/* 15: Deassert Force Wake */
472 	if (rev < IVB_STEP_C0) {
473 		gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
474 		gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
475 	} else {
476 		gtt_write(gtt_bar, 0xa188, 0x1fffe);
477 		if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
478 			gtt_write(gtt_bar, 0xa188,
479 				  gtt_read(gtt_bar, 0xa188) | 1);
480 		}
481 	}
482 
483 	/* 16: SW RC Control */
484 	gtt_write(gtt_bar, 0xa094, 0x00060000);
485 
486 	/* Setup Digital Port Hotplug */
487 	reg32 = gtt_read(gtt_bar, 0xc4030);
488 	if (!reg32) {
489 		u32 dp_hotplug[3];
490 
491 		if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
492 					 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
493 			return -EINVAL;
494 
495 		reg32 = (dp_hotplug[0] & 0x7) << 2;
496 		reg32 |= (dp_hotplug[0] & 0x7) << 10;
497 		reg32 |= (dp_hotplug[0] & 0x7) << 18;
498 		gtt_write(gtt_bar, 0xc4030, reg32);
499 	}
500 
501 	/* Setup Panel Power On Delays */
502 	reg32 = gtt_read(gtt_bar, 0xc7208);
503 	if (!reg32) {
504 		reg32 = (unsigned)fdtdec_get_int(blob, node,
505 						 "panel-port-select", 0) << 30;
506 		reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
507 				<< 16;
508 		reg32 |= fdtdec_get_int(blob, node,
509 					"panel-power-backlight-on-delay", 0);
510 		gtt_write(gtt_bar, 0xc7208, reg32);
511 	}
512 
513 	/* Setup Panel Power Off Delays */
514 	reg32 = gtt_read(gtt_bar, 0xc720c);
515 	if (!reg32) {
516 		reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
517 				<< 16;
518 		reg32 |= fdtdec_get_int(blob, node,
519 					"panel-power-backlight-off-delay", 0);
520 		gtt_write(gtt_bar, 0xc720c, reg32);
521 	}
522 
523 	/* Setup Panel Power Cycle Delay */
524 	cycle_delay = fdtdec_get_int(blob, node,
525 				     "intel,panel-power-cycle-delay", 0);
526 	if (cycle_delay) {
527 		reg32 = gtt_read(gtt_bar, 0xc7210);
528 		reg32 &= ~0xff;
529 		reg32 |= cycle_delay;
530 		gtt_write(gtt_bar, 0xc7210, reg32);
531 	}
532 
533 	/* Enable Backlight if needed */
534 	reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
535 	if (reg32) {
536 		gtt_write(gtt_bar, 0x48250, (1 << 31));
537 		gtt_write(gtt_bar, 0x48254, reg32);
538 	}
539 	reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
540 	if (reg32) {
541 		gtt_write(gtt_bar, 0xc8250, (1 << 31));
542 		gtt_write(gtt_bar, 0xc8254, reg32);
543 	}
544 
545 	return 0;
546 }
547 
548 /*
549  * Some vga option roms are used for several chipsets but they only have one
550  * PCI ID in their header. If we encounter such an option rom, we need to do
551  * the mapping ourselves.
552  */
553 
board_map_oprom_vendev(uint32_t vendev)554 uint32_t board_map_oprom_vendev(uint32_t vendev)
555 {
556 	switch (vendev) {
557 	case 0x80860102:		/* GT1 Desktop */
558 	case 0x8086010a:		/* GT1 Server */
559 	case 0x80860112:		/* GT2 Desktop */
560 	case 0x80860116:		/* GT2 Mobile */
561 	case 0x80860122:		/* GT2 Desktop >=1.3GHz */
562 	case 0x80860126:		/* GT2 Mobile >=1.3GHz */
563 	case 0x80860156:                /* IVB */
564 	case 0x80860166:                /* IVB */
565 		return 0x80860106;	/* GT1 Mobile */
566 	}
567 
568 	return vendev;
569 }
570 
int15_handler(void)571 static int int15_handler(void)
572 {
573 	int res = 0;
574 
575 	debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
576 
577 	switch (M.x86.R_AX) {
578 	case 0x5f34:
579 		/*
580 		 * Set Panel Fitting Hook:
581 		 *  bit 2 = Graphics Stretching
582 		 *  bit 1 = Text Stretching
583 		 *  bit 0 = Centering (do not set with bit1 or bit2)
584 		 *  0     = video bios default
585 		 */
586 		M.x86.R_AX = 0x005f;
587 		M.x86.R_CL = 0x00; /* Use video bios default */
588 		res = 1;
589 		break;
590 	case 0x5f35:
591 		/*
592 		 * Boot Display Device Hook:
593 		 *  bit 0 = CRT
594 		 *  bit 1 = TV (eDP)
595 		 *  bit 2 = EFP
596 		 *  bit 3 = LFP
597 		 *  bit 4 = CRT2
598 		 *  bit 5 = TV2 (eDP)
599 		 *  bit 6 = EFP2
600 		 *  bit 7 = LFP2
601 		 */
602 		M.x86.R_AX = 0x005f;
603 		M.x86.R_CX = 0x0000; /* Use video bios default */
604 		res = 1;
605 		break;
606 	case 0x5f51:
607 		/*
608 		 * Hook to select active LFP configuration:
609 		 *  00h = No LVDS, VBIOS does not enable LVDS
610 		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
611 		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
612 		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
613 		 */
614 		M.x86.R_AX = 0x005f;
615 		M.x86.R_CX = 0x0003; /* eDP */
616 		res = 1;
617 		break;
618 	case 0x5f70:
619 		switch (M.x86.R_CH) {
620 		case 0:
621 			/* Get Mux */
622 			M.x86.R_AX = 0x005f;
623 			M.x86.R_CX = 0x0000;
624 			res = 1;
625 			break;
626 		case 1:
627 			/* Set Mux */
628 			M.x86.R_AX = 0x005f;
629 			M.x86.R_CX = 0x0000;
630 			res = 1;
631 			break;
632 		case 2:
633 			/* Get SG/Non-SG mode */
634 			M.x86.R_AX = 0x005f;
635 			M.x86.R_CX = 0x0000;
636 			res = 1;
637 			break;
638 		default:
639 			/* Interrupt was not handled */
640 			debug("Unknown INT15 5f70 function: 0x%02x\n",
641 			      M.x86.R_CH);
642 			break;
643 		}
644 		break;
645 	case 0x5fac:
646 		res = 1;
647 		break;
648 	default:
649 		debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
650 		break;
651 	}
652 	return res;
653 }
654 
sandybridge_setup_graphics(struct udevice * dev,struct udevice * video_dev)655 static void sandybridge_setup_graphics(struct udevice *dev,
656 				       struct udevice *video_dev)
657 {
658 	u32 reg32;
659 	u16 reg16;
660 	u8 reg8;
661 
662 	dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16);
663 	switch (reg16) {
664 	case 0x0102: /* GT1 Desktop */
665 	case 0x0106: /* GT1 Mobile */
666 	case 0x010a: /* GT1 Server */
667 	case 0x0112: /* GT2 Desktop */
668 	case 0x0116: /* GT2 Mobile */
669 	case 0x0122: /* GT2 Desktop >=1.3GHz */
670 	case 0x0126: /* GT2 Mobile >=1.3GHz */
671 	case 0x0156: /* IvyBridge */
672 	case 0x0166: /* IvyBridge */
673 		break;
674 	default:
675 		debug("Graphics not supported by this CPU/chipset\n");
676 		return;
677 	}
678 
679 	debug("Initialising Graphics\n");
680 
681 	/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
682 	dm_pci_read_config16(dev, GGC, &reg16);
683 	reg16 &= ~0x00f8;
684 	reg16 |= 1 << 3;
685 	/* Program GTT memory by setting GGC[9:8] = 2MB */
686 	reg16 &= ~0x0300;
687 	reg16 |= 2 << 8;
688 	/* Enable VGA decode */
689 	reg16 &= ~0x0002;
690 	dm_pci_write_config16(dev, GGC, reg16);
691 
692 	/* Enable 256MB aperture */
693 	dm_pci_read_config8(video_dev, MSAC, &reg8);
694 	reg8 &= ~0x06;
695 	reg8 |= 0x02;
696 	dm_pci_write_config8(video_dev, MSAC, reg8);
697 
698 	/* Erratum workarounds */
699 	reg32 = readl(MCHBAR_REG(0x5f00));
700 	reg32 |= (1 << 9) | (1 << 10);
701 	writel(reg32, MCHBAR_REG(0x5f00));
702 
703 	/* Enable SA Clock Gating */
704 	reg32 = readl(MCHBAR_REG(0x5f00));
705 	writel(reg32 | 1, MCHBAR_REG(0x5f00));
706 
707 	/* GPU RC6 workaround for sighting 366252 */
708 	reg32 = readl(MCHBAR_REG(0x5d14));
709 	reg32 |= (1 << 31);
710 	writel(reg32, MCHBAR_REG(0x5d14));
711 
712 	/* VLW */
713 	reg32 = readl(MCHBAR_REG(0x6120));
714 	reg32 &= ~(1 << 0);
715 	writel(reg32, MCHBAR_REG(0x6120));
716 
717 	reg32 = readl(MCHBAR_REG(0x5418));
718 	reg32 |= (1 << 4) | (1 << 5);
719 	writel(reg32, MCHBAR_REG(0x5418));
720 }
721 
gma_func0_init(struct udevice * dev)722 static int gma_func0_init(struct udevice *dev)
723 {
724 	struct udevice *nbridge;
725 	void *gtt_bar;
726 	u32 reg32;
727 	int ret;
728 	int rev;
729 
730 	/* Enable PCH Display Port */
731 	writew(0x0010, RCB_REG(DISPBDF));
732 	setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
733 
734 	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
735 	if (ret)
736 		return ret;
737 	rev = bridge_silicon_revision(nbridge);
738 	sandybridge_setup_graphics(nbridge, dev);
739 
740 	/* IGD needs to be Bus Master */
741 	dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
742 	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
743 	dm_pci_write_config32(dev, PCI_COMMAND, reg32);
744 
745 	gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
746 	debug("GT bar %p\n", gtt_bar);
747 	ret = gma_pm_init_pre_vbios(gtt_bar, rev);
748 	if (ret)
749 		return ret;
750 
751 	return rev;
752 }
753 
bd82x6x_video_probe(struct udevice * dev)754 static int bd82x6x_video_probe(struct udevice *dev)
755 {
756 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
757 	ulong fbbase;
758 	void *gtt_bar;
759 	int ret, rev;
760 
761 	rev = gma_func0_init(dev);
762 	if (rev < 0)
763 		return rev;
764 	ret = vesa_setup_video(dev, int15_handler);
765 	if (ret)
766 		return ret;
767 
768 	/* Post VBIOS init */
769 	gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
770 	ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
771 	if (ret)
772 		return ret;
773 
774 	/* Use write-combining for the graphics memory, 256MB */
775 	fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
776 	mtrr_set_next_var(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
777 
778 	return 0;
779 }
780 
bd82x6x_video_bind(struct udevice * dev)781 static int bd82x6x_video_bind(struct udevice *dev)
782 {
783 	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
784 
785 	/* Set the maximum supported resolution */
786 	uc_plat->size = 2560 * 1600 * 4;
787 	log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
788 
789 	return 0;
790 }
791 
792 static const struct udevice_id bd82x6x_video_ids[] = {
793 	{ .compatible = "intel,gma" },
794 	{ }
795 };
796 
797 U_BOOT_DRIVER(bd82x6x_video) = {
798 	.name	= "bd82x6x_video",
799 	.id	= UCLASS_VIDEO,
800 	.of_match = bd82x6x_video_ids,
801 	.bind	= bd82x6x_video_bind,
802 	.probe	= bd82x6x_video_probe,
803 };
804