1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * Copyright 2021 NXP
8 */
9
10 #include <env.h>
11 #include <init.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <asm/io.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/bootm.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/dma.h>
21 #include <asm/mach-imx/hab.h>
22 #include <stdbool.h>
23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/crm_regs.h>
25 #include <dm.h>
26 #include <imx_thermal.h>
27 #include <mmc.h>
28
29 #define has_err007805() \
30 (is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull())
31
32 struct scu_regs {
33 u32 ctrl;
34 u32 config;
35 u32 status;
36 u32 invalidate;
37 u32 fpga_rev;
38 };
39
40 #if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX_THERMAL)
41 static const struct imx_thermal_plat imx6_thermal_plat = {
42 .regs = (void *)ANATOP_BASE_ADDR,
43 .fuse_bank = 1,
44 .fuse_word = 6,
45 };
46
47 U_BOOT_DRVINFO(imx6_thermal) = {
48 .name = "imx_thermal",
49 .plat = &imx6_thermal_plat,
50 };
51 #endif
52
53 #if defined(CONFIG_IMX_HAB)
54 struct imx_fuse const imx_sec_config_fuse = {
55 .bank = 0,
56 .word = 6,
57 };
58
59 struct imx_fuse const imx_field_return_fuse = {
60 .bank = 5,
61 .word = 6,
62 };
63 #endif
64
get_nr_cpus(void)65 u32 get_nr_cpus(void)
66 {
67 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
68 return readl(&scu->config) & 3;
69 }
70
get_cpu_rev(void)71 u32 get_cpu_rev(void)
72 {
73 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
74 u32 reg = readl(&anatop->digprog_sololite);
75 u32 type = ((reg >> 16) & 0xff);
76 u32 major, cfg = 0;
77
78 if (type != MXC_CPU_MX6SL) {
79 reg = readl(&anatop->digprog);
80 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
81 cfg = readl(&scu->config) & 3;
82 type = ((reg >> 16) & 0xff);
83 if (type == MXC_CPU_MX6DL) {
84 if (!cfg)
85 type = MXC_CPU_MX6SOLO;
86 }
87
88 if (type == MXC_CPU_MX6Q) {
89 if (cfg == 1)
90 type = MXC_CPU_MX6D;
91 }
92
93 if (type == MXC_CPU_MX6ULL) {
94 if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
95 type = MXC_CPU_MX6ULZ;
96 }
97 }
98 major = ((reg >> 8) & 0xff);
99 if ((major >= 1) &&
100 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
101 major--;
102 type = MXC_CPU_MX6QP;
103 if (cfg == 1)
104 type = MXC_CPU_MX6DP;
105 }
106 reg &= 0xff; /* mx6 silicon revision */
107
108 /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
109 if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
110 reg = 0x3;
111
112 return (type << 12) | (reg + (0x10 * (major + 1)));
113 }
114
115 /*
116 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
117 * defines a 2-bit SPEED_GRADING
118 */
119 #define OCOTP_CFG3_SPEED_SHIFT 16
120 #define OCOTP_CFG3_SPEED_800MHZ 0
121 #define OCOTP_CFG3_SPEED_850MHZ 1
122 #define OCOTP_CFG3_SPEED_1GHZ 2
123 #define OCOTP_CFG3_SPEED_1P2GHZ 3
124
125 /*
126 * For i.MX6UL
127 */
128 #define OCOTP_CFG3_SPEED_528MHZ 1
129 #define OCOTP_CFG3_SPEED_696MHZ 2
130
131 /*
132 * For i.MX6ULL
133 */
134 #define OCOTP_CFG3_SPEED_792MHZ 2
135 #define OCOTP_CFG3_SPEED_900MHZ 3
136
get_cpu_speed_grade_hz(void)137 u32 get_cpu_speed_grade_hz(void)
138 {
139 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
140 struct fuse_bank *bank = &ocotp->bank[0];
141 struct fuse_bank0_regs *fuse =
142 (struct fuse_bank0_regs *)bank->fuse_regs;
143 uint32_t val;
144
145 val = readl(&fuse->cfg3);
146 val >>= OCOTP_CFG3_SPEED_SHIFT;
147 val &= 0x3;
148
149 if (is_mx6ul()) {
150 if (val == OCOTP_CFG3_SPEED_528MHZ)
151 return 528000000;
152 else if (val == OCOTP_CFG3_SPEED_696MHZ)
153 return 696000000;
154 else
155 return 0;
156 }
157
158 if (is_mx6ull()) {
159 if (val == OCOTP_CFG3_SPEED_528MHZ)
160 return 528000000;
161 else if (val == OCOTP_CFG3_SPEED_792MHZ)
162 return 792000000;
163 else if (val == OCOTP_CFG3_SPEED_900MHZ)
164 return 900000000;
165 else
166 return 0;
167 }
168
169 switch (val) {
170 /* Valid for IMX6DQ */
171 case OCOTP_CFG3_SPEED_1P2GHZ:
172 if (is_mx6dq() || is_mx6dqp())
173 return 1200000000;
174 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
175 case OCOTP_CFG3_SPEED_1GHZ:
176 return 996000000;
177 /* Valid for IMX6DQ */
178 case OCOTP_CFG3_SPEED_850MHZ:
179 if (is_mx6dq() || is_mx6dqp())
180 return 852000000;
181 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
182 case OCOTP_CFG3_SPEED_800MHZ:
183 return 792000000;
184 }
185 return 0;
186 }
187
188 /*
189 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
190 * defines a 2-bit Temperature Grade
191 *
192 * return temperature grade and min/max temperature in Celsius
193 */
194 #define OCOTP_MEM0_TEMP_SHIFT 6
195
get_cpu_temp_grade(int * minc,int * maxc)196 u32 get_cpu_temp_grade(int *minc, int *maxc)
197 {
198 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
199 struct fuse_bank *bank = &ocotp->bank[1];
200 struct fuse_bank1_regs *fuse =
201 (struct fuse_bank1_regs *)bank->fuse_regs;
202 uint32_t val;
203
204 val = readl(&fuse->mem0);
205 val >>= OCOTP_MEM0_TEMP_SHIFT;
206 val &= 0x3;
207
208 if (minc && maxc) {
209 if (val == TEMP_AUTOMOTIVE) {
210 *minc = -40;
211 *maxc = 125;
212 } else if (val == TEMP_INDUSTRIAL) {
213 *minc = -40;
214 *maxc = 105;
215 } else if (val == TEMP_EXTCOMMERCIAL) {
216 *minc = -20;
217 *maxc = 105;
218 } else {
219 *minc = 0;
220 *maxc = 95;
221 }
222 }
223 return val;
224 }
225
226 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)227 u32 __weak get_board_rev(void)
228 {
229 u32 cpurev = get_cpu_rev();
230 u32 type = ((cpurev >> 12) & 0xff);
231 if (type == MXC_CPU_MX6SOLO)
232 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
233
234 if (type == MXC_CPU_MX6D)
235 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
236
237 return cpurev;
238 }
239 #endif
240
clear_ldo_ramp(void)241 static void clear_ldo_ramp(void)
242 {
243 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
244 int reg;
245
246 /* ROM may modify LDO ramp up time according to fuse setting, so in
247 * order to be in the safe side we neeed to reset these settings to
248 * match the reset value: 0'b00
249 */
250 reg = readl(&anatop->ana_misc2);
251 reg &= ~(0x3f << 24);
252 writel(reg, &anatop->ana_misc2);
253 }
254
255 /*
256 * Set the PMU_REG_CORE register
257 *
258 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
259 * Possible values are from 0.725V to 1.450V in steps of
260 * 0.025V (25mV).
261 */
set_ldo_voltage(enum ldo_reg ldo,u32 mv)262 int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
263 {
264 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
265 u32 val, step, old, reg = readl(&anatop->reg_core);
266 u8 shift;
267
268 /* No LDO_SOC/PU/ARM */
269 if (is_mx6sll())
270 return 0;
271
272 if (mv < 725)
273 val = 0x00; /* Power gated off */
274 else if (mv > 1450)
275 val = 0x1F; /* Power FET switched full on. No regulation */
276 else
277 val = (mv - 700) / 25;
278
279 clear_ldo_ramp();
280
281 switch (ldo) {
282 case LDO_SOC:
283 shift = 18;
284 break;
285 case LDO_PU:
286 shift = 9;
287 break;
288 case LDO_ARM:
289 shift = 0;
290 break;
291 default:
292 return -EINVAL;
293 }
294
295 old = (reg & (0x1F << shift)) >> shift;
296 step = abs(val - old);
297 if (step == 0)
298 return 0;
299
300 reg = (reg & ~(0x1F << shift)) | (val << shift);
301 writel(reg, &anatop->reg_core);
302
303 /*
304 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
305 * step
306 */
307 udelay(3 * step);
308
309 return 0;
310 }
311
set_ahb_rate(u32 val)312 static void set_ahb_rate(u32 val)
313 {
314 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
315 u32 reg, div;
316
317 div = get_periph_clk() / val - 1;
318 reg = readl(&mxc_ccm->cbcdr);
319
320 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
321 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
322 }
323
clear_mmdc_ch_mask(void)324 static void clear_mmdc_ch_mask(void)
325 {
326 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
327 u32 reg;
328 reg = readl(&mxc_ccm->ccdr);
329
330 /* Clear MMDC channel mask */
331 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
332 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
333 else
334 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
335 writel(reg, &mxc_ccm->ccdr);
336 }
337
338 #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
339
init_bandgap(void)340 static void init_bandgap(void)
341 {
342 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
343 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
344 struct fuse_bank *bank = &ocotp->bank[1];
345 struct fuse_bank1_regs *fuse =
346 (struct fuse_bank1_regs *)bank->fuse_regs;
347 uint32_t val;
348
349 /*
350 * Ensure the bandgap has stabilized.
351 */
352 while (!(readl(&anatop->ana_misc0) & 0x80))
353 ;
354 /*
355 * For best noise performance of the analog blocks using the
356 * outputs of the bandgap, the reftop_selfbiasoff bit should
357 * be set.
358 */
359 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
360 /*
361 * On i.MX6ULL,we need to set VBGADJ bits according to the
362 * REFTOP_TRIM[3:0] in fuse table
363 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
364 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
365 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
366 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
367 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
368 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
369 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
370 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
371 */
372 if (is_mx6ull()) {
373 static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7};
374
375 val = readl(&fuse->mem0);
376 val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
377 val &= 0x7;
378
379 writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
380 &anatop->ana_misc0_set);
381 }
382 }
383
384 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
noc_setup(void)385 static void noc_setup(void)
386 {
387 enable_ipu_clock();
388
389 writel(0x80000201, 0xbb0608);
390 /* Bypass IPU1 QoS generator */
391 writel(0x00000002, 0x00bb048c);
392 /* Bypass IPU2 QoS generator */
393 writel(0x00000002, 0x00bb050c);
394 /* Bandwidth THR for of PRE0 */
395 writel(0x00000200, 0x00bb0690);
396 /* Bandwidth THR for of PRE1 */
397 writel(0x00000200, 0x00bb0710);
398 /* Bandwidth THR for of PRE2 */
399 writel(0x00000200, 0x00bb0790);
400 /* Bandwidth THR for of PRE3 */
401 writel(0x00000200, 0x00bb0810);
402 /* Saturation THR for of PRE0 */
403 writel(0x00000010, 0x00bb0694);
404 /* Saturation THR for of PRE1 */
405 writel(0x00000010, 0x00bb0714);
406 /* Saturation THR for of PRE2 */
407 writel(0x00000010, 0x00bb0794);
408 /* Saturation THR for of PRE */
409 writel(0x00000010, 0x00bb0814);
410
411 disable_ipu_clock();
412 }
413 #endif
414
arch_cpu_init(void)415 int arch_cpu_init(void)
416 {
417 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
418
419 init_aips();
420
421 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
422 clear_mmdc_ch_mask();
423
424 /*
425 * Disable self-bias circuit in the analog bandap.
426 * The self-bias circuit is used by the bandgap during startup.
427 * This bit should be set after the bandgap has initialized.
428 */
429 init_bandgap();
430
431 if (!is_mx6ul() && !is_mx6ull()) {
432 /*
433 * When low freq boot is enabled, ROM will not set AHB
434 * freq, so we need to ensure AHB freq is 132MHz in such
435 * scenario.
436 *
437 * To i.MX6UL, when power up, default ARM core and
438 * AHB rate is 396M and 132M.
439 */
440 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
441 set_ahb_rate(132000000);
442 }
443
444 if (is_mx6ul()) {
445 if (is_soc_rev(CHIP_REV_1_0) == 0) {
446 /*
447 * According to the design team's requirement on
448 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
449 * as open drain 100K (0x0000b8a0).
450 * Only exists on TO1.0
451 */
452 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
453 } else {
454 /*
455 * From TO1.1, SNVS adds internal pull up control
456 * for POR_B, the register filed is GPBIT[1:0],
457 * after system boot up, it can be set to 2b'01
458 * to disable internal pull up.It can save about
459 * 30uA power in SNVS mode.
460 */
461 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
462 (~0x1400)) | 0x400,
463 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
464 }
465 }
466
467 if (is_mx6ull()) {
468 /*
469 * GPBIT[1:0] is suggested to set to 2'b11:
470 * 2'b00 : always PUP100K
471 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
472 * 2'b10 : always disable PUP100K
473 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
474 * register offset is different from i.MX6UL, since
475 * i.MX6UL is fixed by ECO.
476 */
477 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
478 0x3, MX6UL_SNVS_LP_BASE_ADDR);
479 }
480
481 /* Set perclk to source from OSC 24MHz */
482 if (has_err007805())
483 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
484
485 imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
486
487 if (is_mx6sx())
488 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
489
490 init_src();
491
492 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
493 if (is_mx6dqp())
494 noc_setup();
495 #endif
496
497 enable_ca7_smp();
498
499 return 0;
500 }
501
502 #ifdef CONFIG_ENV_IS_IN_MMC
board_mmc_get_env_dev(int devno)503 __weak int board_mmc_get_env_dev(int devno)
504 {
505 return CONFIG_ENV_MMC_DEVICE_INDEX;
506 }
507
mmc_get_boot_dev(void)508 static int mmc_get_boot_dev(void)
509 {
510 u32 soc_sbmr = imx6_src_get_boot_mode();
511 u32 bootsel;
512 int devno;
513
514 /*
515 * Refer to
516 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
517 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
518 * i.MX6SL/SX/UL has same layout.
519 */
520 bootsel = (soc_sbmr & 0x000000FF) >> 6;
521
522 /* No boot from sd/mmc */
523 if (bootsel != 1)
524 return -1;
525
526 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
527 devno = (soc_sbmr & 0x00001800) >> 11;
528
529 return devno;
530 }
531
mmc_get_env_dev(void)532 int mmc_get_env_dev(void)
533 {
534 int devno = mmc_get_boot_dev();
535
536 /* If not boot from sd/mmc, use default value */
537 if (devno < 0)
538 return CONFIG_ENV_MMC_DEVICE_INDEX;
539
540 return board_mmc_get_env_dev(devno);
541 }
542
543 #ifdef CONFIG_ENV_MMC_EMMC_HW_PARTITION
board_mmc_get_env_part(int devno)544 __weak int board_mmc_get_env_part(int devno)
545 {
546 return CONFIG_ENV_MMC_EMMC_HW_PARTITION;
547 }
548
mmc_get_env_part(struct mmc * mmc)549 uint mmc_get_env_part(struct mmc *mmc)
550 {
551 int devno = mmc_get_boot_dev();
552
553 /* If not boot from sd/mmc, use default value */
554 if (devno < 0)
555 return CONFIG_ENV_MMC_EMMC_HW_PARTITION;
556
557 return board_mmc_get_env_part(devno);
558 }
559 #endif
560 #endif
561
board_postclk_init(void)562 int board_postclk_init(void)
563 {
564 /* NO LDO SOC on i.MX6SLL */
565 if (is_mx6sll())
566 return 0;
567
568 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
569
570 return 0;
571 }
572
573 #ifndef CONFIG_XPL_BUILD
574 /*
575 * cfg_val will be used for
576 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
577 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
578 * instead of SBMR1 to determine the boot device.
579 */
580 const struct boot_mode soc_boot_modes[] = {
581 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
582 /* reserved value should start rom usb */
583 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
584 {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
585 #else
586 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
587 #endif
588 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
589 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
590 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
591 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
592 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
593 {"ecspi3:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0a)},
594 {"ecspi3:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x1a)},
595 {"ecspi3:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x2a)},
596 {"ecspi3:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x3a)},
597 /* 4 bit bus width */
598 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
599 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
600 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
601 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
602 {NULL, 0},
603 };
604 #endif
605
reset_misc(void)606 void reset_misc(void)
607 {
608 #ifndef CONFIG_XPL_BUILD
609 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
610 lcdif_power_down();
611 #endif
612 #endif
613 }
614
s_init(void)615 void s_init(void)
616 {
617 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
618 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
619 u32 mask480;
620 u32 mask528;
621 u32 reg, periph1, periph2;
622
623 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
624 return;
625
626 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
627 * to make sure PFD is working right, otherwise, PFDs may
628 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
629 * workaround in ROM code, as bus clock need it
630 */
631
632 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
633 ANATOP_PFD_CLKGATE_MASK(1) |
634 ANATOP_PFD_CLKGATE_MASK(2) |
635 ANATOP_PFD_CLKGATE_MASK(3);
636 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
637 ANATOP_PFD_CLKGATE_MASK(3);
638
639 reg = readl(&ccm->cbcmr);
640 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
641 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
642 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
643 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
644
645 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
646 if ((periph2 != 0x2) && (periph1 != 0x2))
647 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
648
649 if ((periph2 != 0x1) && (periph1 != 0x1) &&
650 (periph2 != 0x3) && (periph1 != 0x3))
651 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
652
653 writel(mask480, &anatop->pfd_480_set);
654 writel(mask528, &anatop->pfd_528_set);
655 writel(mask480, &anatop->pfd_480_clr);
656 writel(mask528, &anatop->pfd_528_clr);
657 }
658
659 #ifdef CONFIG_IMX_HDMI
imx_enable_hdmi_phy(void)660 void imx_enable_hdmi_phy(void)
661 {
662 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
663 u8 reg;
664 reg = readb(&hdmi->phy_conf0);
665 reg |= HDMI_PHY_CONF0_PDZ_MASK;
666 writeb(reg, &hdmi->phy_conf0);
667 udelay(3000);
668 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
669 writeb(reg, &hdmi->phy_conf0);
670 udelay(3000);
671 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
672 writeb(reg, &hdmi->phy_conf0);
673 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
674 }
675
imx_setup_hdmi(void)676 void imx_setup_hdmi(void)
677 {
678 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
679 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
680 int reg, count;
681 u8 val;
682
683 /* Turn on HDMI PHY clock */
684 reg = readl(&mxc_ccm->CCGR2);
685 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
686 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
687 writel(reg, &mxc_ccm->CCGR2);
688 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
689 reg = readl(&mxc_ccm->chsccdr);
690 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
691 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
692 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
693 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
694 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
695 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
696 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
697 writel(reg, &mxc_ccm->chsccdr);
698
699 /* Clear the overflow condition */
700 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
701 /* TMDS software reset */
702 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
703 val = readb(&hdmi->fc_invidconf);
704 /* Need minimum 3 times to write to clear the register */
705 for (count = 0 ; count < 5 ; count++)
706 writeb(val, &hdmi->fc_invidconf);
707 }
708 }
709 #endif
710
711 #ifdef CONFIG_ARCH_MISC_INIT
712 /*
713 * UNIQUE_ID describes a unique ID based on silicon wafer
714 * and die X/Y position
715 *
716 * UNIQUE_ID offset 0x410
717 * 31:0 fuse 0
718 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
719 *
720 * UNIQUE_ID offset 0x420
721 * 31:24 fuse 1
722 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
723 * 23:16 fuse 1
724 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
725 * 15:11 fuse 1
726 * The wafer number of the wafer on which the device was fabricated/SJC
727 * CHALLENGE/ Unique ID
728 * 10:0 fuse 1
729 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
730 */
setup_serial_number(void)731 static void setup_serial_number(void)
732 {
733 char serial_string[17];
734 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
735 struct fuse_bank *bank = &ocotp->bank[0];
736 struct fuse_bank0_regs *fuse =
737 (struct fuse_bank0_regs *)bank->fuse_regs;
738
739 if (env_get("serial#"))
740 return;
741
742 snprintf(serial_string, sizeof(serial_string), "%08x%08x",
743 fuse->uid_low, fuse->uid_high);
744 env_set("serial#", serial_string);
745 }
746
arch_misc_init(void)747 int arch_misc_init(void)
748 {
749 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
750 struct udevice *dev;
751 int ret;
752
753 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
754 if (ret)
755 printf("Failed to initialize caam_jr: %d\n", ret);
756 }
757
758 if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
759 struct udevice *dev;
760 int ret;
761
762 ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
763 if (ret)
764 printf("Failed to initialize dcp rng: %d\n", ret);
765 }
766
767 setup_serial_number();
768 return 0;
769 }
770 #endif
771
772 /*
773 * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
774 * MX6Q and MX6QP processors
775 */
gpr_init(void)776 void gpr_init(void)
777 {
778 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
779
780 /*
781 * If this function is used in a common MX6 spl implementation
782 * we have to ensure that it is only called for suitable cpu types,
783 * otherwise it breaks hardware parts like enet1, can1, can2, etc.
784 */
785 if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
786 return;
787
788 /* enable AXI cache for VDOA/VPU/IPU */
789 writel(0xF00000CF, &iomux->gpr[4]);
790 if (is_mx6dqp()) {
791 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
792 writel(0x77177717, &iomux->gpr[6]);
793 writel(0x77177717, &iomux->gpr[7]);
794 } else {
795 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
796 writel(0x007F007F, &iomux->gpr[6]);
797 writel(0x007F007F, &iomux->gpr[7]);
798 }
799 }
800