1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 5 */ 6 7 #ifndef _SYS_PROTO_H_ 8 #define _SYS_PROTO_H_ 9 10 #include <asm/io.h> 11 #include <asm/mach-imx/regs-common.h> 12 #include <asm/mach-imx/module_fuse.h> 13 #include <linux/bitops.h> 14 #include "../arch-imx/cpu.h" 15 16 struct bd_info; 17 18 #define soc_rev() (get_cpu_rev() & 0xFF) 19 #define is_soc_rev(rev) (soc_rev() == rev) 20 21 /* returns MXC_CPU_ value */ 22 #define cpu_type(rev) (((rev) >> 12) & 0x1ff) 23 #define soc_type(rev) (((rev) >> 12) & 0xf0) 24 /* both macros return/take MXC_CPU_ constants */ 25 #define get_cpu_type() (cpu_type(get_cpu_rev())) 26 #define get_soc_type() (soc_type(get_cpu_rev())) 27 #define is_cpu_type(cpu) (get_cpu_type() == cpu) 28 #define is_soc_type(soc) (get_soc_type() == soc) 29 30 #define is_mx6() (is_soc_type(MXC_SOC_MX6)) 31 #define is_mx7() (is_soc_type(MXC_SOC_MX7)) 32 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) 33 #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 34 #define is_imx9() (is_soc_type(MXC_SOC_IMX9)) 35 #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT)) 36 37 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 38 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 39 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) 40 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) 41 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) 42 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) 43 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) 44 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) 45 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) 46 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) 47 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) 48 49 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 50 51 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) 52 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) 53 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) 54 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) 55 #define is_imx8ulp() (is_cpu_type(MXC_CPU_IMX8ULP)) 56 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ 57 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ 58 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) 59 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) 60 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) 61 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) 62 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) 63 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) 64 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ 65 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ 66 is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \ 67 is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ)) 68 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) 69 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) 70 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) 71 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) 72 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) 73 #define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ)) 74 #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) 75 #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) 76 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ 77 is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL)) 78 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) 79 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) 80 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) 81 #define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL)) 82 83 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 84 85 #define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \ 86 is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \ 87 is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \ 88 is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311) || \ 89 is_cpu_type(MXC_CPU_IMX9302) || is_cpu_type(MXC_CPU_IMX9301)) 90 #define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351)) 91 #define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332)) 92 #define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331)) 93 #define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322)) 94 #define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321)) 95 #define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312)) 96 #define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311)) 97 #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302)) 98 #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301)) 99 100 #define is_imx95() (is_cpu_type(MXC_CPU_IMX95)) 101 102 #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121)) 103 #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111)) 104 #define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101)) 105 #define is_imx91() (is_cpu_type(MXC_CPU_IMX91) || is_cpu_type(MXC_CPU_IMX9111) || \ 106 is_cpu_type(MXC_CPU_IMX9101) || is_cpu_type(MXC_CPU_IMX9121)) 107 108 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) 109 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) 110 111 #ifdef CONFIG_MX6 112 #define IMX6_SRC_GPR10_BMODE BIT(28) 113 #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 114 115 #define IMX6_BMODE_MASK GENMASK(7, 0) 116 #define IMX6_BMODE_SHIFT 4 117 #define IMX6_BMODE_EIM_MASK BIT(3) 118 #define IMX6_BMODE_EIM_SHIFT 3 119 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) 120 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 121 122 enum imx6_bmode_serial_rom { 123 IMX6_BMODE_ECSPI1, 124 IMX6_BMODE_ECSPI2, 125 IMX6_BMODE_ECSPI3, 126 IMX6_BMODE_ECSPI4, 127 IMX6_BMODE_ECSPI5, 128 IMX6_BMODE_I2C1, 129 IMX6_BMODE_I2C2, 130 IMX6_BMODE_I2C3, 131 }; 132 133 enum imx6_bmode_eim { 134 IMX6_BMODE_NOR, 135 IMX6_BMODE_ONENAND, 136 }; 137 138 enum imx6_bmode { 139 IMX6_BMODE_EIM, 140 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 141 IMX6_BMODE_QSPI, 142 IMX6_BMODE_RESERVED, 143 #else 144 IMX6_BMODE_RESERVED, 145 IMX6_BMODE_SATA, 146 #endif 147 IMX6_BMODE_SERIAL_ROM, 148 IMX6_BMODE_SD, 149 IMX6_BMODE_ESD, 150 IMX6_BMODE_MMC, 151 IMX6_BMODE_EMMC, 152 IMX6_BMODE_NAND_MIN, 153 IMX6_BMODE_NAND_MAX = 0xf, 154 }; 155 156 u32 imx6_src_get_boot_mode(void); 157 void gpr_init(void); 158 159 #endif /* CONFIG_MX6 */ 160 161 #ifdef CONFIG_MX7 162 #define IMX7_SRC_GPR10_BMODE BIT(28) 163 #define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 164 #endif 165 166 /* address translation table */ 167 struct rproc_att { 168 u32 da; /* device address (From Cortex M4 view) */ 169 u32 sa; /* system bus address */ 170 u32 size; /* size of reg range */ 171 }; 172 173 const struct rproc_att *imx_bootaux_get_hostmap(void); 174 175 struct rom_api { 176 u16 ver; 177 u16 tag; 178 u32 reserved1; 179 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor); 180 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor); 181 }; 182 183 enum boot_dev_type_e { 184 BT_DEV_TYPE_SD = 1, 185 BT_DEV_TYPE_MMC = 2, 186 BT_DEV_TYPE_NAND = 3, 187 BT_DEV_TYPE_FLEXSPINOR = 4, 188 BT_DEV_TYPE_SPI_NOR = 6, 189 190 BT_DEV_TYPE_USB = 0xE, 191 BT_DEV_TYPE_MEM_DEV = 0xF, 192 193 BT_DEV_TYPE_INVALID = 0xFF 194 }; 195 196 enum boot_stage_type { 197 BT_STAGE_PRIMARY = 0x6, 198 BT_STAGE_SECONDARY = 0x9, 199 BT_STAGE_RECOVERY = 0xa, 200 BT_STAGE_USB = 0x5, 201 }; 202 203 #define QUERY_ROM_VER 1 204 #define QUERY_BT_DEV 2 205 #define QUERY_PAGE_SZ 3 206 #define QUERY_IVT_OFF 4 207 #define QUERY_BT_STAGE 5 208 #define QUERY_IMG_OFF 6 209 210 #define ROM_API_OKAY 0xF0 211 212 extern struct rom_api *g_rom_api; 213 extern unsigned long rom_pointer[]; 214 215 ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf); 216 ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev); 217 218 u32 rom_api_download_image(u8 *dest, u32 offset, u32 size); 219 u32 rom_api_query_boot_infor(u32 info_type, u32 *info); 220 221 #if IS_ENABLED(CONFIG_SCMI_FIRMWARE) 222 typedef struct rom_passover { 223 u16 tag; // Tag 224 u8 len; // Fixed value of 0x80 225 u8 ver; // Version 226 u32 boot_mode; // Boot mode 227 u32 card_addr_mode; // SD card address mode 228 u32 bad_blks_of_img_set0; // NAND bad block count skipped 1 229 u32 ap_mu_id; // AP MU ID 230 u32 bad_blks_of_img_set1; // NAND bad block count skipped 1 231 u8 boot_stage; // Boot stage 232 u8 img_set_sel; // Image set booted from 233 u8 rsv0[2]; // Reserved 234 u32 img_set_end; // Offset of Image End 235 u32 rom_version; // ROM version 236 u8 boot_dev_state; // Boot device state 237 u8 boot_dev_inst; // Boot device type 238 u8 boot_dev_type; // Boot device instance 239 u8 rsv1; // Reserved 240 u32 dev_page_size; // Boot device page size 241 u32 cnt_header_ofs; // Container header offset 242 u32 img_ofs; // Image offset 243 } __packed rom_passover_t; 244 245 /** 246 * struct scmi_rom_passover_out - Response payload for ROM_PASSOVER_GET command 247 * @status: SCMI clock ID 248 * @attributes: Attributes of the targets clock state 249 */ 250 struct scmi_rom_passover_get_out { 251 u32 status; 252 u32 numPassover; 253 u32 passover[(sizeof(rom_passover_t) + 8) / 4]; 254 }; 255 256 #endif 257 258 /* For i.MX ULP */ 259 #define BT0CFG_LPBOOT_MASK 0x1 260 #define BT0CFG_DUALBOOT_MASK 0x2 261 262 enum bt_mode { 263 LOW_POWER_BOOT, /* LP_BT = 1 */ 264 DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ 265 SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ 266 }; 267 268 u32 get_nr_cpus(void); 269 u32 get_cpu_rev(void); 270 u32 get_cpu_speed_grade_hz(void); 271 u32 get_cpu_temp_grade(int *minc, int *maxc); 272 const char *get_imx_type(u32 imxtype); 273 u32 imx_ddr_size(void); 274 void sdelay(unsigned long); 275 void set_chipselect_size(int const); 276 277 void init_aips(void); 278 void init_src(void); 279 void init_snvs(void); 280 void imx_wdog_disable_powerdown(void); 281 282 void board_mem_get_layout(u64 *phys_sdram_1_start, 283 u64 *phys_sdram_1_size, 284 u64 *phys_sdram_2_start, 285 u64 *phys_sdram_2_size); 286 287 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data); 288 int arch_auxiliary_core_check_up(u32 core_id); 289 290 int board_mmc_get_env_dev(int devno); 291 292 int nxp_board_rev(void); 293 char nxp_board_rev_string(void); 294 295 /* 296 * Initializes on-chip ethernet controllers. 297 * to override, implement board_eth_init() 298 */ 299 int fecmxc_initialize(struct bd_info *bis); 300 u32 get_ahb_clk(void); 301 u32 get_periph_clk(void); 302 303 void lcdif_power_down(void); 304 305 int mxs_reset_block(struct mxs_register_32 *reg); 306 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); 307 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); 308 309 void board_late_mmc_env_init(void); 310 311 unsigned long call_imx_sip(unsigned long id, unsigned long reg0, 312 unsigned long reg1, unsigned long reg2, 313 unsigned long reg3); 314 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, 315 unsigned long *reg1, unsigned long reg2, 316 unsigned long reg3); 317 318 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 319 320 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) 321 void enable_ca7_smp(void); 322 #endif 323 324 enum boot_device get_boot_device(void); 325 326 int disable_cpu_nodes(void *blob, const char * const *nodes_path, 327 u32 num_disabled_cores, u32 max_cores); 328 int fixup_thermal_trips(void *blob, const char *name); 329 #endif 330