1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Cadence DDR Driver
4 *
5 * Copyright (C) 2012-2022 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9 #include <errno.h>
10
11 #include "cps_drv_lpddr4.h"
12 #include "lpddr4_if.h"
13 #include "lpddr4.h"
14 #include "lpddr4_structs_if.h"
15
16 static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
17 static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
18 static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
19 static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval);
20 static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
21 static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
22 static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
23 static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
24 static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits);
25 static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
26 static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
27 static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
28 static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
29 static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
30 static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
31 static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
32 static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
33 static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
34 static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
35 static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
36 static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
37 static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
38 static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
39 static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
40 static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
41 static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
42 static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
43 static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
44 static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
45 static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
46 static u32 lpddr4_getphyrwmask(u32 regoffset);
47
lpddr4_pollctlirq(const lpddr4_privatedata * pd,lpddr4_intr_ctlinterrupt irqbit,u32 delay)48 u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
49 {
50 u32 result = 0U;
51 u32 timeout = 0U;
52 bool irqstatus = false;
53
54 do {
55 if (++timeout == delay) {
56 result = (u32)EIO;
57 break;
58 }
59 result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
60 } while ((irqstatus == (bool)false) && (result == (u32)0));
61
62 return result;
63 }
64
lpddr4_pollphyindepirq(const lpddr4_privatedata * pd,lpddr4_intr_phyindepinterrupt irqbit,u32 delay)65 static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay)
66 {
67 u32 result = 0U;
68 u32 timeout = 0U;
69 bool irqstatus = false;
70
71 do {
72 if (++timeout == delay) {
73 result = (u32)EIO;
74 break;
75 }
76 result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
77 } while ((irqstatus == (bool)false) && (result == (u32)0));
78
79 return result;
80 }
81
lpddr4_pollandackirq(const lpddr4_privatedata * pd)82 static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd)
83 {
84 u32 result = 0U;
85
86 result = lpddr4_pollphyindepirq(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT, LPDDR4_CUSTOM_TIMEOUT_DELAY);
87
88 if (result == (u32)0)
89 result = lpddr4_ackphyindepinterrupt(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT);
90 if (result == (u32)0)
91 result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MC_INIT_DONE, LPDDR4_CUSTOM_TIMEOUT_DELAY);
92 if (result == (u32)0)
93 result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MC_INIT_DONE);
94 return result;
95 }
96
lpddr4_startsequencecontroller(const lpddr4_privatedata * pd)97 static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd)
98 {
99 u32 result = 0U;
100 u32 regval = 0U;
101 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
102 lpddr4_infotype infotype;
103
104 regval = CPS_FLD_SET(LPDDR4__PI_START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
105 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
106
107 regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
108 CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
109
110 if (pd->infohandler != (lpddr4_infocallback)NULL) {
111 infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
112 pd->infohandler(pd, infotype);
113 }
114
115 result = lpddr4_pollandackirq(pd);
116
117 return result;
118 }
119
lpddr4_addoffset(volatile u32 * addr,u32 regoffset)120 volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset)
121 {
122 volatile u32 *local_addr = addr;
123 volatile u32 *regaddr = &local_addr[regoffset];
124
125 return regaddr;
126 }
127
lpddr4_probe(const lpddr4_config * config,u16 * configsize)128 u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize)
129 {
130 u32 result;
131
132 result = (u32)(lpddr4_probesf(config, configsize));
133 if (result == (u32)0)
134 *configsize = (u16)(sizeof(lpddr4_privatedata));
135 return result;
136 }
137
lpddr4_init(lpddr4_privatedata * pd,const lpddr4_config * cfg)138 u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg)
139 {
140 u32 result = 0U;
141
142 result = lpddr4_initsf(pd, cfg);
143 if (result == (u32)0) {
144 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)cfg->ctlbase;
145 pd->ctlbase = ctlregbase;
146 pd->infohandler = (lpddr4_infocallback)cfg->infohandler;
147 pd->ctlinterrupthandler = (lpddr4_ctlcallback)cfg->ctlinterrupthandler;
148 pd->phyindepinterrupthandler = (lpddr4_phyindepcallback)cfg->phyindepinterrupthandler;
149 }
150 return result;
151 }
152
lpddr4_start(const lpddr4_privatedata * pd)153 u32 lpddr4_start(const lpddr4_privatedata *pd)
154 {
155 u32 result = 0U;
156
157 result = lpddr4_startsf(pd);
158 if (result == (u32)0)
159 result = lpddr4_enablepiinitiator(pd);
160 if (result == (u32)0)
161 result = lpddr4_startsequencecontroller(pd);
162
163 return result;
164 }
165
lpddr4_readreg(const lpddr4_privatedata * pd,lpddr4_regblock cpp,u32 regoffset,u32 * regvalue)166 u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue)
167 {
168 u32 result = 0U;
169
170 result = lpddr4_readregsf(pd, cpp, regvalue);
171 if (result == (u32)0) {
172 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
173
174 if (cpp == LPDDR4_CTL_REGS) {
175 if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
176 result = (u32)EINVAL;
177 else
178 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset));
179 } else if (cpp == LPDDR4_PHY_REGS) {
180 if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
181 result = (u32)EINVAL;
182 else
183 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset));
184
185 } else {
186 if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
187 result = (u32)EINVAL;
188 else
189 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset));
190 }
191 }
192 return result;
193 }
194
lpddr4_getphyrwmask(u32 regoffset)195 static u32 lpddr4_getphyrwmask(u32 regoffset)
196 {
197 u32 rwmask = 0U;
198 u32 arrayoffset = 0U;
199 u32 slicenum, sliceoffset = 0U;
200
201 for (slicenum = (u32)0U; slicenum <= (DSLICE_NUM + ASLICE_NUM); slicenum++) {
202 sliceoffset = sliceoffset + (u32)SLICE_WIDTH;
203 if (regoffset < sliceoffset)
204 break;
205 }
206 arrayoffset = regoffset - (sliceoffset - (u32)SLICE_WIDTH);
207
208 if (slicenum < DSLICE_NUM) {
209 rwmask = lpddr4_getdslicemask(slicenum, arrayoffset);
210 } else {
211 if (slicenum == DSLICE_NUM) {
212 if (arrayoffset < ASLICE0_REG_COUNT)
213 rwmask = g_lpddr4_address_slice_0_rw_mask[arrayoffset];
214 } else {
215 if (arrayoffset < PHY_CORE_REG_COUNT)
216 rwmask = g_lpddr4_phy_core_rw_mask[arrayoffset];
217 }
218 }
219 return rwmask;
220 }
221
lpddr4_deferredregverify(const lpddr4_privatedata * pd,lpddr4_regblock cpp,u32 regvalues[],u16 regnum[],u16 regcount)222 u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount)
223 {
224 u32 result = (u32)0;
225 u32 aindex;
226 u32 regreadval = 0U;
227 u32 rwmask = 0U;
228
229 result = lpddr4_deferredregverifysf(pd, cpp);
230
231 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
232 result = EINVAL;
233 if (result == (u32)0) {
234 for (aindex = 0; aindex < regcount; aindex++) {
235 result = lpddr4_readreg(pd, cpp, (u32)regnum[aindex], ®readval);
236
237 if (result == (u32)0) {
238 switch (cpp) {
239 case LPDDR4_PHY_INDEP_REGS:
240 rwmask = g_lpddr4_pi_rw_mask[(u32)regnum[aindex]];
241 break;
242 case LPDDR4_PHY_REGS:
243 rwmask = lpddr4_getphyrwmask((u32)regnum[aindex]);
244 break;
245 default:
246 rwmask = g_lpddr4_ddr_controller_rw_mask[(u32)regnum[aindex]];
247 break;
248 }
249
250 if ((rwmask & regreadval) != ((u32)(regvalues[aindex]) & rwmask)) {
251 result = EIO;
252 break;
253 }
254 }
255 }
256 }
257 return result;
258 }
259
lpddr4_writereg(const lpddr4_privatedata * pd,lpddr4_regblock cpp,u32 regoffset,u32 regvalue)260 u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
261 {
262 u32 result = 0U;
263
264 result = lpddr4_writeregsf(pd, cpp);
265 if (result == (u32)0) {
266 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
267
268 if (cpp == LPDDR4_CTL_REGS) {
269 if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
270 result = (u32)EINVAL;
271 else
272 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset), regvalue);
273 } else if (cpp == LPDDR4_PHY_REGS) {
274 if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
275 result = (u32)EINVAL;
276 else
277 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset), regvalue);
278 } else {
279 if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
280 result = (u32)EINVAL;
281 else
282 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
283 }
284 }
285
286 return result;
287 }
288
lpddr4_getmmrregister(const lpddr4_privatedata * pd,u32 readmoderegval,u64 * mmrvalue,u8 * mmrstatus)289 u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus)
290 {
291 u32 result = 0U;
292 u32 tdelay = 1000U;
293 u32 regval = 0U;
294
295 result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
296 if (result == (u32)0) {
297 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
298
299 regval = CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__READ_MODEREG__REG)), readmoderegval);
300 CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
301
302 result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_READ_DONE, tdelay);
303 }
304 if (result == (u32)0)
305 result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
306 return result;
307 }
308
lpddr4_writemmrregister(const lpddr4_privatedata * pd,u32 writemoderegval)309 static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval)
310 {
311 u32 result = (u32)0;
312 u32 tdelay = 1000U;
313 u32 regval = 0U;
314 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
315
316 regval = CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG)), writemoderegval);
317 CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
318
319 result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_WRITE_DONE, tdelay);
320
321 return result;
322 }
323
lpddr4_setmmrregister(const lpddr4_privatedata * pd,u32 writemoderegval,u8 * mrwstatus)324 u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus)
325 {
326 u32 result = 0U;
327
328 result = lpddr4_setmmrregistersf(pd, mrwstatus);
329 if (result == (u32)0) {
330 result = lpddr4_writemmrregister(pd, writemoderegval);
331
332 if (result == (u32)0)
333 result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_WRITE_DONE);
334 if (result == (u32)0) {
335 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
336 *mrwstatus = (u8)CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRW_STATUS__REG)));
337 if ((*mrwstatus) != 0U)
338 result = (u32)EIO;
339 }
340 }
341
342 return result;
343 }
344
lpddr4_writectlconfig(const lpddr4_privatedata * pd,u32 regvalues[],u16 regnum[],u16 regcount)345 u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
346 {
347 u32 result;
348 u32 aindex;
349
350 result = lpddr4_writectlconfigsf(pd);
351 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
352 result = EINVAL;
353
354 if (result == (u32)0) {
355 for (aindex = 0; aindex < regcount; aindex++)
356 result = (u32)lpddr4_writereg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
357 (u32)regvalues[aindex]);
358 }
359 return result;
360 }
361
lpddr4_writephyindepconfig(const lpddr4_privatedata * pd,u32 regvalues[],u16 regnum[],u16 regcount)362 u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
363 {
364 u32 result;
365 u32 aindex;
366
367 result = lpddr4_writephyindepconfigsf(pd);
368 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
369 result = EINVAL;
370 if (result == (u32)0) {
371 for (aindex = 0; aindex < regcount; aindex++)
372 result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
373 (u32)regvalues[aindex]);
374 }
375 return result;
376 }
377
lpddr4_writephyconfig(const lpddr4_privatedata * pd,u32 regvalues[],u16 regnum[],u16 regcount)378 u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
379 {
380 u32 result;
381 u32 aindex;
382
383 result = lpddr4_writephyconfigsf(pd);
384 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
385 result = EINVAL;
386 if (result == (u32)0) {
387 for (aindex = 0; aindex < regcount; aindex++)
388 result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
389 (u32)regvalues[aindex]);
390 }
391 return result;
392 }
393
lpddr4_readctlconfig(const lpddr4_privatedata * pd,u32 regvalues[],u16 regnum[],u16 regcount)394 u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
395 {
396 u32 result;
397 u32 aindex;
398
399 result = lpddr4_readctlconfigsf(pd);
400 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
401 result = EINVAL;
402 if (result == (u32)0) {
403 for (aindex = 0; aindex < regcount; aindex++)
404 result = (u32)lpddr4_readreg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
405 (u32 *)(®values[aindex]));
406 }
407 return result;
408 }
409
lpddr4_readphyindepconfig(const lpddr4_privatedata * pd,u32 regvalues[],u16 regnum[],u16 regcount)410 u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
411 {
412 u32 result;
413 u32 aindex;
414
415 result = lpddr4_readphyindepconfigsf(pd);
416 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
417 result = EINVAL;
418 if (result == (u32)0) {
419 for (aindex = 0; aindex < regcount; aindex++)
420 result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
421 (u32 *)(®values[aindex]));
422 }
423 return result;
424 }
425
lpddr4_readphyconfig(const lpddr4_privatedata * pd,u32 regvalues[],u16 regnum[],u16 regcount)426 u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
427 {
428 u32 result;
429 u32 aindex;
430
431 result = lpddr4_readphyconfigsf(pd);
432 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
433 result = EINVAL;
434 if (result == (u32)0) {
435 for (aindex = 0; aindex < regcount; aindex++)
436 result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
437 (u32 *)(®values[aindex]));
438 }
439 return result;
440 }
441
lpddr4_getphyindepinterruptmask(const lpddr4_privatedata * pd,u32 * mask)442 u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask)
443 {
444 u32 result;
445
446 result = lpddr4_getphyindepinterruptmsf(pd, mask);
447 if (result == (u32)0) {
448 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
449 *mask = CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)));
450 }
451 return result;
452 }
453
lpddr4_setphyindepinterruptmask(const lpddr4_privatedata * pd,const u32 * mask)454 u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask)
455 {
456 u32 result;
457 u32 regval = 0;
458 const u32 ui32irqcount = (u32)LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
459
460 result = lpddr4_setphyindepinterruptmsf(pd, mask);
461 if ((result == (u32)0) && (ui32irqcount < WORD_SHIFT)) {
462 if (*mask >= (1U << ui32irqcount))
463 result = (u32)EINVAL;
464 }
465 if (result == (u32)0) {
466 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
467
468 regval = CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)), *mask);
469 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
470 }
471 return result;
472 }
473
lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,lpddr4_intr_phyindepinterrupt intr,bool * irqstatus)474 u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus)
475 {
476 u32 result = 0;
477 u32 phyindepirqstatus = 0;
478
479 result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus);
480 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
481 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
482
483 phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
484 *irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U);
485 }
486 return result;
487 }
488
lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,lpddr4_intr_phyindepinterrupt intr)489 u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr)
490 {
491 u32 result = 0U;
492 u32 regval = 0U;
493
494 result = LPDDR4_INTR_AckPhyIndepIntSF(pd, intr);
495 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
496 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
497
498 regval = ((u32)LPDDR4_BIT_MASK << (u32)intr);
499 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
500 }
501
502 return result;
503 }
504
lpddr4_checkcatrainingerror(lpddr4_ctlregs * ctlregbase,lpddr4_debuginfo * debuginfo,bool * errfoundptr)505 static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
506 {
507 u32 regval;
508 u32 errbitmask = 0U;
509 u32 snum;
510 volatile u32 *regaddress;
511
512 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
513 errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
514 for (snum = 0U; snum < ASLICE_NUM; snum++) {
515 regval = CPS_REG_READ(regaddress);
516 if ((regval & errbitmask) != CA_TRAIN_RL) {
517 debuginfo->catraingerror = CDN_TRUE;
518 *errfoundptr = true;
519 }
520 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
521 }
522 }
523
lpddr4_checkgatelvlerror(lpddr4_ctlregs * ctlregbase,lpddr4_debuginfo * debuginfo,bool * errfoundptr)524 static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
525 {
526 u32 regval;
527 u32 errbitmask = 0U;
528 u32 snum;
529 volatile u32 *regaddress;
530
531 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
532 errbitmask = GATE_LVL_ERROR_FIELDS;
533 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
534 regval = CPS_REG_READ(regaddress);
535 if ((regval & errbitmask) != 0U) {
536 debuginfo->gatelvlerror = CDN_TRUE;
537 *errfoundptr = true;
538 }
539 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
540 }
541 }
542
lpddr4_checkreadlvlerror(lpddr4_ctlregs * ctlregbase,lpddr4_debuginfo * debuginfo,bool * errfoundptr)543 static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
544 {
545 u32 regval;
546 u32 errbitmask = 0U;
547 u32 snum;
548 volatile u32 *regaddress;
549
550 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
551 errbitmask = READ_LVL_ERROR_FIELDS;
552 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
553 regval = CPS_REG_READ(regaddress);
554 if ((regval & errbitmask) != 0U) {
555 debuginfo->readlvlerror = CDN_TRUE;
556 *errfoundptr = true;
557 }
558 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
559 }
560 }
561
lpddr4_checkdqtrainingerror(lpddr4_ctlregs * ctlregbase,lpddr4_debuginfo * debuginfo,bool * errfoundptr)562 static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
563 {
564 u32 regval;
565 u32 errbitmask = 0U;
566 u32 snum;
567 volatile u32 *regaddress;
568
569 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
570 errbitmask = DQ_LVL_STATUS;
571 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
572 regval = CPS_REG_READ(regaddress);
573 if ((regval & errbitmask) != 0U) {
574 debuginfo->dqtrainingerror = CDN_TRUE;
575 *errfoundptr = true;
576 }
577 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
578 }
579 }
580
lpddr4_checklvlerrors(const lpddr4_privatedata * pd,lpddr4_debuginfo * debuginfo,bool errfound)581 bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound)
582 {
583 bool localerrfound = errfound;
584
585 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
586
587 if (localerrfound == (bool)false)
588 lpddr4_checkcatrainingerror(ctlregbase, debuginfo, &localerrfound);
589
590 if (localerrfound == (bool)false)
591 lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
592
593 if (localerrfound == (bool)false)
594 lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
595
596 if (localerrfound == (bool)false)
597 lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
598
599 if (localerrfound == (bool)false)
600 lpddr4_checkdqtrainingerror(ctlregbase, debuginfo, &localerrfound);
601 return localerrfound;
602 }
603
lpddr4_seterror(volatile u32 * reg,u32 errbitmask,u8 * errfoundptr,const u32 errorinfobits)604 static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits)
605 {
606 u32 regval = 0U;
607
608 regval = CPS_REG_READ(reg);
609 if ((regval & errbitmask) != errorinfobits)
610 *errfoundptr = CDN_TRUE;
611 return *errfoundptr;
612 }
613
lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,lpddr4_debuginfo * debuginfo,u8 * errfoundptr)614 void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr)
615 {
616 u32 errbitmask = (LPDDR4_BIT_MASK << 0x1U) | (LPDDR4_BIT_MASK);
617
618 debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
619 errbitmask, errfoundptr, PLL_READY);
620 if (*errfoundptr == CDN_FALSE)
621 debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
622 errbitmask, errfoundptr, PLL_READY);
623
624 if (*errfoundptr == CDN_FALSE)
625 debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
626 IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
627 if (*errfoundptr == CDN_FALSE)
628 debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
629 IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
630 if (*errfoundptr == CDN_FALSE)
631 debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
632 IO_CALIB_FIELD, errfoundptr, IO_CALIB_STATE);
633 }
634
lpddr4_setphysnapsettings(lpddr4_ctlregs * ctlregbase,const bool errorfound)635 static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
636 {
637 u32 snum = 0U;
638 volatile u32 *regaddress;
639 u32 regval = 0U;
640
641 if (errorfound == (bool)false) {
642 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
643 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
644 regval = CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
645 CPS_REG_WRITE(regaddress, regval);
646 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
647 }
648 }
649 }
650
lpddr4_setphyadrsnapsettings(lpddr4_ctlregs * ctlregbase,const bool errorfound)651 static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
652 {
653 u32 snum = 0U;
654 volatile u32 *regaddress;
655 u32 regval = 0U;
656
657 if (errorfound == (bool)false) {
658 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
659 for (snum = (u32)0U; snum < ASLICE_NUM; snum++) {
660 regval = CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
661 CPS_REG_WRITE(regaddress, regval);
662 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
663 }
664 }
665 }
666
lpddr4_setsettings(lpddr4_ctlregs * ctlregbase,const bool errorfound)667 void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
668 {
669 lpddr4_setphysnapsettings(ctlregbase, errorfound);
670 lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
671 }
672
readpdwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,u32 * cycles)673 static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
674 {
675 if (*fspnum == LPDDR4_FSP_0)
676 *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)));
677 else if (*fspnum == LPDDR4_FSP_1)
678 *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)));
679 else
680 *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)));
681 }
682
readsrshortwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,u32 * cycles)683 static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
684 {
685 if (*fspnum == LPDDR4_FSP_0)
686 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
687 else if (*fspnum == LPDDR4_FSP_1)
688 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
689 else
690 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
691 }
692
readsrlongwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,u32 * cycles)693 static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
694 {
695 if (*fspnum == LPDDR4_FSP_0)
696 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
697 else if (*fspnum == LPDDR4_FSP_1)
698 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
699 else
700 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
701 }
702
readsrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,u32 * cycles)703 static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
704 {
705 if (*fspnum == LPDDR4_FSP_0)
706 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
707 else if (*fspnum == LPDDR4_FSP_1)
708 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
709 else
710 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
711 }
712
readsrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,u32 * cycles)713 static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
714 {
715 if (*fspnum == LPDDR4_FSP_0)
716 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
717 else if (*fspnum == LPDDR4_FSP_1)
718 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
719 else
720 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
721 }
722
readsrdplongwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,u32 * cycles)723 static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
724 {
725 if (*fspnum == LPDDR4_FSP_0)
726 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
727 else if (*fspnum == LPDDR4_FSP_1)
728 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
729 else
730 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
731 }
732
readsrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,u32 * cycles)733 static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
734 {
735 if (*fspnum == LPDDR4_FSP_0)
736 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
737 else if (*fspnum == LPDDR4_FSP_1)
738 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
739 else
740 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
741
742 }
743
lpddr4_readlpiwakeuptime(lpddr4_ctlregs * ctlregbase,const lpddr4_lpiwakeupparam * lpiwakeupparam,const lpddr4_ctlfspnum * fspnum,u32 * cycles)744 static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
745 {
746 if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
747 readpdwakeup(fspnum, ctlregbase, cycles);
748 else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
749 readsrshortwakeup(fspnum, ctlregbase, cycles);
750 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
751 readsrlongwakeup(fspnum, ctlregbase, cycles);
752 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
753 readsrlonggatewakeup(fspnum, ctlregbase, cycles);
754 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
755 readsrdpshortwakeup(fspnum, ctlregbase, cycles);
756 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
757 readsrdplongwakeup(fspnum, ctlregbase, cycles);
758 else
759 readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
760 }
761
lpddr4_getlpiwakeuptime(const lpddr4_privatedata * pd,const lpddr4_lpiwakeupparam * lpiwakeupparam,const lpddr4_ctlfspnum * fspnum,u32 * cycles)762 u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
763 {
764 u32 result = 0U;
765
766 result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
767 if (result == (u32)0) {
768 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
769 lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
770 }
771 return result;
772 }
773
writepdwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,const u32 * cycles)774 static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
775 {
776 u32 regval = 0U;
777
778 if (*fspnum == LPDDR4_FSP_0) {
779 regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)), *cycles);
780 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), regval);
781 } else if (*fspnum == LPDDR4_FSP_1) {
782 regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)), *cycles);
783 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), regval);
784 } else {
785 regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)), *cycles);
786 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), regval);
787 }
788 }
789
writesrshortwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,const u32 * cycles)790 static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
791 {
792 u32 regval = 0U;
793
794 if (*fspnum == LPDDR4_FSP_0) {
795 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)), *cycles);
796 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG), regval);
797 } else if (*fspnum == LPDDR4_FSP_1) {
798 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)), *cycles);
799 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG), regval);
800 } else {
801 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)), *cycles);
802 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG), regval);
803 }
804 }
805
writesrlongwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,const u32 * cycles)806 static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
807 {
808 u32 regval = 0U;
809
810 if (*fspnum == LPDDR4_FSP_0) {
811 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)), *cycles);
812 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), regval);
813 } else if (*fspnum == LPDDR4_FSP_1) {
814 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)), *cycles);
815 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), regval);
816 } else {
817 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)), *cycles);
818 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), regval);
819 }
820 }
821
writesrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,const u32 * cycles)822 static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
823 {
824 u32 regval = 0U;
825
826 if (*fspnum == LPDDR4_FSP_0) {
827 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
828 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
829 } else if (*fspnum == LPDDR4_FSP_1) {
830 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
831 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
832 } else {
833 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
834 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
835 }
836 }
837
writesrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,const u32 * cycles)838 static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
839 {
840 u32 regval = 0U;
841
842 if (*fspnum == LPDDR4_FSP_0) {
843 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)), *cycles);
844 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
845 } else if (*fspnum == LPDDR4_FSP_1) {
846 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)), *cycles);
847 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
848 } else {
849 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)), *cycles);
850 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
851 }
852 }
853
writesrdplongwakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,const u32 * cycles)854 static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
855 {
856 u32 regval = 0U;
857
858 if (*fspnum == LPDDR4_FSP_0) {
859 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)), *cycles);
860 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
861 } else if (*fspnum == LPDDR4_FSP_1) {
862 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)), *cycles);
863 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
864 } else {
865 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)), *cycles);
866 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
867 }
868 }
writesrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,lpddr4_ctlregs * ctlregbase,const u32 * cycles)869 static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
870 {
871 u32 regval = 0U;
872
873 if (*fspnum == LPDDR4_FSP_0) {
874 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
875 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
876 } else if (*fspnum == LPDDR4_FSP_1) {
877 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
878 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
879 } else {
880 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
881 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
882 }
883 }
884
lpddr4_writelpiwakeuptime(lpddr4_ctlregs * ctlregbase,const lpddr4_lpiwakeupparam * lpiwakeupparam,const lpddr4_ctlfspnum * fspnum,const u32 * cycles)885 static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
886 {
887 if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
888 writepdwakeup(fspnum, ctlregbase, cycles);
889 else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
890 writesrshortwakeup(fspnum, ctlregbase, cycles);
891 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
892 writesrlongwakeup(fspnum, ctlregbase, cycles);
893 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
894 writesrlonggatewakeup(fspnum, ctlregbase, cycles);
895 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
896 writesrdpshortwakeup(fspnum, ctlregbase, cycles);
897 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
898 writesrdplongwakeup(fspnum, ctlregbase, cycles);
899 else
900 writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
901 }
902
lpddr4_setlpiwakeuptime(const lpddr4_privatedata * pd,const lpddr4_lpiwakeupparam * lpiwakeupparam,const lpddr4_ctlfspnum * fspnum,const u32 * cycles)903 u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
904 {
905 u32 result = 0U;
906
907 result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
908 if (result == (u32)0) {
909 if (*cycles > NIBBLE_MASK)
910 result = (u32)EINVAL;
911 }
912 if (result == (u32)0) {
913 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
914 lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
915 }
916 return result;
917 }
918
lpddr4_getdbireadmode(const lpddr4_privatedata * pd,bool * on_off)919 u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off)
920 {
921 u32 result = 0U;
922
923 result = lpddr4_getdbireadmodesf(pd, on_off);
924
925 if (result == (u32)0) {
926 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
927 if (CPS_FLD_READ(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) == 0U)
928 *on_off = false;
929 else
930 *on_off = true;
931 }
932 return result;
933 }
934
lpddr4_getdbiwritemode(const lpddr4_privatedata * pd,bool * on_off)935 u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off)
936 {
937 u32 result = 0U;
938
939 result = lpddr4_getdbireadmodesf(pd, on_off);
940
941 if (result == (u32)0) {
942 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
943 if (CPS_FLD_READ(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) == 0U)
944 *on_off = false;
945 else
946 *on_off = true;
947 }
948 return result;
949 }
950
lpddr4_setdbimode(const lpddr4_privatedata * pd,const lpddr4_dbimode * mode)951 u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
952 {
953 u32 result = 0U;
954 u32 regval = 0U;
955
956 result = lpddr4_setdbimodesf(pd, mode);
957
958 if (result == (u32)0) {
959 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
960
961 if (*mode == LPDDR4_DBI_RD_ON)
962 regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 1U);
963 else if (*mode == LPDDR4_DBI_RD_OFF)
964 regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 0U);
965 else if (*mode == LPDDR4_DBI_WR_ON)
966 regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 1U);
967 else
968 regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 0U);
969 CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
970 }
971 return result;
972 }
973
lpddr4_getrefreshrate(const lpddr4_privatedata * pd,const lpddr4_ctlfspnum * fspnum,u32 * tref,u32 * tras_max)974 u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max)
975 {
976 u32 result = 0U;
977
978 result = lpddr4_getrefreshratesf(pd, fspnum, tref, tras_max);
979
980 if (result == (u32)0) {
981 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
982
983 switch (*fspnum) {
984 case LPDDR4_FSP_2:
985 *tref = CPS_FLD_READ(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)));
986 *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)));
987 break;
988 case LPDDR4_FSP_1:
989 *tref = CPS_FLD_READ(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)));
990 *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)));
991 break;
992 default:
993 *tref = CPS_FLD_READ(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)));
994 *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)));
995 break;
996 }
997 }
998 return result;
999 }
1000
lpddr4_updatefsp2refrateparams(const lpddr4_privatedata * pd,const u32 * tref,const u32 * tras_max)1001 static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
1002 {
1003 u32 regval = 0U;
1004 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1005
1006 regval = CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)), *tref);
1007 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), regval);
1008 regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)), *tras_max);
1009 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG), regval);
1010 }
1011
lpddr4_updatefsp1refrateparams(const lpddr4_privatedata * pd,const u32 * tref,const u32 * tras_max)1012 static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
1013 {
1014 u32 regval = 0U;
1015 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1016
1017 regval = CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)), *tref);
1018 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), regval);
1019 regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)), *tras_max);
1020 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG), regval);;
1021 }
1022
lpddr4_updatefsp0refrateparams(const lpddr4_privatedata * pd,const u32 * tref,const u32 * tras_max)1023 static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
1024 {
1025 u32 regval = 0U;
1026 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1027
1028 regval = CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)), *tref);
1029 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), regval);
1030 regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)), *tras_max);
1031 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG), regval);
1032 }
1033
lpddr4_setrefreshrate(const lpddr4_privatedata * pd,const lpddr4_ctlfspnum * fspnum,const u32 * tref,const u32 * tras_max)1034 u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
1035 {
1036 u32 result = 0U;
1037
1038 result = lpddr4_setrefreshratesf(pd, fspnum, tref, tras_max);
1039
1040 if (result == (u32)0) {
1041 switch (*fspnum) {
1042 case LPDDR4_FSP_2:
1043 lpddr4_updatefsp2refrateparams(pd, tref, tras_max);
1044 break;
1045 case LPDDR4_FSP_1:
1046 lpddr4_updatefsp1refrateparams(pd, tref, tras_max);
1047 break;
1048 default:
1049 lpddr4_updatefsp0refrateparams(pd, tref, tras_max);
1050 break;
1051 }
1052 }
1053 return result;
1054 }
1055
lpddr4_refreshperchipselect(const lpddr4_privatedata * pd,const u32 trefinterval)1056 u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval)
1057 {
1058 u32 result = 0U;
1059 u32 regval = 0U;
1060
1061 result = lpddr4_refreshperchipselectsf(pd);
1062
1063 if (result == (u32)0) {
1064 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1065 regval = CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG)), trefinterval);
1066 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), regval);
1067 }
1068 return result;
1069 }
1070