1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <asm/arch/device.h>
7 #include <asm/arch/msg_port.h>
8 #include <asm/arch/quark.h>
9
msg_port_setup(int op,int port,int reg)10 void msg_port_setup(int op, int port, int reg)
11 {
12 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
13 (((op) << 24) | ((port) << 16) |
14 (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
15 }
16
msg_port_read(u8 port,u32 reg)17 u32 msg_port_read(u8 port, u32 reg)
18 {
19 u32 value;
20
21 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
22 reg & 0xffffff00);
23 msg_port_setup(MSG_OP_READ, port, reg);
24 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
25
26 return value;
27 }
28
msg_port_write(u8 port,u32 reg,u32 value)29 void msg_port_write(u8 port, u32 reg, u32 value)
30 {
31 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
32 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
33 reg & 0xffffff00);
34 msg_port_setup(MSG_OP_WRITE, port, reg);
35 }
36
msg_port_alt_read(u8 port,u32 reg)37 u32 msg_port_alt_read(u8 port, u32 reg)
38 {
39 u32 value;
40
41 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
42 reg & 0xffffff00);
43 msg_port_setup(MSG_OP_ALT_READ, port, reg);
44 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
45
46 return value;
47 }
48
msg_port_alt_write(u8 port,u32 reg,u32 value)49 void msg_port_alt_write(u8 port, u32 reg, u32 value)
50 {
51 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
52 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
53 reg & 0xffffff00);
54 msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
55 }
56
msg_port_io_read(u8 port,u32 reg)57 u32 msg_port_io_read(u8 port, u32 reg)
58 {
59 u32 value;
60
61 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
62 reg & 0xffffff00);
63 msg_port_setup(MSG_OP_IO_READ, port, reg);
64 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
65
66 return value;
67 }
68
msg_port_io_write(u8 port,u32 reg,u32 value)69 void msg_port_io_write(u8 port, u32 reg, u32 value)
70 {
71 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
72 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
73 reg & 0xffffff00);
74 msg_port_setup(MSG_OP_IO_WRITE, port, reg);
75 }
76