1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2008
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 */
7
8 #ifndef _KWBIMAGE_H_
9 #define _KWBIMAGE_H_
10
11 #include <compiler.h>
12 #include <stdint.h>
13
14 #include <linux/compiler_attributes.h>
15
16 #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
17 #define MAX_TEMPBUF_LEN 32
18
19 /* NAND ECC Mode */
20 #define IBR_HDR_ECC_DEFAULT 0x00
21 #define IBR_HDR_ECC_FORCED_HAMMING 0x01
22 #define IBR_HDR_ECC_FORCED_RS 0x02
23 #define IBR_HDR_ECC_DISABLED 0x03
24
25 /* Boot Type - block ID */
26 #define IBR_HDR_I2C_ID 0x4D
27 #define IBR_HDR_SPI_ID 0x5A
28 #define IBR_HDR_NAND_ID 0x8B
29 #define IBR_HDR_SATA_ID 0x78
30 #define IBR_HDR_PEX_ID 0x9C
31 #define IBR_HDR_UART_ID 0x69
32 #define IBR_HDR_SDIO_ID 0xAE
33 #define IBR_DEF_ATTRIB 0x00
34
35 /* Structure of the main header, version 0 (Kirkwood, Dove) */
36 struct main_hdr_v0 {
37 uint8_t blockid; /* 0x0 */
38 uint8_t nandeccmode; /* 0x1 */
39 uint16_t nandpagesize; /* 0x2-0x3 */
40 uint32_t blocksize; /* 0x4-0x7 */
41 uint8_t version; /* 0x8 */
42 uint8_t rsvd1[3]; /* 0x9-0xB */
43 uint32_t srcaddr; /* 0xC-0xF */
44 uint32_t destaddr; /* 0x10-0x13 */
45 uint32_t execaddr; /* 0x14-0x17 */
46 uint8_t satapiomode; /* 0x18 */
47 uint8_t nandblocksize; /* 0x19 */
48 union {
49 uint8_t nandbadblklocation; /* 0x1A */
50 uint16_t ddrinitdelay; /* 0x1A-0x1B */
51 };
52 uint8_t rsvd2; /* 0x1C */
53 uint8_t bin; /* 0x1D */
54 uint8_t ext; /* 0x1E */
55 uint8_t checksum; /* 0x1F */
56 } __packed;
57
58 struct ext_hdr_v0_reg {
59 uint32_t raddr;
60 uint32_t rdata;
61 } __packed;
62
63 /* Structure of the extension header, version 0 (Kirkwood, Dove) */
64 struct ext_hdr_v0 {
65 /*
66 * Beware that extension header offsets specified in 88AP510 Functional
67 * Specifications are relative to the start of the main header, not to
68 * the start of the extension header itself.
69 */
70 uint32_t offset; /* 0x0-0x3 */
71 uint8_t rsvd1[8]; /* 0x4-0xB */
72 uint32_t enddelay; /* 0xC-0xF */
73 uint32_t match_addr; /* 0x10-0x13 */
74 uint32_t match_mask; /* 0x14-0x17 */
75 uint32_t match_value; /* 0x18-0x1B */
76 uint8_t ddrwritetype; /* 0x1C */
77 uint8_t ddrresetmpp; /* 0x1D */
78 uint8_t ddrclkenmpp; /* 0x1E */
79 uint8_t ddrinitdelay; /* 0x1F */
80 struct ext_hdr_v0_reg rcfg[55]; /* 0x20-0x1D7 */
81 uint8_t rsvd2[7]; /* 0x1D8-0x1DE */
82 uint8_t checksum; /* 0x1DF */
83 } __packed;
84
85 /* Structure of the binary code header, version 0 (Dove) */
86 struct bin_hdr_v0 {
87 uint32_t match_addr; /* 0x00-0x03 */
88 uint32_t match_mask; /* 0x04-0x07 */
89 uint32_t match_value; /* 0x08-0x0B */
90 uint32_t offset; /* 0x0C-0x0F */
91 uint32_t destaddr; /* 0x10-0x13 */
92 uint32_t size; /* 0x14-0x17 */
93 uint32_t execaddr; /* 0x18-0x1B */
94 uint32_t params[4]; /* 0x1C-0x2B */
95 uint8_t params_flags; /* 0x2C */
96 uint8_t rsvd1; /* 0x2D */
97 uint8_t rsvd2; /* 0x2E */
98 uint8_t checksum; /* 0x2F */
99 uint8_t code[2000]; /* 0x30-0x7FF */
100 } __packed;
101
102 /* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
103 struct main_hdr_v1 {
104 uint8_t blockid; /* 0x0 */
105 uint8_t flags; /* 0x1 */
106 uint16_t nandpagesize; /* 0x2-0x3 */
107 uint32_t blocksize; /* 0x4-0x7 */
108 uint8_t version; /* 0x8 */
109 uint8_t headersz_msb; /* 0x9 */
110 uint16_t headersz_lsb; /* 0xA-0xB */
111 uint32_t srcaddr; /* 0xC-0xF */
112 uint32_t destaddr; /* 0x10-0x13 */
113 uint32_t execaddr; /* 0x14-0x17 */
114 uint8_t options; /* 0x18 */
115 uint8_t nandblocksize; /* 0x19 */
116 uint8_t nandbadblklocation; /* 0x1A */
117 uint8_t reserved4; /* 0x1B */
118 uint16_t reserved5; /* 0x1C-0x1D */
119 uint8_t ext; /* 0x1E */
120 uint8_t checksum; /* 0x1F */
121 } __packed;
122
123 /*
124 * Main header options
125 */
126 #define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
127 #define MAIN_HDR_V1_OPT_BAUD_2400 0x1
128 #define MAIN_HDR_V1_OPT_BAUD_4800 0x2
129 #define MAIN_HDR_V1_OPT_BAUD_9600 0x3
130 #define MAIN_HDR_V1_OPT_BAUD_19200 0x4
131 #define MAIN_HDR_V1_OPT_BAUD_38400 0x5
132 #define MAIN_HDR_V1_OPT_BAUD_57600 0x6
133 #define MAIN_HDR_V1_OPT_BAUD_115200 0x7
134
135 /*
136 * Header for the optional headers, version 1 (Armada 370/XP/375/38x/39x)
137 */
138 struct opt_hdr_v1 {
139 uint8_t headertype;
140 uint8_t headersz_msb;
141 uint16_t headersz_lsb;
142 char data[0];
143 } __packed;
144
145 /*
146 * Public Key data in DER format
147 */
148 struct pubkey_der_v1 {
149 uint8_t key[524];
150 } __packed;
151
152 /*
153 * Signature (RSA 2048)
154 */
155 struct sig_v1 {
156 uint8_t sig[256];
157 } __packed;
158
159 /*
160 * Structure of secure header (Armada XP/375/38x/39x)
161 */
162 struct secure_hdr_v1 {
163 uint8_t headertype; /* 0x0 */
164 uint8_t headersz_msb; /* 0x1 */
165 uint16_t headersz_lsb; /* 0x2 - 0x3 */
166 uint32_t reserved1; /* 0x4 - 0x7 */
167 struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
168 uint8_t jtag_delay; /* 0x214 */
169 uint8_t reserved2; /* 0x215 */
170 uint16_t reserved3; /* 0x216 - 0x217 */
171 uint32_t boxid; /* 0x218 - 0x21B */
172 uint32_t flashid; /* 0x21C - 0x21F */
173 struct sig_v1 hdrsig; /* 0x220 - 0x31F */
174 struct sig_v1 imgsig; /* 0x320 - 0x41F */
175 struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
176 struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
177 uint8_t next; /* 0x25E0 */
178 uint8_t reserved4; /* 0x25E1 */
179 uint16_t reserved5; /* 0x25E2 - 0x25E3 */
180 } __packed;
181
182 /*
183 * Structure of register set
184 */
185 struct register_set_hdr_v1 {
186 uint8_t headertype; /* 0x0 */
187 uint8_t headersz_msb; /* 0x1 */
188 uint16_t headersz_lsb; /* 0x2 - 0x3 */
189 union {
190 struct {
191 uint32_t address; /* 0x4+8*N - 0x7+8*N */
192 uint32_t value; /* 0x8+8*N - 0xB+8*N */
193 } __packed entry;
194 struct {
195 uint8_t next; /* 0xC+8*N */
196 uint8_t delay; /* 0xD+8*N */
197 uint16_t reserved; /* 0xE+8*N - 0xF+8*N */
198 } __packed last_entry;
199 } data[];
200 } __packed;
201
202 /*
203 * Value 0 in register_set_hdr_v1 delay field is special.
204 * Instead of delay it setup SDRAM Controller.
205 */
206 #define REGISTER_SET_HDR_OPT_DELAY_SDRAM_SETUP 0
207 #define REGISTER_SET_HDR_OPT_DELAY_MS(val) ((val) ?: 1)
208
209 /*
210 * Various values for the opt_hdr_v1->headertype field, describing the
211 * different types of optional headers. The "secure" header contains
212 * informations related to secure boot (encryption keys, etc.). The
213 * "binary" header contains ARM binary code to be executed prior to
214 * executing the main payload (usually the bootloader). This is
215 * typically used to execute DDR3 training code. The "register" header
216 * allows to describe a set of (address, value) tuples that are
217 * generally used to configure the DRAM controller.
218 */
219 #define OPT_HDR_V1_SECURE_TYPE 0x1
220 #define OPT_HDR_V1_BINARY_TYPE 0x2
221 #define OPT_HDR_V1_REGISTER_TYPE 0x3
222
223 /*
224 * Byte 8 of the image header contains the version number. In the v0
225 * header, byte 8 was reserved, and always set to 0. In the v1 header,
226 * byte 8 has been changed to a proper field, set to 1.
227 */
kwbimage_version(const void * header)228 static inline unsigned int kwbimage_version(const void *header)
229 {
230 const unsigned char *ptr = header;
231 return ptr[8];
232 }
233
kwbheader_size(const void * header)234 static inline size_t kwbheader_size(const void *header)
235 {
236 if (kwbimage_version(header) == 0) {
237 const struct main_hdr_v0 *hdr = header;
238
239 /*
240 * First extension header starts immediately after the main
241 * header without any padding. Between extension headers is
242 * 0x20 byte padding. There is no padding after the last
243 * extension header. First binary code header starts immediately
244 * after the last extension header (or immediately after the
245 * main header if there is no extension header) without any
246 * padding. There is no padding between binary code headers and
247 * neither after the last binary code header.
248 */
249 return sizeof(*hdr) +
250 hdr->ext * sizeof(struct ext_hdr_v0) +
251 ((hdr->ext > 1) ? ((hdr->ext - 1) * 0x20) : 0) +
252 hdr->bin * sizeof(struct bin_hdr_v0);
253 } else {
254 const struct main_hdr_v1 *hdr = header;
255
256 return (hdr->headersz_msb << 16) |
257 le16_to_cpu(hdr->headersz_lsb);
258 }
259 }
260
kwbheader_size_for_csum(const void * header)261 static inline size_t kwbheader_size_for_csum(const void *header)
262 {
263 if (kwbimage_version(header) == 0)
264 return sizeof(struct main_hdr_v0);
265 else
266 return kwbheader_size(header);
267 }
268
ext_hdr_v0_first(void * img)269 static inline struct ext_hdr_v0 *ext_hdr_v0_first(void *img)
270 {
271 struct main_hdr_v0 *mhdr;
272
273 if (kwbimage_version(img) != 0)
274 return NULL;
275
276 mhdr = img;
277 if (mhdr->ext)
278 return (struct ext_hdr_v0 *)(mhdr + 1);
279 else
280 return NULL;
281 }
282
_ext_hdr_v0_end(struct main_hdr_v0 * mhdr)283 static inline void *_ext_hdr_v0_end(struct main_hdr_v0 *mhdr)
284 {
285 return (uint8_t *)mhdr + kwbheader_size(mhdr) - mhdr->bin * sizeof(struct bin_hdr_v0);
286 }
287
ext_hdr_v0_next(void * img,struct ext_hdr_v0 * cur)288 static inline struct ext_hdr_v0 *ext_hdr_v0_next(void *img, struct ext_hdr_v0 *cur)
289 {
290 if ((void *)(cur + 1) < _ext_hdr_v0_end(img))
291 return (struct ext_hdr_v0 *)((uint8_t *)(cur + 1) + 0x20);
292 else
293 return NULL;
294 }
295
296 #define for_each_ext_hdr_v0(ehdr, img) \
297 for ((ehdr) = ext_hdr_v0_first((img)); \
298 (ehdr) != NULL; \
299 (ehdr) = ext_hdr_v0_next((img), (ehdr)))
300
bin_hdr_v0_first(void * img)301 static inline struct bin_hdr_v0 *bin_hdr_v0_first(void *img)
302 {
303 struct main_hdr_v0 *mhdr;
304
305 if (kwbimage_version(img) != 0)
306 return NULL;
307
308 mhdr = img;
309 if (mhdr->bin)
310 return _ext_hdr_v0_end(mhdr);
311 else
312 return NULL;
313 }
314
315 #define for_each_bin_hdr_v0(bhdr, img) \
316 for ((bhdr) = bin_hdr_v0_first((img)); \
317 (bhdr) && (void *)(bhdr) < (void *)((uint8_t *)img + kwbheader_size(img)); \
318 (bhdr) = (struct bin_hdr_v0 *)((bhdr))+1)
319
opt_hdr_v1_size(const struct opt_hdr_v1 * ohdr)320 static inline uint32_t opt_hdr_v1_size(const struct opt_hdr_v1 *ohdr)
321 {
322 return (ohdr->headersz_msb << 16) | le16_to_cpu(ohdr->headersz_lsb);
323 }
324
opt_hdr_v1_valid_size(const struct opt_hdr_v1 * ohdr,const void * mhdr_end)325 static inline int opt_hdr_v1_valid_size(const struct opt_hdr_v1 *ohdr,
326 const void *mhdr_end)
327 {
328 uint32_t ohdr_size;
329
330 if ((const void *)(ohdr + 1) > mhdr_end)
331 return 0;
332
333 ohdr_size = opt_hdr_v1_size(ohdr);
334 if (ohdr_size < 8 || (const void *)((const uint8_t *)ohdr + ohdr_size) > mhdr_end)
335 return 0;
336
337 return 1;
338 }
339
opt_hdr_v1_first(void * img)340 static inline struct opt_hdr_v1 *opt_hdr_v1_first(void *img) {
341 struct main_hdr_v1 *mhdr;
342
343 if (kwbimage_version(img) != 1)
344 return NULL;
345
346 mhdr = img;
347 if (mhdr->ext)
348 return (struct opt_hdr_v1 *)(mhdr + 1);
349 else
350 return NULL;
351 }
352
opt_hdr_v1_ext(struct opt_hdr_v1 * cur)353 static inline uint8_t *opt_hdr_v1_ext(struct opt_hdr_v1 *cur)
354 {
355 uint32_t size = opt_hdr_v1_size(cur);
356
357 return (uint8_t *)cur + size - 4;
358 }
359
_opt_hdr_v1_next(struct opt_hdr_v1 * cur)360 static inline struct opt_hdr_v1 *_opt_hdr_v1_next(struct opt_hdr_v1 *cur)
361 {
362 return (struct opt_hdr_v1 *)((uint8_t *)cur + opt_hdr_v1_size(cur));
363 }
364
opt_hdr_v1_next(struct opt_hdr_v1 * cur)365 static inline struct opt_hdr_v1 *opt_hdr_v1_next(struct opt_hdr_v1 *cur)
366 {
367 if (*opt_hdr_v1_ext(cur))
368 return _opt_hdr_v1_next(cur);
369 else
370 return NULL;
371 }
372
373 #define for_each_opt_hdr_v1(ohdr, img) \
374 for ((ohdr) = opt_hdr_v1_first((img)); \
375 (ohdr) != NULL; \
376 (ohdr) = opt_hdr_v1_next((ohdr)))
377
378 #endif /* _KWBIMAGE_H_ */
379