1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Compulab, Ltd.
4 */
5
6 #include <asm/arch/sys_proto.h>
7 #include <asm/arch/mux.h>
8 #include "board.h"
9
10 static struct module_pin_mux rgmii1_pin_mux[] = {
11 {OFFSET(mii1_txen), MODE(2)},
12 {OFFSET(mii1_txd3), MODE(2)},
13 {OFFSET(mii1_txd2), MODE(2)},
14 {OFFSET(mii1_txd1), MODE(2)},
15 {OFFSET(mii1_txd0), MODE(2)},
16 {OFFSET(mii1_txclk), MODE(2)},
17 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
18 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
19 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
20 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN},
21 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE | PULLDOWN_EN},
22 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE | PULLDOWN_EN},
23 {-1},
24 };
25
26 static struct module_pin_mux rgmii2_pin_mux[] = {
27 {OFFSET(gpmc_a0), MODE(2)}, /* txen */
28 {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */
29 {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */
30 {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */
31 {OFFSET(gpmc_a5), MODE(2)}, /* txd0 */
32 {OFFSET(gpmc_a6), MODE(2)}, /* txclk */
33 {OFFSET(gpmc_a1), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxvd */
34 {OFFSET(gpmc_a7), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxclk */
35 {OFFSET(gpmc_a8), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd3 */
36 {OFFSET(gpmc_a9), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd2 */
37 {OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd1 */
38 {OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUP_EN}, /* rxd0 */
39 {-1},
40 };
41
42 static struct module_pin_mux mdio_pin_mux[] = {
43 {OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)},
44 {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
45 {-1},
46 };
47
48 static struct module_pin_mux uart0_pin_mux[] = {
49 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
50 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
51 {-1},
52 };
53
54 static struct module_pin_mux mmc0_pin_mux[] = {
55 {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},
56 {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},
57 {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)},
58 {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)},
59 {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)},
60 {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)},
61 {-1},
62 };
63
64 static struct module_pin_mux i2c_pin_mux[] = {
65 {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
66 {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
67 {OFFSET(spi2_sclk), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
68 {OFFSET(spi2_cs0), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
69 {-1},
70 };
71
72 static struct module_pin_mux nand_pin_mux[] = {
73 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
74 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
75 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
76 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
77 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
78 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
79 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
80 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
81 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
82 {OFFSET(gpmc_wpn), (MODE(0) | PULLUP_EN)},
83 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
84 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
85 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
86 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
87 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
88 {-1},
89 };
90
91 static struct module_pin_mux emmc_pin_mux[] = {
92 {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* EMMC_CLK */
93 {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_CMD */
94 {OFFSET(gpmc_ad8), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT0 */
95 {OFFSET(gpmc_ad9), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT1 */
96 {OFFSET(gpmc_ad10), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT2 */
97 {OFFSET(gpmc_ad11), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT3 */
98 {OFFSET(gpmc_ad12), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT4 */
99 {OFFSET(gpmc_ad13), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT5 */
100 {OFFSET(gpmc_ad14), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT6 */
101 {OFFSET(gpmc_ad15), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT7 */
102 {-1},
103 };
104
105 static struct module_pin_mux spi_flash_pin_mux[] = {
106 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN)},
107 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},
108 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN)},
109 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},
110 {-1},
111 };
112
set_uart_mux_conf(void)113 void set_uart_mux_conf(void)
114 {
115 configure_module_pin_mux(uart0_pin_mux);
116 }
117
set_mdio_pin_mux(void)118 void set_mdio_pin_mux(void)
119 {
120 configure_module_pin_mux(mdio_pin_mux);
121 }
122
set_rgmii_pin_mux(void)123 void set_rgmii_pin_mux(void)
124 {
125 configure_module_pin_mux(rgmii1_pin_mux);
126 configure_module_pin_mux(rgmii2_pin_mux);
127 }
128
set_mux_conf_regs(void)129 void set_mux_conf_regs(void)
130 {
131 configure_module_pin_mux(mmc0_pin_mux);
132 configure_module_pin_mux(emmc_pin_mux);
133 configure_module_pin_mux(i2c_pin_mux);
134 configure_module_pin_mux(spi_flash_pin_mux);
135 configure_module_pin_mux(nand_pin_mux);
136 }
137
set_i2c_pin_mux(void)138 void set_i2c_pin_mux(void)
139 {
140 configure_module_pin_mux(i2c_pin_mux);
141 }
142