1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 /* Tegra AP (Application Processor) code */
8
9 #include <config.h>
10 #include <log.h>
11 #include <linux/bug.h>
12 #include <asm/io.h>
13 #include <asm/arch/gp_padctrl.h>
14 #include <asm/arch/mc.h>
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clock.h>
17 #include <asm/arch-tegra/fuse.h>
18 #include <asm/arch-tegra/pmc.h>
19 #include <asm/arch-tegra/scu.h>
20 #include <asm/arch-tegra/tegra.h>
21 #include <asm/arch-tegra/warmboot.h>
22
tegra_get_chip(void)23 int tegra_get_chip(void)
24 {
25 int rev;
26 struct apb_misc_gp_ctlr *gp =
27 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
28
29 /*
30 * This is undocumented, Chip ID is bits 15:8 of the register
31 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
32 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
33 */
34 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
35 debug("%s: CHIPID is 0x%02x\n", __func__, rev);
36
37 return rev;
38 }
39
tegra_get_major_version(void)40 u32 tegra_get_major_version(void)
41 {
42 struct apb_misc_gp_ctlr *gp =
43 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
44
45 return (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> HIDREV_MAJORPREV_SHIFT;
46 }
47
tegra_get_sku_info(void)48 int tegra_get_sku_info(void)
49 {
50 int sku_id;
51 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
52
53 sku_id = readl(&fuse->sku_info) & 0xff;
54 debug("%s: SKU info byte is 0x%02x\n", __func__, sku_id);
55
56 return sku_id;
57 }
58
tegra_get_chip_sku(void)59 int tegra_get_chip_sku(void)
60 {
61 uint sku_id, chip_id;
62
63 chip_id = tegra_get_chip();
64 sku_id = tegra_get_sku_info();
65
66 switch (chip_id) {
67 case CHIPID_TEGRA20:
68 switch (sku_id) {
69 case SKU_ID_AP20:
70 case SKU_ID_T20:
71 case SKU_ID_AP20H:
72 return TEGRA_SOC_T20;
73 case SKU_ID_T25SE:
74 case SKU_ID_AP25:
75 case SKU_ID_T25:
76 case SKU_ID_AP25E:
77 case SKU_ID_T25E:
78 return TEGRA_SOC_T25;
79 }
80 break;
81 case CHIPID_TEGRA30:
82 switch (sku_id) {
83 case SKU_ID_T33:
84 case SKU_ID_T30:
85 case SKU_ID_TM30MQS_P_A3:
86 default:
87 return TEGRA_SOC_T30;
88 }
89 break;
90 case CHIPID_TEGRA114:
91 switch (sku_id) {
92 case SKU_ID_T114_ENG:
93 case SKU_ID_T114_1:
94 default:
95 return TEGRA_SOC_T114;
96 }
97 break;
98 case CHIPID_TEGRA124:
99 switch (sku_id) {
100 case SKU_ID_T124_ENG:
101 default:
102 return TEGRA_SOC_T124;
103 }
104 break;
105 case CHIPID_TEGRA210:
106 switch (sku_id) {
107 case SKU_ID_T210_ENG:
108 default:
109 return TEGRA_SOC_T210;
110 }
111 break;
112 }
113
114 /* unknown chip/sku id */
115 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02x/0x%02x)\n",
116 __func__, chip_id, sku_id);
117 return TEGRA_SOC_UNKNOWN;
118 }
119
120 #ifndef CONFIG_ARM64
enable_scu(void)121 static void enable_scu(void)
122 {
123 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
124 u32 reg;
125
126 /* Only enable the SCU on T20/T25 */
127 if (tegra_get_chip() != CHIPID_TEGRA20)
128 return;
129
130 /* If SCU already setup/enabled, return */
131 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
132 return;
133
134 /* Invalidate all ways for all processors */
135 writel(0xFFFF, &scu->scu_inv_all);
136
137 /* Enable SCU - bit 0 */
138 reg = readl(&scu->scu_ctrl);
139 reg |= SCU_CTRL_ENABLE;
140 writel(reg, &scu->scu_ctrl);
141 }
142
get_odmdata(void)143 static u32 get_odmdata(void)
144 {
145 /*
146 * ODMDATA is stored in the BCT in IRAM by the BootROM.
147 * The BCT start and size are stored in the BIT in IRAM.
148 * Read the data @ bct_start + (bct_size - 12). This works
149 * on BCTs for currently supported SoCs, which are locked down.
150 * If this changes in new chips, we can revisit this algorithm.
151 */
152 unsigned long bct_start;
153 u32 odmdata;
154
155 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
156 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
157
158 return odmdata;
159 }
160
init_pmc_scratch(void)161 static void init_pmc_scratch(void)
162 {
163 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
164 u32 odmdata;
165 int i;
166
167 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
168 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
169 if (!tegra_cpu_is_non_secure())
170 #endif
171 {
172 for (i = 0; i < 23; i++)
173 writel(0, &pmc->pmc_scratch1 + i);
174 }
175
176 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
177 odmdata = get_odmdata();
178 writel(odmdata, &pmc->pmc_scratch20);
179 }
180
181 #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
protect_secure_section(void)182 void protect_secure_section(void)
183 {
184 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
185
186 /* Must be MB aligned */
187 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
188 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
189
190 writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
191 writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
192 }
193 #endif
194
195 #if defined(CONFIG_ARMV7_NONSEC)
smmu_flush(struct mc_ctlr * mc)196 static void smmu_flush(struct mc_ctlr *mc)
197 {
198 (void)readl(&mc->mc_smmu_config);
199 }
200
smmu_enable(void)201 static void smmu_enable(void)
202 {
203 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
204 u32 value;
205
206 /*
207 * Enable translation for all clients since access to this register
208 * is restricted to TrustZone-secured requestors. The kernel will use
209 * the per-SWGROUP enable bits to enable or disable translations.
210 */
211 writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
212 writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
213 writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
214 writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
215
216 /*
217 * Enable SMMU globally since access to this register is restricted
218 * to TrustZone-secured requestors.
219 */
220 value = readl(&mc->mc_smmu_config);
221 value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
222 writel(value, &mc->mc_smmu_config);
223
224 smmu_flush(mc);
225 }
226 #else
smmu_enable(void)227 static void smmu_enable(void)
228 {
229 }
230 #endif
231
s_init(void)232 void s_init(void)
233 {
234 /* Init PMC scratch memory */
235 init_pmc_scratch();
236
237 enable_scu();
238
239 /* init the cache */
240 config_cache();
241
242 /* enable SMMU */
243 smmu_enable();
244 }
245 #endif
246