1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <cpu_func.h>
7 #include <log.h>
8 #include <asm/global_data.h>
9
10 #include <linux/arm-smccc.h>
11
12 #include <asm/io.h>
13 #include <asm/arch-tegra/pmc.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
tegra_pmc_detect_tz_only(void)18 static bool tegra_pmc_detect_tz_only(void)
19 {
20 static bool initialized = false;
21 static bool is_tz_only = false;
22 u32 value, saved;
23
24 if (!initialized) {
25 saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
26 value = saved ^ 0xffffffff;
27
28 if (value == 0xffffffff)
29 value = 0xdeadbeef;
30
31 /* write pattern and read it back */
32 writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
33 value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
34
35 /* if we read all-zeroes, access is restricted to TZ only */
36 if (value == 0) {
37 debug("access to PMC is restricted to TZ\n");
38 is_tz_only = true;
39 } else {
40 /* restore original value */
41 writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
42 }
43
44 initialized = true;
45 }
46
47 return is_tz_only;
48 }
49 #endif
50
tegra_pmc_readl(unsigned long offset)51 uint32_t tegra_pmc_readl(unsigned long offset)
52 {
53 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
54 if (tegra_pmc_detect_tz_only()) {
55 struct arm_smccc_res res;
56
57 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
58 0, 0, 0, &res);
59 if (res.a0)
60 printf("%s(): SMC failed: %lu\n", __func__, res.a0);
61
62 return res.a1;
63 }
64 #endif
65
66 return readl(NV_PA_PMC_BASE + offset);
67 }
68
tegra_pmc_writel(u32 value,unsigned long offset)69 void tegra_pmc_writel(u32 value, unsigned long offset)
70 {
71 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
72 if (tegra_pmc_detect_tz_only()) {
73 struct arm_smccc_res res;
74
75 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
76 value, 0, 0, 0, 0, &res);
77 if (res.a0)
78 printf("%s(): SMC failed: %lu\n", __func__, res.a0);
79
80 return;
81 }
82 #endif
83
84 writel(value, NV_PA_PMC_BASE + offset);
85 }
86