1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010 - 2011
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <asm/global_data.h>
8 #include <asm/io.h>
9 #include <linux/errno.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/emc.h>
12 #include <asm/arch/gp_padctrl.h>
13 #include <asm/arch/pinmux.h>
14 #include <asm/arch/sdram_param.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/ap.h>
17 #include <asm/arch-tegra/apb_misc.h>
18 #include <asm/arch-tegra/clk_rst.h>
19 #include <asm/arch-tegra/pmc.h>
20 #include <asm/arch-tegra/fuse.h>
21 #include <asm/arch-tegra/warmboot.h>
22 #include <asm/arch-tegra/crypto.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 /*
27 * This is the place in SRAM where the SDRAM parameters are stored. There
28 * are 4 blocks, one for each RAM code
29 */
30 #define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
31
32 /* TODO: If we later add support for the Misc GP controller, refactor this */
33 union xm2cfga_reg {
34 struct {
35 u32 reserved0:2;
36 u32 hsm_en:1;
37 u32 reserved1:2;
38 u32 preemp_en:1;
39 u32 vref_en:1;
40 u32 reserved2:5;
41 u32 cal_drvdn:5;
42 u32 reserved3:3;
43 u32 cal_drvup:5;
44 u32 reserved4:3;
45 u32 cal_drvdn_slwr:2;
46 u32 cal_drvup_slwf:2;
47 };
48 u32 word;
49 };
50
51 union xm2cfgd_reg {
52 struct {
53 u32 reserved0:2;
54 u32 hsm_en:1;
55 u32 schmt_en:1;
56 u32 lpmd:2;
57 u32 vref_en:1;
58 u32 reserved1:5;
59 u32 cal_drvdn:5;
60 u32 reserved2:3;
61 u32 cal_drvup:5;
62 u32 reserved3:3;
63 u32 cal_drvdn_slwr:2;
64 u32 cal_drvup_slwf:2;
65 };
66 u32 word;
67 };
68
69 /*
70 * TODO: This register is not documented in the TRM yet. We could move this
71 * into the EMC and give it a proper interface, but not while it is
72 * undocumented.
73 */
74 union fbio_spare_reg {
75 struct {
76 u32 reserved:24;
77 u32 cfg_wb0:8;
78 };
79 u32 word;
80 };
81
82 /* We pack the resume information into these unions for later */
83 union scratch2_reg {
84 struct {
85 u32 pllm_base_divm:5;
86 u32 pllm_base_divn:10;
87 u32 pllm_base_divp:3;
88 u32 pllm_misc_lfcon:4;
89 u32 pllm_misc_cpcon:4;
90 u32 gp_xm2cfga_padctrl_preemp:1;
91 u32 gp_xm2cfgd_padctrl_schmt:1;
92 u32 osc_ctrl_xobp:1;
93 u32 memory_type:3;
94 };
95 u32 word;
96 };
97
98 union scratch4_reg {
99 struct {
100 u32 emc_clock_divider:8;
101 u32 pllm_stable_time:8;
102 u32 pllx_stable_time:8;
103 u32 emc_fbio_spare_cfg_wb0:8;
104 };
105 u32 word;
106 };
107
108 union scratch24_reg {
109 struct {
110 u32 emc_auto_cal_wait:8;
111 u32 emc_pin_program_wait:8;
112 u32 warmboot_wait:8;
113 u32 reserved:8;
114 };
115 u32 word;
116 };
117
warmboot_save_sdram_params(void)118 int warmboot_save_sdram_params(void)
119 {
120 u32 ram_code;
121 struct sdram_params sdram;
122 struct apb_misc_pp_ctlr *apb_misc =
123 (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
124 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
125 struct apb_misc_gp_ctlr *gp =
126 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
127 struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
128 union scratch2_reg scratch2;
129 union scratch4_reg scratch4;
130 union scratch24_reg scratch24;
131 union xm2cfga_reg xm2cfga;
132 union xm2cfgd_reg xm2cfgd;
133 union fbio_spare_reg fbio_spare;
134
135 /* get ram code that is used as index to array sdram_params in BCT */
136 ram_code = (readl(&apb_misc->strapping_opt_a) >>
137 STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
138 memcpy(&sdram,
139 (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
140 sizeof(sdram));
141
142 xm2cfga.word = readl(&gp->xm2cfga);
143 xm2cfgd.word = readl(&gp->xm2cfgd);
144
145 scratch2.word = 0;
146 scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
147
148 /* Get the memory PLL settings */
149 {
150 u32 divm, divn, divp, cpcon, lfcon;
151
152 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
153 &cpcon, &lfcon))
154 return -1;
155 scratch2.pllm_base_divm = divm;
156 scratch2.pllm_base_divn = divn;
157 scratch2.pllm_base_divp = divp;
158 scratch2.pllm_misc_cpcon = cpcon;
159 scratch2.pllm_misc_lfcon = lfcon;
160 }
161
162 scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
163 scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
164 scratch2.memory_type = sdram.memory_type;
165 writel(scratch2.word, &pmc->pmc_scratch2);
166
167 /* collect data from various sources for pmc_scratch4 */
168 fbio_spare.word = readl(&emc->fbio_spare);
169 scratch4.word = 0;
170 scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
171 scratch4.emc_clock_divider = sdram.emc_clock_divider;
172 scratch4.pllm_stable_time = -1;
173 scratch4.pllx_stable_time = -1;
174 writel(scratch4.word, &pmc->pmc_scratch4);
175
176 /* collect various data from sdram for pmc_scratch24 */
177 scratch24.word = 0;
178 scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
179 scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
180 scratch24.warmboot_wait = sdram.warm_boot_wait;
181 writel(scratch24.word, &pmc->pmc_scratch24);
182
183 return 0;
184 }
185
determine_crypto_options(int * is_encrypted,int * is_signed)186 static void determine_crypto_options(int *is_encrypted, int *is_signed)
187 {
188 switch (tegra_fuse_get_operation_mode()) {
189 case MODE_ODM_PRODUCTION_SECURE:
190 *is_encrypted = 1;
191 *is_signed = 1;
192 break;
193 case MODE_ODM_PRODUCTION_OPEN:
194 case MODE_PRODUCTION:
195 *is_encrypted = 0;
196 *is_signed = 1;
197 break;
198 case MODE_UNDEFINED:
199 default:
200 *is_encrypted = 0;
201 *is_signed = 0;
202 break;
203 }
204 }
205
encrypt_wb_code(u8 * source,u8 * destination,u32 length)206 static int encrypt_wb_code(u8 *source, u8 *destination, u32 length)
207 {
208 source += offsetof(struct wb_header, random_aes_block);
209 destination += offsetof(struct wb_header, random_aes_block);
210 length -= offsetof(struct wb_header, random_aes_block);
211
212 return encrypt_data_block(source, destination, length);
213 }
214
sign_wb_code(u32 start,u32 length)215 static int sign_wb_code(u32 start, u32 length)
216 {
217 int err;
218 u8 *source; /* Pointer to source */
219 u8 *hash;
220
221 /* Calculate AES block parameters. */
222 source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
223 length -= offsetof(struct wb_header, random_aes_block);
224 hash = (u8 *)(start + offsetof(struct wb_header, hash));
225 err = sign_data_block(source, length, hash);
226
227 return err;
228 }
229
warmboot_prepare_code(u32 seg_address,u32 seg_length)230 int warmboot_prepare_code(u32 seg_address, u32 seg_length)
231 {
232 int err = 0;
233 u32 length; /* length of the signed/encrypt code */
234 struct wb_header *dst_header; /* Pointer to dest WB header */
235 int is_encrypted; /* Segment is encrypted */
236 int is_signed; /* Segment is signed */
237
238 /* Determine crypto options. */
239 determine_crypto_options(&is_encrypted, &is_signed);
240
241 /* Get the actual code limits. */
242 length = roundup(((u32)wb_end - (u32)wb_start), 16);
243
244 /*
245 * The region specified by seg_address must be in SDRAM and must be
246 * nonzero in length.
247 */
248 if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
249 seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
250 err = -EFAULT;
251 goto fail;
252 }
253
254 /* Things must be 16-byte aligned. */
255 if ((seg_length & 0xF) || (seg_address & 0xF)) {
256 err = -EINVAL;
257 goto fail;
258 }
259
260 /* Will the code fit? (destination includes wb_header + wb code) */
261 if (seg_length < (length + sizeof(struct wb_header))) {
262 err = -EINVAL;
263 goto fail;
264 }
265
266 dst_header = (struct wb_header *)seg_address;
267 memset((char *)dst_header, 0, sizeof(struct wb_header));
268
269 /* Populate the random_aes_block as requested. */
270 {
271 u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
272 u32 *end = (u32 *)(((u32)aes_block) +
273 sizeof(dst_header->random_aes_block));
274
275 do {
276 *aes_block++ = 0;
277 } while (aes_block < end);
278 }
279
280 /* Populate the header. */
281 dst_header->length_insecure = length + sizeof(struct wb_header);
282 dst_header->length_secure = length + sizeof(struct wb_header);
283 dst_header->destination = NV_WB_RUN_ADDRESS;
284 dst_header->entry_point = NV_WB_RUN_ADDRESS;
285 dst_header->code_length = length;
286
287 if (is_encrypted)
288 encrypt_wb_code((u8 *)wb_start, (u8 *)dst_header,
289 length + sizeof(struct wb_header));
290 else
291 /* copy the wb code directly following dst_header */
292 memcpy((char *)(dst_header + 1), (char *)wb_start, length);
293
294 if (is_signed)
295 err = sign_wb_code(seg_address, dst_header->length_insecure);
296
297 fail:
298 if (err)
299 printf("Warning: warmboot code copy failed (error=%d)\n", err);
300
301 return err;
302 }
303