1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * ENETC ethernet controller driver 4 * Copyright 2017-2021 NXP 5 */ 6 7 #ifndef _ENETC_H 8 #define _ENETC_H 9 10 #include <linux/bitops.h> 11 #define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args) 12 13 /* PCI function IDs */ 14 #define PCI_DEVICE_ID_ENETC_ETH 0xE100 15 #define PCI_DEVICE_ID_ENETC4_ETH 0xE101 16 #define PCI_DEVICE_ID_ENETC_MDIO 0xEE01 17 #define PCI_DEVICE_ID_ENETC4_EMDIO 0xEE00 18 19 /* ENETC Ethernet controller registers */ 20 /* Station interface register offsets */ 21 #define ENETC_SIMR 0x000 22 #define ENETC_SIMR_EN BIT(31) 23 #define ENETC_SICAR0 0x040 24 /* write cache cfg: snoop, no allocate, data & BD coherent */ 25 #define ENETC_SICAR_WR_CFG 0x6767 26 /* read cache cfg: coherent copy, look up, don't alloc in cache */ 27 #define ENETC_SICAR_RD_CFG_LS 0x27270000 28 #define ENETC_SICAR_RD_CFG_IMX 0x2b2b0000 29 #define ENETC_SIROCT 0x300 30 #define ENETC_SIRFRM 0x308 31 #define ENETC_SITOCT 0x320 32 #define ENETC_SITFRM 0x328 33 34 /* Rx/Tx Buffer Descriptor Ring registers */ 35 enum enetc_bdr_type {TX, RX}; 36 #define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off)) 37 #define ENETC_BDR_IDX_MASK 0xffff 38 39 /* Rx BDR reg offsets */ 40 #define ENETC_RBMR 0x00 41 #define ENETC_RBMR_EN BIT(31) 42 #define ENETC_RBBSR 0x08 43 /* initial consumer index for Rx BDR */ 44 #define ENETC_RBCIR 0x0c 45 #define ENETC_RBBAR0 0x10 46 #define ENETC_RBBAR1 0x14 47 #define ENETC_RBPIR 0x18 48 #define ENETC_RBLENR 0x20 49 50 /* Tx BDR reg offsets */ 51 #define ENETC_TBMR 0x00 52 #define ENETC_TBMR_EN BIT(31) 53 #define ENETC_TBBAR0 0x10 54 #define ENETC_TBBAR1 0x14 55 #define ENETC_TBPIR 0x18 56 #define ENETC_TBCIR 0x1c 57 #define ENETC_TBLENR 0x20 58 59 /* Port registers offset */ 60 #define ENETC_PORT_REGS_OFF 0x10000 61 62 /* Port registers */ 63 #define ENETC_PMR_OFFSET_IMX 0x0010 64 #define ENETC_PMR_OFFSET_LS 0x0000 65 #define ENETC_PMR 0x0000 66 #define ENETC_PMR_SI0_EN BIT(16) 67 #define ENETC_PSIPMMR 0x0018 68 #define ENETC_PSIPMARn_OFFSET_IMX 0x0000 69 #define ENETC_PSIPMARn_OFFSET_LS 0x0080 70 #define ENETC_PSIPMAR0 0x0080 71 #define ENETC_PSIPMAR1 0x0084 72 #define ENETC_PCAPR_OFFSET_IMX 0x4008 73 #define ENETC_PCAPR_OFFSET_LS 0x0900 74 #define ENETC_PCAPR0 0x0000 75 #define ENETC_PCAPRO_MDIO BIT(11) /* LS only */ 76 #define ENETC_PCS_PROT GENMASK(15, 0) /* IMX only */ 77 /* ENETC base registers */ 78 #define ENETC_PSICFGR_OFFSET_LS 0x0940 79 #define ENETC_PSICFGR_SHIFT_LS 0x10 80 #define ENETC_PSICFGR_OFFSET_IMX 0x2010 81 #define ENETC_PSICFGR_SHIFT_IMX 0x80 82 #define ENETC_PSICFGR(n, s) ((n) * (s)) 83 #define ENETC_PSICFGR_SET_BDR(rx, tx) (((rx) << 16) | (tx)) 84 /* MAC configuration */ 85 #define ENETC_PM_OFFSET_IMX 0x5000 86 #define ENETC_PM_OFFSET_LS 0x8000 87 #define ENETC_PM_CC 0x0008 88 #define ENETC_PM_CC_DEFAULT 0x0810 89 #define ENETC_PM_CC_TXP_IMX BIT(15) 90 #define ENETC_PM_CC_TXP_LS BIT(11) 91 #define ENETC_PM_CC_PROMIS BIT(4) 92 #define ENETC_PM_CC_TX BIT(1) 93 #define ENETC_PM_CC_RX BIT(0) 94 #define ENETC_PM_MAXFRM 0x0014 95 #define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN 96 #define ENETC_PM_IMDIO_BASE 0x0030 97 #define ENETC_PM_IF_MODE 0x0300 98 #define ENETC_PM_IF_MODE_RG BIT(2) 99 #define ENETC_PM_IF_MODE_AN_ENA BIT(15) 100 #define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13) 101 #define ENETC_PM_IFM_SSP_1000 (2 << 13) 102 #define ENETC_PM_IFM_SSP_100 (0 << 13) 103 #define ENETC_PM_IFM_SSP_10 (1 << 13) 104 #define ENETC_PM_IFM_FULL_DPX_IMX BIT(6) 105 #define ENETC_PM_IFM_FULL_DPX_LS BIT(12) 106 #define ENETC_PM_IF_IFMODE_MASK_IMX GENMASK(2, 0) 107 #define ENETC_PM_IF_IFMODE_MASK_LS GENMASK(1, 0) 108 109 /* i.MX95 specific registers */ 110 #define IMX95_ENETC_SIPMAR0 0x80 111 #define IMX95_ENETC_SIPMAR1 0x84 112 113 /* Port registers */ 114 #define IMX95_ENETC_PMAR0 0x4020 115 #define IMX95_ENETC_PMAR1 0x4024 116 #define ENETC_POR 0x4100 117 118 /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */ 119 #define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER 120 #define ENETC_BD_ALIGN 128 121 122 /* single pair of Rx/Tx rings */ 123 #define ENETC_RX_BDR_CNT 1 124 #define ENETC_TX_BDR_CNT 1 125 #define ENETC_RX_BDR_ID 0 126 #define ENETC_TX_BDR_ID 0 127 128 /* Tx buffer descriptor */ 129 struct enetc_tx_bd { 130 __le64 addr; 131 __le16 buf_len; 132 __le16 frm_len; 133 __le16 err_csum; 134 __le16 flags; 135 }; 136 137 #define ENETC_TXBD_FLAGS_F BIT(15) 138 #define ENETC_POLL_TRIES 32000 139 140 /* Rx buffer descriptor */ 141 union enetc_rx_bd { 142 /* SW provided BD format */ 143 struct { 144 __le64 addr; 145 u8 reserved[8]; 146 } w; 147 148 /* ENETC returned BD format */ 149 struct { 150 __le16 inet_csum; 151 __le16 parse_summary; 152 __le32 rss_hash; 153 __le16 buf_len; 154 __le16 vlan_opt; 155 union { 156 struct { 157 __le16 flags; 158 __le16 error; 159 }; 160 __le32 lstatus; 161 }; 162 } r; 163 }; 164 165 #define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1) 166 #define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1) 167 #define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff) 168 #define ENETC_RXBD_STATUS(flags) ((flags) << 16) 169 170 /* Tx/Rx ring info */ 171 struct bd_ring { 172 void *cons_idx; 173 void *prod_idx; 174 /* next BD index to use */ 175 int next_prod_idx; 176 int next_cons_idx; 177 int bd_count; 178 }; 179 180 /* ENETC private structure */ 181 struct enetc_priv { 182 struct enetc_tx_bd *enetc_txbd; 183 union enetc_rx_bd *enetc_rxbd; 184 185 void *regs_base; /* base ENETC registers */ 186 void *port_regs; /* base ENETC port registers */ 187 188 /* Rx/Tx buffer descriptor rings info */ 189 struct bd_ring tx_bdr; 190 struct bd_ring rx_bdr; 191 192 int uclass_id; 193 struct mii_dev imdio; 194 struct phy_device *phy; 195 }; 196 197 struct enetc_data { 198 /* Register layout offsets */ 199 u16 reg_offset_pmr; 200 u16 reg_offset_psipmar; 201 u16 reg_offset_pcapr; 202 u16 reg_offset_psicfgr; 203 u16 reg_offset_mac; 204 }; 205 206 /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */ 207 #define ENETC_PCS_PHY_ADDR 0 208 209 /* PCS registers */ 210 #define ENETC_PCS_CR 0x00 211 #define ENETC_PCS_CR_RESET_AN 0x1200 212 #define ENETC_PCS_CR_DEF_VAL 0x0140 213 #define ENETC_PCS_CR_RST BIT(15) 214 #define ENETC_PCS_DEV_ABILITY 0x04 215 #define ENETC_PCS_DEV_ABILITY_SGMII 0x4001 216 #define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001 217 #define ENETC_PCS_LINK_TIMER1 0x12 218 #define ENETC_PCS_LINK_TIMER1_VAL 0x06a0 219 #define ENETC_PCS_LINK_TIMER2 0x13 220 #define ENETC_PCS_LINK_TIMER2_VAL 0x0003 221 #define ENETC_PCS_IF_MODE 0x14 222 #define ENETC_PCS_IF_MODE_SGMII BIT(0) 223 #define ENETC_PCS_IF_MODE_SGMII_AN BIT(1) 224 #define ENETC_PCS_IF_MODE_SPEED_1G BIT(3) 225 226 /* PCS replicator block for USXGMII */ 227 #define ENETC_PCS_DEVAD_REPL 0x1f 228 229 #define ENETC_PCS_REPL_LINK_TIMER_1 0x12 230 #define ENETC_PCS_REPL_LINK_TIMER_1_DEF 0x0003 231 #define ENETC_PCS_REPL_LINK_TIMER_2 0x13 232 #define ENETC_PCS_REPL_LINK_TIMER_2_DEF 0x06a0 233 234 /* ENETC external MDIO registers */ 235 #define ENETC_MDIO_BASE 0x1c00 236 #define ENETC_MDIO_CFG 0x00 237 #define ENETC_EMDIO_CFG_C22 0x00809508 238 #define ENETC_EMDIO_CFG_C45 0x00809548 239 #define ENETC_EMDIO_CFG_RD_ER BIT(1) 240 #define ENETC_EMDIO_CFG_BSY BIT(0) 241 #define ENETC_MDIO_CTL 0x04 242 #define ENETC_MDIO_CTL_READ BIT(15) 243 #define ENETC_MDIO_DATA 0x08 244 #define ENETC_MDIO_STAT 0x0c 245 246 #define ENETC_MDIO_READ_ERR 0xffff 247 248 struct enetc_mdio_priv { 249 void *regs_base; 250 }; 251 252 /* 253 * these functions are implemented by ENETC_MDIO and are re-used by ENETC driver 254 * to drive serdes / internal SoC PHYs 255 */ 256 int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad, 257 int reg); 258 int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad, 259 int reg, u16 val); 260 261 /* sets up primary MAC addresses in DT/IERB */ 262 void fdt_fixup_enetc_mac(void *blob); 263 264 #endif /* _ENETC_H */ 265