1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * K3: AM62 SoC definitions, structures etc.
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 */
8
9 #ifndef __ASM_ARCH_AM62_HARDWARE_H
10 #define __ASM_ARCH_AM62_HARDWARE_H
11
12 #include <config.h>
13 #ifndef __ASSEMBLY__
14 #include <linux/bitops.h>
15 #endif
16
17 #define PADCFG_MMR0_BASE 0x04080000
18 #define PADCFG_MMR1_BASE 0x000f0000
19 #define CTRL_MMR0_BASE 0x00100000
20 #define MCU_CTRL_MMR0_BASE 0x04500000
21 #define WKUP_CTRL_MMR0_BASE 0x43000000
22
23 #define CTRLMMR_WKUP_JTAG_DEVICE_ID (WKUP_CTRL_MMR0_BASE + 0x18)
24 #define JTAG_DEV_ID_MASK GENMASK(31, 18)
25 #define JTAG_DEV_ID_SHIFT 18
26 #define JTAG_DEV_CORE_NR_MASK GENMASK(21, 19)
27 #define JTAG_DEV_CORE_NR_SHIFT 19
28 #define JTAG_DEV_GPU_MASK BIT(18)
29 #define JTAG_DEV_GPU_SHIFT 18
30 #define JTAG_DEV_FEATURES_MASK GENMASK(17, 13)
31 #define JTAG_DEV_FEATURES_SHIFT 13
32 #define JTAG_DEV_SECURITY_MASK BIT(12)
33 #define JTAG_DEV_SECURITY_SHIFT 12
34 #define JTAG_DEV_SAFETY_MASK BIT(11)
35 #define JTAG_DEV_SAFETY_SHIFT 11
36 #define JTAG_DEV_SPEED_MASK GENMASK(10, 6)
37 #define JTAG_DEV_SPEED_SHIFT 6
38 #define JTAG_DEV_TEMP_MASK GENMASK(5, 3)
39 #define JTAG_DEV_TEMP_SHIFT 3
40 #define JTAG_DEV_PKG_MASK GENMASK(2, 0)
41 #define JTAG_DEV_PKG_SHIFT 0
42
43 #define JTAG_DEV_FEATURE_NO_PRU 0x4
44
45 #define JTAG_DEV_TEMP_COMMERCIAL 0x3
46 #define JTAG_DEV_TEMP_INDUSTRIAL 0x4
47 #define JTAG_DEV_TEMP_AUTOMOTIVE 0x5
48
49 #define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
50 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
51 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
52 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
53 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
54 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
55 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
56 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
57 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
58 #define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK (~BIT(17))
59
60 /* Primary Bootmode MMC Config macros */
61 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
62 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
63 #define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
64 #define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
65
66 /* Primary Bootmode USB Config macros */
67 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
68 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
69
70 /* Backup Bootmode USB Config macros */
71 #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
72
73 #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
74 #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
75 #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
76
77 #define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
78 #define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
79
80 #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
81
82 /* Reset Reason Detection */
83 #define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178)
84
85 #define RST_SRC_SAFETY_ERR BIT(31)
86 #define RST_SRC_MAIN_ESM_ERR BIT(30)
87 #define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25)
88 #define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24)
89 #define RST_SRC_DS_MAIN_PORZ BIT(23)
90 #define RST_SRC_DM_WDT_RST BIT(22)
91 #define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21)
92 #define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20)
93 #define RST_SRC_SW_MCU_WARM_RST BIT(16)
94 #define RST_SRC_SMS_WARM_RST BIT(13)
95 #define RST_SRC_SMS_COLD_RST BIT(12)
96 #define RST_SRC_DEBUG_RST BIT(8)
97 #define RST_SRC_THERMAL_RST BIT(4)
98 #define RST_SRC_MAIN_RESET_PIN BIT(2)
99 #define RST_SRC_MCU_RESET_PIN BIT(0)
100
101 /* Debounce register configuration */
102 #define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4))
103
104 #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
105 #define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
106
107 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
108
k3_get_core_nr(void)109 static inline int k3_get_core_nr(void)
110 {
111 u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
112
113 return (full_devid & JTAG_DEV_CORE_NR_MASK) >> JTAG_DEV_CORE_NR_SHIFT;
114 }
115
k3_get_speed_grade(void)116 static inline char k3_get_speed_grade(void)
117 {
118 u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
119 u32 speed_grade = (full_devid & JTAG_DEV_SPEED_MASK) >>
120 JTAG_DEV_SPEED_SHIFT;
121
122 return 'A' - 1 + speed_grade;
123 }
124
k3_get_temp_grade(void)125 static inline int k3_get_temp_grade(void)
126 {
127 u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
128
129 return (full_devid & JTAG_DEV_TEMP_MASK) >> JTAG_DEV_TEMP_SHIFT;
130 }
131
k3_get_max_temp(void)132 static inline int k3_get_max_temp(void)
133 {
134 switch (k3_get_temp_grade()) {
135 case JTAG_DEV_TEMP_INDUSTRIAL:
136 return 105;
137 case JTAG_DEV_TEMP_AUTOMOTIVE:
138 return 125;
139 case JTAG_DEV_TEMP_COMMERCIAL:
140 default:
141 return 95;
142 }
143 }
144
k3_get_a53_max_frequency(void)145 static inline int k3_get_a53_max_frequency(void)
146 {
147 switch (k3_get_speed_grade()) {
148 case 'K':
149 return 800000000;
150 case 'S':
151 return 1000000000;
152 case 'T':
153 return 1250000000;
154 case 'G':
155 default:
156 return 300000000;
157 }
158 }
159
k3_has_pru(void)160 static inline int k3_has_pru(void)
161 {
162 u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
163 u32 feature_mask = (full_devid & JTAG_DEV_FEATURES_MASK) >>
164 JTAG_DEV_FEATURES_SHIFT;
165
166 return !(feature_mask & JTAG_DEV_FEATURE_NO_PRU);
167 }
168
k3_has_gpu(void)169 static inline int k3_has_gpu(void)
170 {
171 u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
172
173 return (full_devid & JTAG_DEV_GPU_MASK) >> JTAG_DEV_GPU_SHIFT;
174 }
175
176 #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
177
178 static const u32 put_device_ids[] = {};
179
180 #endif
181
182 static const u32 put_core_ids[] = {};
183
184 #endif /* __ASM_ARCH_AM62_HARDWARE_H */
185