1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * K3: AM62Px SoC definitions, structures etc.
4 *
5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 #ifndef __ASM_ARCH_AM62P_HARDWARE_H
9 #define __ASM_ARCH_AM62P_HARDWARE_H
10
11 #include <config.h>
12 #ifndef __ASSEMBLY__
13 #include <linux/bitops.h>
14 #endif
15
16 #define PADCFG_MMR0_BASE 0x04080000
17 #define PADCFG_MMR1_BASE 0x000f0000
18 #define CTRL_MMR0_BASE 0x00100000
19 #define MCU_CTRL_MMR0_BASE 0x04500000
20 #define WKUP_CTRL_MMR0_BASE 0x43000000
21
22 #define CTRLMMR_WKUP_JTAG_DEVICE_ID (WKUP_CTRL_MMR0_BASE + 0x18)
23 #define JTAG_DEV_CORE_NR_MASK GENMASK(19, 18)
24 #define JTAG_DEV_CORE_NR_SHIFT 18
25 #define JTAG_DEV_CANFD_MASK BIT(15)
26 #define JTAG_DEV_CANFD_SHIFT 15
27 #define JTAG_DEV_VIDEO_CODEC_MASK BIT(14)
28 #define JTAG_DEV_VIDEO_CODEC_SHIFT 14
29 #define JTAG_DEV_SPEED_MASK GENMASK(10, 6)
30 #define JTAG_DEV_SPEED_SHIFT 6
31 #define JTAG_DEV_TEMP_MASK GENMASK(5, 3)
32 #define JTAG_DEV_TEMP_SHIFT 3
33
34 #define JTAG_DEV_TEMP_AUTOMOTIVE 0x5
35 #define JTAG_DEV_TEMP_EXTENDED_VALUE 105
36 #define JTAG_DEV_TEMP_AUTOMOTIVE_VALUE 125
37
38 #define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
39 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
40 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
41 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
42 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
43 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
44 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
45 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
46 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
47
48 /* Primary Bootmode MMC Config macros */
49 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
50 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
51 #define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
52 #define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
53
54 /* Primary Bootmode USB Config macros */
55 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
56 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
57
58 /* Backup Bootmode USB Config macros */
59 #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
60
61 /*
62 * The CTRL_MMR0 memory space is divided into several equally-spaced
63 * partitions, so defining the partition size allows us to determine
64 * register addresses common to those partitions.
65 */
66 #define CTRL_MMR0_PARTITION_SIZE 0x4000
67
68 /*
69 * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
70 * shared register definitions. The same registers are also used for
71 * PADCFG_MMR lock/kick-mechanism.
72 */
73 #define CTRLMMR_LOCK_KICK0 0x1008
74 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
75 #define CTRLMMR_LOCK_KICK1 0x100c
76 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
77
78 #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
79 #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
80 #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
81
82 #define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
83 #define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
84
85 #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c4f1e0
86
87 #define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
88
89 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
90
k3_get_core_nr(void)91 static inline int k3_get_core_nr(void)
92 {
93 u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
94
95 return ((dev_id & JTAG_DEV_CORE_NR_MASK) >> JTAG_DEV_CORE_NR_SHIFT) + 1;
96 }
97
k3_has_video_codec(void)98 static inline int k3_has_video_codec(void)
99 {
100 u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
101
102 return !((dev_id & JTAG_DEV_VIDEO_CODEC_MASK) >> JTAG_DEV_VIDEO_CODEC_SHIFT);
103 }
104
k3_has_canfd(void)105 static inline int k3_has_canfd(void)
106 {
107 u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
108
109 return (dev_id & JTAG_DEV_CANFD_MASK) >> JTAG_DEV_CANFD_SHIFT;
110 }
111
k3_get_max_temp(void)112 static inline int k3_get_max_temp(void)
113 {
114 u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
115 u32 dev_temp = (dev_id & JTAG_DEV_TEMP_MASK) >> JTAG_DEV_TEMP_SHIFT;
116
117 if (dev_temp == JTAG_DEV_TEMP_AUTOMOTIVE)
118 return JTAG_DEV_TEMP_AUTOMOTIVE_VALUE;
119 else
120 return JTAG_DEV_TEMP_EXTENDED_VALUE;
121 }
122
k3_get_speed_grade(void)123 static inline char k3_get_speed_grade(void)
124 {
125 u32 dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
126 u32 speed_grade = (dev_id & JTAG_DEV_SPEED_MASK) >>
127 JTAG_DEV_SPEED_SHIFT;
128
129 return 'A' - 1 + speed_grade;
130 }
131
k3_get_a53_max_frequency(void)132 static inline int k3_get_a53_max_frequency(void)
133 {
134 if (k3_get_speed_grade() == 'O')
135 return 1000000000;
136 else
137 return 1250000000;
138 }
139
140 #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
141
142 static const u32 put_device_ids[] = {};
143
144 #endif
145
146 static const u32 put_core_ids[] = {};
147
148 #endif /* __ASM_ARCH_AM62P_HARDWARE_H */
149