1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * (C) Copyright 2015 Google, Inc
4 */
5
6 #ifndef _ASM_ARCH_CLOCK_H
7 #define _ASM_ARCH_CLOCK_H
8
9 #include <linux/types.h>
10
11 struct udevice;
12
13 /* define pll mode */
14 #define RKCLK_PLL_MODE_SLOW 0
15 #define RKCLK_PLL_MODE_NORMAL 1
16 #define RKCLK_PLL_MODE_DEEP 2
17
18 /*
19 * PLL flags
20 */
21 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
22 /* normal mode only. now only for pll_rk3036, pll_rk3328 type */
23 #define ROCKCHIP_PLL_FIXED_MODE BIT(1)
24
25 enum {
26 ROCKCHIP_SYSCON_NOC,
27 ROCKCHIP_SYSCON_GRF,
28 ROCKCHIP_SYSCON_SGRF,
29 ROCKCHIP_SYSCON_PMU,
30 ROCKCHIP_SYSCON_PMUGRF,
31 ROCKCHIP_SYSCON_PMUSGRF,
32 ROCKCHIP_SYSCON_CIC,
33 ROCKCHIP_SYSCON_MSCH,
34 ROCKCHIP_SYSCON_USBGRF,
35 ROCKCHIP_SYSCON_PCIE30_PHY_GRF,
36 ROCKCHIP_SYSCON_PHP_GRF,
37 ROCKCHIP_SYSCON_PIPE_PHY0_GRF,
38 ROCKCHIP_SYSCON_PIPE_PHY1_GRF,
39 ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
40 ROCKCHIP_SYSCON_VOP_GRF,
41 ROCKCHIP_SYSCON_VO_GRF,
42 };
43
44 /* Standard Rockchip clock numbers */
45 enum rk_clk_id {
46 CLK_OSC,
47 CLK_ARM,
48 CLK_DDR,
49 CLK_CODEC,
50 CLK_GENERAL,
51 CLK_NEW,
52
53 CLK_COUNT,
54 };
55
56 #define PLL(_type, _id, _con, _mode, _mshift, \
57 _lshift, _pflags, _rtable) \
58 { \
59 .id = _id, \
60 .type = _type, \
61 .con_offset = _con, \
62 .mode_offset = _mode, \
63 .mode_shift = _mshift, \
64 .lock_shift = _lshift, \
65 .pll_flags = _pflags, \
66 .rate_table = _rtable, \
67 }
68
69 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
70 _postdiv2, _dsmpd, _frac) \
71 { \
72 .rate = _rate##U, \
73 .fbdiv = _fbdiv, \
74 .postdiv1 = _postdiv1, \
75 .refdiv = _refdiv, \
76 .postdiv2 = _postdiv2, \
77 .dsmpd = _dsmpd, \
78 .frac = _frac, \
79 }
80
81 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
82 { \
83 .rate = _rate##U, \
84 .p = _p, \
85 .m = _m, \
86 .s = _s, \
87 .k = _k, \
88 }
89
90 struct rockchip_pll_rate_table {
91 unsigned long rate;
92 unsigned int nr;
93 unsigned int nf;
94 unsigned int no;
95 unsigned int nb;
96 /* for RK3036/RK3399 */
97 unsigned int fbdiv;
98 unsigned int postdiv1;
99 unsigned int refdiv;
100 unsigned int postdiv2;
101 unsigned int dsmpd;
102 unsigned int frac;
103 /* for RK3588 */
104 unsigned int m;
105 unsigned int p;
106 unsigned int s;
107 unsigned int k;
108 };
109
110 enum rockchip_pll_type {
111 pll_rk3036,
112 pll_rk3066,
113 pll_rk3328,
114 pll_rk3366,
115 pll_rk3399,
116 pll_rk3588,
117 };
118
119 struct rockchip_pll_clock {
120 unsigned int id;
121 unsigned int con_offset;
122 unsigned int mode_offset;
123 unsigned int mode_shift;
124 unsigned int lock_shift;
125 enum rockchip_pll_type type;
126 unsigned int pll_flags;
127 struct rockchip_pll_rate_table *rate_table;
128 unsigned int mode_mask;
129 };
130
131 struct rockchip_cpu_rate_table {
132 unsigned long rate;
133 unsigned int aclk_div;
134 unsigned int pclk_div;
135 };
136
137 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
138 void __iomem *base, ulong clk_id,
139 ulong drate);
140 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
141 void __iomem *base, ulong clk_id);
142 const struct rockchip_cpu_rate_table *
143 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
144 ulong rate);
145
rk_pll_id(enum rk_clk_id clk_id)146 static inline int rk_pll_id(enum rk_clk_id clk_id)
147 {
148 return clk_id - 1;
149 }
150
151 struct sysreset_reg {
152 unsigned int glb_srst_fst_value;
153 unsigned int glb_srst_snd_value;
154 };
155
156 /**
157 * clk_get_divisor() - Calculate the required clock divisior
158 *
159 * Given an input rate and a required output_rate, calculate the Rockchip
160 * divisor needed to achieve this.
161 *
162 * @input_rate: Input clock rate in Hz
163 * @output_rate: Output clock rate in Hz
164 * Return: divisor register value to use
165 */
clk_get_divisor(ulong input_rate,uint output_rate)166 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
167 {
168 uint clk_div;
169
170 clk_div = input_rate / output_rate;
171 clk_div = (clk_div + 1) & 0xfffe;
172
173 return clk_div;
174 }
175
176 /**
177 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
178 *
179 * Return: pointer to registers, or -ve error on error
180 */
181 void *rockchip_get_cru(void);
182
183 /**
184 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
185 *
186 * Return: pointer to registers, or -ve error on error
187 */
188 void *rockchip_get_pmucru(void);
189
190 struct rockchip_cru;
191 struct rk3288_grf;
192
193 void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf);
194
195 int rockchip_get_clk(struct udevice **devp);
196
197 /*
198 * rockchip_reset_bind() - Bind soft reset device as child of clock device
199 *
200 * @pdev: clock udevice
201 * @reg_offset: the first offset in cru for softreset registers
202 * @reg_number: the reg numbers of softreset registers
203 * Return: 0 success, or error value
204 */
205 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
206 /*
207 * rockchip_reset_bind_lut() - Bind soft reset device as child of clock device
208 * using a dedicated SoC lookup table
209 * @pdev: clock udevice
210 * @lookup_table: register lookup_table dedicated to SoC
211 * @reg_offset: the first offset in cru for softreset registers
212 * @reg_number: the reg numbers of softreset registers
213 * Return: 0 success, or error value
214 */
215 int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
216 u32 reg_offset, u32 reg_number);
217 /*
218 * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
219 * using dedicated RK3528 lookup table
220 *
221 * @pdev: clock udevice
222 * @reg_offset: the first offset in cru for softreset registers
223 * @reg_number: the reg numbers of softreset registers
224 * Return: 0 success, or error value
225 */
226 int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
227 /*
228 * rk3576_reset_bind_lut() - Bind soft reset device as child of clock device
229 * using dedicated RK3576 lookup table
230 *
231 * @pdev: clock udevice
232 * @reg_offset: the first offset in cru for softreset registers
233 * @reg_number: the reg numbers of softreset registers
234 * Return: 0 success, or error value
235 */
236 int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
237 /*
238 * rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
239 * using dedicated RK3588 lookup table
240 *
241 * @pdev: clock udevice
242 * @reg_offset: the first offset in cru for softreset registers
243 * @reg_number: the reg numbers of softreset registers
244 * Return: 0 success, or error value
245 */
246 int rk3588_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
247
248 #endif
249