1/* 2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC 3 * 4 * Copyright (C) 2011 Atmel, 5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, 6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * Licensed under GPLv2 or later. 9 */ 10 11#include "skeleton.dtsi" 12#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/clock/at91.h> 16 17/ { 18 model = "Atmel AT91SAM9260 family SoC"; 19 compatible = "atmel,at91sam9260"; 20 interrupt-parent = <&aic>; 21 22 aliases { 23 serial0 = &dbgu; 24 serial1 = &usart0; 25 serial2 = &usart1; 26 serial3 = &usart2; 27 serial4 = &usart3; 28 serial5 = &uart0; 29 serial6 = &uart1; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 tcb0 = &tcb0; 34 tcb1 = &tcb1; 35 i2c0 = &i2c0; 36 ssc0 = &ssc0; 37 spi0 = &spi0; 38 }; 39 cpus { 40 cpu { 41 compatible = "arm,arm926ej-s"; 42 device_type = "cpu"; 43 }; 44 }; 45 46 memory { 47 reg = <0x20000000 0x04000000>; 48 }; 49 50 clocks { 51 slow_xtal: slow_xtal { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <0>; 55 }; 56 57 main_xtal: main_xtal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <0>; 61 }; 62 63 adc_op_clk: adc_op_clk{ 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <5000000>; 67 }; 68 }; 69 70 sram0: sram@002ff000 { 71 compatible = "mmio-sram"; 72 reg = <0x002ff000 0x2000>; 73 }; 74 75 ahb { 76 compatible = "simple-bus"; 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges; 80 bootph-all; 81 82 apb { 83 compatible = "simple-bus"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges; 87 bootph-all; 88 89 aic: interrupt-controller@fffff000 { 90 #interrupt-cells = <3>; 91 compatible = "atmel,at91rm9200-aic"; 92 interrupt-controller; 93 reg = <0xfffff000 0x200>; 94 atmel,external-irqs = <29 30 31>; 95 }; 96 97 ramc0: ramc@ffffea00 { 98 compatible = "atmel,at91sam9260-sdramc"; 99 reg = <0xffffea00 0x200>; 100 }; 101 102 pmc: pmc@fffffc00 { 103 compatible = "atmel,at91sam9260-pmc", "syscon"; 104 reg = <0xfffffc00 0x100>; 105 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 106 interrupt-controller; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 #interrupt-cells = <1>; 110 bootph-all; 111 112 main_osc: main_osc { 113 compatible = "atmel,at91rm9200-clk-main-osc"; 114 #clock-cells = <0>; 115 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 116 clocks = <&main_xtal>; 117 }; 118 119 main: mainck { 120 compatible = "atmel,at91rm9200-clk-main"; 121 #clock-cells = <0>; 122 clocks = <&main_osc>; 123 }; 124 125 slow_rc_osc: slow_rc_osc { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <32768>; 129 clock-accuracy = <50000000>; 130 }; 131 132 clk32k: slck { 133 compatible = "atmel,at91sam9260-clk-slow"; 134 #clock-cells = <0>; 135 clocks = <&slow_rc_osc>, <&slow_xtal>; 136 }; 137 138 plla: pllack@0 { 139 compatible = "atmel,at91rm9200-clk-pll"; 140 #clock-cells = <0>; 141 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 142 clocks = <&main>; 143 reg = <0>; 144 atmel,clk-input-range = <1000000 32000000>; 145 #atmel,pll-clk-output-range-cells = <4>; 146 atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, 147 <150000000 240000000 2 1>; 148 }; 149 150 pllb: pllbck@1 { 151 compatible = "atmel,at91rm9200-clk-pll"; 152 #clock-cells = <0>; 153 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 154 clocks = <&main>; 155 reg = <1>; 156 atmel,clk-input-range = <1000000 5000000>; 157 #atmel,pll-clk-output-range-cells = <4>; 158 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; 159 }; 160 161 mck: masterck { 162 compatible = "atmel,at91rm9200-clk-master"; 163 #clock-cells = <0>; 164 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 165 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 166 atmel,clk-output-range = <0 105000000>; 167 atmel,clk-divisors = <1 2 4 0>; 168 bootph-all; 169 }; 170 171 usb: usbck { 172 compatible = "atmel,at91rm9200-clk-usb"; 173 #clock-cells = <0>; 174 atmel,clk-divisors = <1 2 4 0>; 175 clocks = <&pllb>; 176 }; 177 178 prog: progck { 179 compatible = "atmel,at91rm9200-clk-programmable"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 interrupt-parent = <&pmc>; 183 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 184 185 prog0: prog@0 { 186 #clock-cells = <0>; 187 reg = <0>; 188 interrupts = <AT91_PMC_PCKRDY(0)>; 189 }; 190 191 prog1: prog@1 { 192 #clock-cells = <0>; 193 reg = <1>; 194 interrupts = <AT91_PMC_PCKRDY(1)>; 195 }; 196 }; 197 198 systemck { 199 compatible = "atmel,at91rm9200-clk-system"; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 uhpck: uhpck@6 { 204 #clock-cells = <0>; 205 reg = <6>; 206 clocks = <&usb>; 207 }; 208 209 udpck: udpck@7 { 210 #clock-cells = <0>; 211 reg = <7>; 212 clocks = <&usb>; 213 }; 214 215 pck0: pck0@8 { 216 #clock-cells = <0>; 217 reg = <8>; 218 clocks = <&prog0>; 219 }; 220 221 pck1: pck1@9 { 222 #clock-cells = <0>; 223 reg = <9>; 224 clocks = <&prog1>; 225 }; 226 }; 227 228 periphck { 229 compatible = "atmel,at91rm9200-clk-peripheral"; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 clocks = <&mck>; 233 bootph-all; 234 235 pioA_clk: pioA_clk@2 { 236 #clock-cells = <0>; 237 reg = <2>; 238 bootph-all; 239 }; 240 241 pioB_clk: pioB_clk@3 { 242 #clock-cells = <0>; 243 reg = <3>; 244 bootph-all; 245 }; 246 247 pioC_clk: pioC_clk@4 { 248 #clock-cells = <0>; 249 reg = <4>; 250 bootph-all; 251 }; 252 253 adc_clk: adc_clk@5 { 254 #clock-cells = <0>; 255 reg = <5>; 256 }; 257 258 usart0_clk: usart0_clk@6 { 259 #clock-cells = <0>; 260 reg = <6>; 261 }; 262 263 usart1_clk: usart1_clk@7 { 264 #clock-cells = <0>; 265 reg = <7>; 266 }; 267 268 usart2_clk: usart2_clk@8 { 269 #clock-cells = <0>; 270 reg = <8>; 271 }; 272 273 mci0_clk: mci0_clk@9 { 274 #clock-cells = <0>; 275 reg = <9>; 276 }; 277 278 udc_clk: udc_clk@10 { 279 #clock-cells = <0>; 280 reg = <10>; 281 }; 282 283 twi0_clk: twi0_clk@11 { 284 reg = <11>; 285 #clock-cells = <0>; 286 }; 287 288 spi0_clk: spi0_clk@12 { 289 #clock-cells = <0>; 290 reg = <12>; 291 }; 292 293 spi1_clk: spi1_clk@13 { 294 #clock-cells = <0>; 295 reg = <13>; 296 }; 297 298 ssc0_clk: ssc0_clk@14 { 299 #clock-cells = <0>; 300 reg = <14>; 301 }; 302 303 tc0_clk: tc0_clk@17 { 304 #clock-cells = <0>; 305 reg = <17>; 306 }; 307 308 tc1_clk: tc1_clk@18 { 309 #clock-cells = <0>; 310 reg = <18>; 311 }; 312 313 tc2_clk: tc2_clk@19 { 314 #clock-cells = <0>; 315 reg = <19>; 316 }; 317 318 ohci_clk: ohci_clk@20 { 319 #clock-cells = <0>; 320 reg = <20>; 321 }; 322 323 macb0_clk: macb0_clk@21 { 324 #clock-cells = <0>; 325 reg = <21>; 326 }; 327 328 isi_clk: isi_clk@22 { 329 #clock-cells = <0>; 330 reg = <22>; 331 }; 332 333 usart3_clk: usart3_clk@23 { 334 #clock-cells = <0>; 335 reg = <23>; 336 }; 337 338 uart0_clk: uart0_clk@24 { 339 #clock-cells = <0>; 340 reg = <24>; 341 }; 342 343 uart1_clk: uart1_clk@25 { 344 #clock-cells = <0>; 345 reg = <25>; 346 }; 347 348 tc3_clk: tc3_clk@26 { 349 #clock-cells = <0>; 350 reg = <26>; 351 }; 352 353 tc4_clk: tc4_clk@27 { 354 #clock-cells = <0>; 355 reg = <27>; 356 }; 357 358 tc5_clk: tc5_clk@28 { 359 #clock-cells = <0>; 360 reg = <28>; 361 }; 362 }; 363 }; 364 365 rstc@fffffd00 { 366 compatible = "atmel,at91sam9260-rstc"; 367 reg = <0xfffffd00 0x10>; 368 clocks = <&clk32k>; 369 }; 370 371 shdwc@fffffd10 { 372 compatible = "atmel,at91sam9260-shdwc"; 373 reg = <0xfffffd10 0x10>; 374 clocks = <&clk32k>; 375 }; 376 377 pit: timer@fffffd30 { 378 compatible = "atmel,at91sam9260-pit"; 379 reg = <0xfffffd30 0xf>; 380 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 381 clocks = <&mck>; 382 }; 383 384 tcb0: timer@fffa0000 { 385 compatible = "atmel,at91rm9200-tcb"; 386 reg = <0xfffa0000 0x100>; 387 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 388 18 IRQ_TYPE_LEVEL_HIGH 0 389 19 IRQ_TYPE_LEVEL_HIGH 0>; 390 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; 391 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 392 }; 393 394 tcb1: timer@fffdc000 { 395 compatible = "atmel,at91rm9200-tcb"; 396 reg = <0xfffdc000 0x100>; 397 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 398 27 IRQ_TYPE_LEVEL_HIGH 0 399 28 IRQ_TYPE_LEVEL_HIGH 0>; 400 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>; 401 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 402 }; 403 404 pinctrl: pinctrl@fffff400 { 405 #address-cells = <1>; 406 #size-cells = <1>; 407 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 408 ranges = <0xfffff400 0xfffff400 0x600>; 409 410 atmel,mux-mask = < 411 /* A B */ 412 0xffffffff 0xffc00c3b /* pioA */ 413 0xffffffff 0x7fff3ccf /* pioB */ 414 0xffffffff 0x007fffff /* pioC */ 415 >; 416 bootph-all; 417 418 /* shared pinctrl settings */ 419 dbgu { 420 bootph-all; 421 pinctrl_dbgu: dbgu-0 { 422 atmel,pins = 423 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ 424 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */ 425 }; 426 }; 427 428 usart0 { 429 pinctrl_usart0: usart0-0 { 430 atmel,pins = 431 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ 432 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ 433 }; 434 435 pinctrl_usart0_rts: usart0_rts-0 { 436 atmel,pins = 437 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ 438 }; 439 440 pinctrl_usart0_cts: usart0_cts-0 { 441 atmel,pins = 442 <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ 443 }; 444 445 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { 446 atmel,pins = 447 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ 448 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ 449 }; 450 451 pinctrl_usart0_dcd: usart0_dcd-0 { 452 atmel,pins = 453 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ 454 }; 455 456 pinctrl_usart0_ri: usart0_ri-0 { 457 atmel,pins = 458 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ 459 }; 460 }; 461 462 usart1 { 463 pinctrl_usart1: usart1-0 { 464 atmel,pins = 465 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */ 466 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */ 467 }; 468 469 pinctrl_usart1_rts: usart1_rts-0 { 470 atmel,pins = 471 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ 472 }; 473 474 pinctrl_usart1_cts: usart1_cts-0 { 475 atmel,pins = 476 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ 477 }; 478 }; 479 480 usart2 { 481 pinctrl_usart2: usart2-0 { 482 atmel,pins = 483 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */ 484 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */ 485 }; 486 487 pinctrl_usart2_rts: usart2_rts-0 { 488 atmel,pins = 489 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ 490 }; 491 492 pinctrl_usart2_cts: usart2_cts-0 { 493 atmel,pins = 494 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ 495 }; 496 }; 497 498 usart3 { 499 pinctrl_usart3: usart3-0 { 500 atmel,pins = 501 <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */ 502 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ 503 }; 504 505 pinctrl_usart3_rts: usart3_rts-0 { 506 atmel,pins = 507 <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 508 }; 509 510 pinctrl_usart3_cts: usart3_cts-0 { 511 atmel,pins = 512 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 513 }; 514 }; 515 516 uart0 { 517 pinctrl_uart0: uart0-0 { 518 atmel,pins = 519 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */ 520 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 521 }; 522 }; 523 524 uart1 { 525 pinctrl_uart1: uart1-0 { 526 atmel,pins = 527 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */ 528 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */ 529 }; 530 }; 531 532 nand { 533 pinctrl_nand: nand-0 { 534 atmel,pins = 535 <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */ 536 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */ 537 }; 538 }; 539 540 macb { 541 pinctrl_macb_rmii: macb_rmii-0 { 542 atmel,pins = 543 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 544 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 545 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 546 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 547 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ 548 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 549 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ 550 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ 551 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ 552 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 553 }; 554 555 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 556 atmel,pins = 557 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ 558 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ 559 AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ 560 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 561 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ 562 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 563 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 564 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 565 }; 566 567 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { 568 atmel,pins = 569 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ 570 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ 571 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ 572 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 573 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ 574 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 575 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 576 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 577 }; 578 }; 579 580 mmc0 { 581 pinctrl_mmc0_clk: mmc0_clk-0 { 582 atmel,pins = 583 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ 584 }; 585 586 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 587 atmel,pins = 588 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 589 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ 590 }; 591 592 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 593 atmel,pins = 594 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ 595 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ 596 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ 597 }; 598 599 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { 600 atmel,pins = 601 <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ 602 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ 603 }; 604 605 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { 606 atmel,pins = 607 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ 608 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ 609 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ 610 }; 611 }; 612 613 ssc0 { 614 pinctrl_ssc0_tx: ssc0_tx-0 { 615 atmel,pins = 616 <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ 617 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ 618 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 619 }; 620 621 pinctrl_ssc0_rx: ssc0_rx-0 { 622 atmel,pins = 623 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ 624 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ 625 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ 626 }; 627 }; 628 629 spi0 { 630 pinctrl_spi0: spi0-0 { 631 atmel,pins = 632 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ 633 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ 634 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ 635 }; 636 }; 637 638 spi1 { 639 pinctrl_spi1: spi1-0 { 640 atmel,pins = 641 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ 642 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ 643 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ 644 }; 645 }; 646 647 i2c_gpio0 { 648 pinctrl_i2c_gpio0: i2c_gpio0-0 { 649 atmel,pins = 650 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE 651 AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; 652 }; 653 }; 654 655 tcb0 { 656 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 657 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; 658 }; 659 660 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 661 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; 662 }; 663 664 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 665 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 666 }; 667 668 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 669 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 670 }; 671 672 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 673 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 674 }; 675 676 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 677 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 678 }; 679 680 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 681 atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 682 }; 683 684 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 685 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; 686 }; 687 688 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 689 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; 690 }; 691 }; 692 693 tcb1 { 694 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 695 atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; 696 }; 697 698 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 699 atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; 700 }; 701 702 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 703 atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 704 }; 705 706 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 707 atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; 708 }; 709 710 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 711 atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 712 }; 713 714 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 715 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 716 }; 717 718 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 719 atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; 720 }; 721 722 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 723 atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 724 }; 725 726 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 727 atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 728 }; 729 }; 730 731 pioA: gpio@fffff400 { 732 compatible = "atmel,at91rm9200-gpio"; 733 reg = <0xfffff400 0x200>; 734 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 735 #gpio-cells = <2>; 736 gpio-controller; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 clocks = <&pioA_clk>; 740 bootph-all; 741 }; 742 743 pioB: gpio@fffff600 { 744 compatible = "atmel,at91rm9200-gpio"; 745 reg = <0xfffff600 0x200>; 746 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 747 #gpio-cells = <2>; 748 gpio-controller; 749 interrupt-controller; 750 #interrupt-cells = <2>; 751 clocks = <&pioB_clk>; 752 bootph-all; 753 }; 754 755 pioC: gpio@fffff800 { 756 compatible = "atmel,at91rm9200-gpio"; 757 reg = <0xfffff800 0x200>; 758 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 759 #gpio-cells = <2>; 760 gpio-controller; 761 interrupt-controller; 762 #interrupt-cells = <2>; 763 clocks = <&pioC_clk>; 764 bootph-all; 765 }; 766 }; 767 768 dbgu: serial@fffff200 { 769 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 770 reg = <0xfffff200 0x200>; 771 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&pinctrl_dbgu>; 774 clocks = <&mck>; 775 clock-names = "usart"; 776 status = "disabled"; 777 }; 778 779 usart0: serial@fffb0000 { 780 compatible = "atmel,at91sam9260-usart"; 781 reg = <0xfffb0000 0x200>; 782 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 783 atmel,use-dma-rx; 784 atmel,use-dma-tx; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&pinctrl_usart0>; 787 clocks = <&usart0_clk>; 788 clock-names = "usart"; 789 status = "disabled"; 790 }; 791 792 usart1: serial@fffb4000 { 793 compatible = "atmel,at91sam9260-usart"; 794 reg = <0xfffb4000 0x200>; 795 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 796 atmel,use-dma-rx; 797 atmel,use-dma-tx; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_usart1>; 800 clocks = <&usart1_clk>; 801 clock-names = "usart"; 802 status = "disabled"; 803 }; 804 805 usart2: serial@fffb8000 { 806 compatible = "atmel,at91sam9260-usart"; 807 reg = <0xfffb8000 0x200>; 808 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 809 atmel,use-dma-rx; 810 atmel,use-dma-tx; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&pinctrl_usart2>; 813 clocks = <&usart2_clk>; 814 clock-names = "usart"; 815 status = "disabled"; 816 }; 817 818 usart3: serial@fffd0000 { 819 compatible = "atmel,at91sam9260-usart"; 820 reg = <0xfffd0000 0x200>; 821 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; 822 atmel,use-dma-rx; 823 atmel,use-dma-tx; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&pinctrl_usart3>; 826 clocks = <&usart3_clk>; 827 clock-names = "usart"; 828 status = "disabled"; 829 }; 830 831 uart0: serial@fffd4000 { 832 compatible = "atmel,at91sam9260-usart"; 833 reg = <0xfffd4000 0x200>; 834 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; 835 atmel,use-dma-rx; 836 atmel,use-dma-tx; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&pinctrl_uart0>; 839 clocks = <&uart0_clk>; 840 clock-names = "usart"; 841 status = "disabled"; 842 }; 843 844 uart1: serial@fffd8000 { 845 compatible = "atmel,at91sam9260-usart"; 846 reg = <0xfffd8000 0x200>; 847 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; 848 atmel,use-dma-rx; 849 atmel,use-dma-tx; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&pinctrl_uart1>; 852 clocks = <&uart1_clk>; 853 clock-names = "usart"; 854 status = "disabled"; 855 }; 856 857 macb0: ethernet@fffc4000 { 858 compatible = "cdns,at91sam9260-macb", "cdns,macb"; 859 reg = <0xfffc4000 0x100>; 860 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&pinctrl_macb_rmii>; 863 clocks = <&macb0_clk>, <&macb0_clk>; 864 clock-names = "hclk", "pclk"; 865 status = "disabled"; 866 }; 867 868 usb1: gadget@fffa4000 { 869 compatible = "atmel,at91sam9260-udc"; 870 reg = <0xfffa4000 0x4000>; 871 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 872 clocks = <&udc_clk>, <&udpck>; 873 clock-names = "pclk", "hclk"; 874 status = "disabled"; 875 }; 876 877 i2c0: i2c@fffac000 { 878 compatible = "atmel,at91sam9260-i2c"; 879 reg = <0xfffac000 0x100>; 880 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 clocks = <&twi0_clk>; 884 status = "disabled"; 885 }; 886 887 mmc0: mmc@fffa8000 { 888 compatible = "atmel,hsmci"; 889 reg = <0xfffa8000 0x600>; 890 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 pinctrl-names = "default"; 894 clocks = <&mci0_clk>; 895 clock-names = "mci_clk"; 896 status = "disabled"; 897 }; 898 899 ssc0: ssc@fffbc000 { 900 compatible = "atmel,at91rm9200-ssc"; 901 reg = <0xfffbc000 0x4000>; 902 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 905 clocks = <&ssc0_clk>; 906 clock-names = "pclk"; 907 status = "disabled"; 908 }; 909 910 spi0: spi@fffc8000 { 911 #address-cells = <1>; 912 #size-cells = <0>; 913 compatible = "atmel,at91rm9200-spi"; 914 reg = <0xfffc8000 0x200>; 915 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&pinctrl_spi0>; 918 clocks = <&spi0_clk>; 919 clock-names = "spi_clk"; 920 status = "disabled"; 921 }; 922 923 spi1: spi@fffcc000 { 924 #address-cells = <1>; 925 #size-cells = <0>; 926 compatible = "atmel,at91rm9200-spi"; 927 reg = <0xfffcc000 0x200>; 928 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 929 pinctrl-names = "default"; 930 pinctrl-0 = <&pinctrl_spi1>; 931 clocks = <&spi1_clk>; 932 clock-names = "spi_clk"; 933 status = "disabled"; 934 }; 935 936 adc0: adc@fffe0000 { 937 #address-cells = <1>; 938 #size-cells = <0>; 939 compatible = "atmel,at91sam9260-adc"; 940 reg = <0xfffe0000 0x100>; 941 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; 942 clocks = <&adc_clk>, <&adc_op_clk>; 943 clock-names = "adc_clk", "adc_op_clk"; 944 atmel,adc-use-external-triggers; 945 atmel,adc-channels-used = <0xf>; 946 atmel,adc-vref = <3300>; 947 atmel,adc-startup-time = <15>; 948 atmel,adc-res = <8 10>; 949 atmel,adc-res-names = "lowres", "highres"; 950 atmel,adc-use-res = "highres"; 951 952 trigger@0 { 953 reg = <0>; 954 trigger-name = "timer-counter-0"; 955 trigger-value = <0x1>; 956 }; 957 trigger@1 { 958 reg = <1>; 959 trigger-name = "timer-counter-1"; 960 trigger-value = <0x3>; 961 }; 962 963 trigger@2 { 964 reg = <2>; 965 trigger-name = "timer-counter-2"; 966 trigger-value = <0x5>; 967 }; 968 969 trigger@3 { 970 reg = <3>; 971 trigger-name = "external"; 972 trigger-value = <0xd>; 973 trigger-external; 974 }; 975 }; 976 977 rtc: rtc@fffffd20 { 978 compatible = "atmel,at91sam9260-rtt"; 979 reg = <0xfffffd20 0x10>; 980 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 981 clocks = <&clk32k>; 982 status = "disabled"; 983 }; 984 985 watchdog: watchdog@fffffd40 { 986 compatible = "atmel,at91sam9260-wdt"; 987 reg = <0xfffffd40 0x10>; 988 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 989 clocks = <&clk32k>; 990 atmel,watchdog-type = "hardware"; 991 atmel,reset-type = "all"; 992 atmel,dbg-halt; 993 status = "disabled"; 994 }; 995 996 gpbr: syscon@fffffd50 { 997 compatible = "atmel,at91sam9260-gpbr", "syscon"; 998 reg = <0xfffffd50 0x10>; 999 status = "disabled"; 1000 }; 1001 }; 1002 1003 nand0: nand@40000000 { 1004 compatible = "atmel,at91rm9200-nand"; 1005 #address-cells = <1>; 1006 #size-cells = <1>; 1007 reg = <0x40000000 0x10000000 1008 0xffffe800 0x200 1009 >; 1010 atmel,nand-addr-offset = <21>; 1011 atmel,nand-cmd-offset = <22>; 1012 pinctrl-names = "default"; 1013 pinctrl-0 = <&pinctrl_nand>; 1014 gpios = <&pioC 13 GPIO_ACTIVE_HIGH 1015 &pioC 14 GPIO_ACTIVE_HIGH 1016 0 1017 >; 1018 status = "disabled"; 1019 }; 1020 1021 usb0: ohci@00500000 { 1022 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1023 reg = <0x00500000 0x100000>; 1024 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; 1025 clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; 1026 clock-names = "ohci_clk", "hclk", "uhpck"; 1027 status = "disabled"; 1028 }; 1029 }; 1030 1031 i2c@0 { 1032 compatible = "i2c-gpio"; 1033 gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ 1034 &pioA 24 GPIO_ACTIVE_HIGH /* scl */ 1035 >; 1036 i2c-gpio,sda-open-drain; 1037 i2c-gpio,scl-open-drain; 1038 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&pinctrl_i2c_gpio0>; 1043 status = "disabled"; 1044 }; 1045}; 1046