1 /*
2 * Common APIs for EXYNOS based board
3 *
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <linux/types.h>
27 #include <mach/cpu.h>
28 #include <asm/arch/system.h>
29
30 #define DMC_OFFSET 0x10000
31
32 /*
33 * Memory initialization
34 *
35 * @param reset Reset PHY during initialization.
36 */
37 void mem_ctrl_init(int reset);
38
39 /* System Clock initialization */
40 void system_clock_init(void);
41
42 /*
43 * Init subsystems according to the reset status
44 *
45 * Return: 0 for a normal boot, non-zero for a resume
46 */
47 int do_lowlevel_init(void);
48
49 void sdelay(unsigned long);
50
51 enum l2_cache_params {
52 CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
53 CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
54 CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
55 CACHE_DATA_RAM_SETUP = (1 << 5),
56 CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
57 CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
58 CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
59 CACHE_TAG_RAM_SETUP = (1 << 9),
60 CACHE_ECC_AND_PARITY = (1 << 21),
61 CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
62 };
63
64 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
65 /*
66 * Configure L2CTLR to get timings that keep us from hanging/crashing.
67 *
68 * Must be inline here since low_power_start() is called without a
69 * stack (!).
70 */
configure_l2_ctlr(void)71 static inline void configure_l2_ctlr(void)
72 {
73 uint32_t val;
74
75 mrc_l2_ctlr(val);
76
77 val |= CACHE_TAG_RAM_SETUP |
78 CACHE_DATA_RAM_SETUP |
79 CACHE_TAG_RAM_LATENCY_2_CYCLES |
80 CACHE_DATA_RAM_LATENCY_2_CYCLES;
81
82 if (proid_is_exynos542x()) {
83 val |= CACHE_ECC_AND_PARITY |
84 CACHE_TAG_RAM_LATENCY_3_CYCLES |
85 CACHE_DATA_RAM_LATENCY_3_CYCLES;
86 }
87
88 mcr_l2_ctlr(val);
89 }
90
91 /*
92 * Configure L2ACTLR.
93 *
94 * Must be inline here since low_power_start() is called without a
95 * stack (!).
96 */
configure_l2_actlr(void)97 static inline void configure_l2_actlr(void)
98 {
99 uint32_t val;
100
101 if (proid_is_exynos542x()) {
102 mrc_l2_aux_ctlr(val);
103 val |= CACHE_ENABLE_FORCE_L2_LOGIC |
104 CACHE_DISABLE_CLEAN_EVICT;
105 mcr_l2_aux_ctlr(val);
106 }
107 }
108 #endif
109