1// SPDX-License-Identifier: GPL-2.0 or MIT
2/*
3 * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 * Copyright (c) 2022, Linaro Limited. All rights reserved.
5 *
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	interrupt-parent = <&gic>;
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	aliases {
16		serial0 = &uart0;
17		serial1 = &uart1;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	cpus: cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu: cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a35";
31			reg = <0>;
32			next-level-cache = <&L2_0>;
33		};
34	};
35
36	memory@88200000 {
37		device_type = "memory";
38		reg = <0x88200000 0x77e00000>;
39	};
40
41	nvmxip: nvmxip-qspi@08000000 {
42		compatible = "nvmxip,qspi";
43		reg = <0x08000000 0x2000000>;
44		lba_shift = <9>;
45		lba = <65536>;
46	};
47
48	gic: interrupt-controller@1c000000 {
49		compatible = "arm,gic-400";
50		#interrupt-cells = <3>;
51		#address-cells = <0>;
52		interrupt-controller;
53		reg =	<0x1c010000 0x1000>,
54			<0x1c02f000 0x2000>,
55			<0x1c04f000 0x1000>,
56			<0x1c06f000 0x2000>;
57		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
58			      IRQ_TYPE_LEVEL_LOW)>;
59	};
60
61	L2_0: l2-cache0 {
62		compatible = "cache";
63		cache-level = <2>;
64		cache-size = <0x80000>;
65		cache-line-size = <64>;
66		cache-sets = <1024>;
67	};
68
69	refclk100mhz: refclk100mhz {
70		compatible = "fixed-clock";
71		#clock-cells = <0>;
72		clock-frequency = <100000000>;
73		clock-output-names = "apb_pclk";
74	};
75
76	smbclk: refclk24mhzx2 {
77		/* Reference 24MHz clock x 2 */
78		compatible = "fixed-clock";
79		#clock-cells = <0>;
80		clock-frequency = <48000000>;
81		clock-output-names = "smclk";
82	};
83
84	timer {
85		compatible = "arm,armv8-timer";
86		interrupts =	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
87				 IRQ_TYPE_LEVEL_LOW)>,
88				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
89				 IRQ_TYPE_LEVEL_LOW)>,
90				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
91				 IRQ_TYPE_LEVEL_LOW)>,
92				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
93				 IRQ_TYPE_LEVEL_LOW)>;
94	};
95
96	uartclk: uartclk {
97		/* UART clock - 50MHz */
98		compatible = "fixed-clock";
99		#clock-cells = <0>;
100		clock-frequency = <50000000>;
101		clock-output-names = "uartclk";
102	};
103
104	psci {
105		compatible = "arm,psci-1.0", "arm,psci-0.2";
106		method = "smc";
107	};
108
109	fwu-mdata {
110		compatible = "u-boot,fwu-mdata-gpt";
111		fwu-mdata-store = <&nvmxip>;
112	};
113
114	soc {
115		compatible = "simple-bus";
116		#address-cells = <1>;
117		#size-cells = <1>;
118		interrupt-parent = <&gic>;
119		ranges;
120
121		timer@1a220000 {
122			compatible = "arm,armv7-timer-mem";
123			reg = <0x1a220000 0x1000>;
124			#address-cells = <1>;
125			#size-cells = <1>;
126			clock-frequency = <50000000>;
127			ranges;
128
129			frame@1a230000 {
130				frame-number = <0>;
131				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
132				reg = <0x1a230000 0x1000>;
133			};
134		};
135
136		uart0: serial@1a510000 {
137			compatible = "arm,pl011", "arm,primecell";
138			reg = <0x1a510000 0x1000>;
139			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
140			clocks = <&uartclk>, <&refclk100mhz>;
141			clock-names = "uartclk", "apb_pclk";
142		};
143
144		uart1: serial@1a520000 {
145			compatible = "arm,pl011", "arm,primecell";
146			reg = <0x1a520000 0x1000>;
147			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
148			clocks = <&uartclk>, <&refclk100mhz>;
149			clock-names = "uartclk", "apb_pclk";
150		};
151
152		mhu_hse1: mailbox@1b820000 {
153			compatible = "arm,mhuv2-tx", "arm,primecell";
154			reg = <0x1b820000 0x1000>;
155			clocks = <&refclk100mhz>;
156			clock-names = "apb_pclk";
157			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
158			#mbox-cells = <2>;
159			arm,mhuv2-protocols = <0 0>;
160			secure-status = "okay";     /* secure-world-only */
161			status = "disabled";
162		};
163
164		mhu_seh1: mailbox@1b830000 {
165			compatible = "arm,mhuv2-rx", "arm,primecell";
166			reg = <0x1b830000 0x1000>;
167			clocks = <&refclk100mhz>;
168			clock-names = "apb_pclk";
169			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
170			#mbox-cells = <2>;
171			arm,mhuv2-protocols = <0 0>;
172			secure-status = "okay";     /* secure-world-only */
173			status = "disabled";
174		};
175	};
176};
177