1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Based on "omap4.dtsi" 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/pinctrl/dra.h> 10 11#define MAX_SOURCES 400 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 compatible = "ti,dra7xx"; 18 interrupt-parent = <&crossbar_mpu>; 19 chosen { }; 20 21 aliases { 22 i2c0 = &i2c1; 23 i2c1 = &i2c2; 24 i2c2 = &i2c3; 25 i2c3 = &i2c4; 26 i2c4 = &i2c5; 27 serial0 = &uart1; 28 serial1 = &uart2; 29 serial2 = &uart3; 30 serial3 = &uart4; 31 serial4 = &uart5; 32 serial5 = &uart6; 33 serial6 = &uart7; 34 serial7 = &uart8; 35 serial8 = &uart9; 36 serial9 = &uart10; 37 ethernet0 = &cpsw_emac0; 38 ethernet1 = &cpsw_emac1; 39 d_can0 = &dcan1; 40 d_can1 = &dcan2; 41 spi0 = &qspi; 42 remoteproc0 = &ipu1; 43 remoteproc1 = &ipu2; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&gic>; 53 }; 54 55 gic: interrupt-controller@48211000 { 56 compatible = "arm,cortex-a15-gic"; 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 reg = <0x0 0x48211000 0x0 0x1000>, 60 <0x0 0x48212000 0x0 0x2000>, 61 <0x0 0x48214000 0x0 0x2000>, 62 <0x0 0x48216000 0x0 0x2000>; 63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 64 interrupt-parent = <&gic>; 65 }; 66 67 wakeupgen: interrupt-controller@48281000 { 68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 69 interrupt-controller; 70 #interrupt-cells = <3>; 71 reg = <0x0 0x48281000 0x0 0x1000>; 72 interrupt-parent = <&gic>; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 cpu0: cpu@0 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a15"; 82 reg = <0>; 83 84 operating-points-v2 = <&cpu0_opp_table>; 85 86 clocks = <&dpll_mpu_ck>; 87 clock-names = "cpu"; 88 89 clock-latency = <300000>; /* From omap-cpufreq driver */ 90 91 /* cooling options */ 92 cooling-min-level = <0>; 93 cooling-max-level = <2>; 94 #cooling-cells = <2>; /* min followed by max */ 95 }; 96 }; 97 98 cpu0_opp_table: opp-table { 99 compatible = "operating-points-v2-ti-cpu"; 100 syscon = <&scm_wkup>; 101 102 opp_nom-1000000000 { 103 opp-hz = /bits/ 64 <1000000000>; 104 opp-microvolt = <1060000 850000 1150000>; 105 opp-supported-hw = <0xFF 0x01>; 106 opp-suspend; 107 }; 108 109 opp_od-1176000000 { 110 opp-hz = /bits/ 64 <1176000000>; 111 opp-microvolt = <1160000 885000 1160000>; 112 opp-supported-hw = <0xFF 0x02>; 113 }; 114 }; 115 116 /* 117 * The soc node represents the soc top level view. It is used for IPs 118 * that are not memory mapped in the MPU view or for the MPU itself. 119 */ 120 soc { 121 compatible = "ti,omap-infra"; 122 mpu { 123 compatible = "ti,omap5-mpu"; 124 ti,hwmods = "mpu"; 125 }; 126 }; 127 128 /* 129 * XXX: Use a flat representation of the SOC interconnect. 130 * The real OMAP interconnect network is quite complex. 131 * Since it will not bring real advantage to represent that in DT for 132 * the moment, just use a fake OCP bus entry to represent the whole bus 133 * hierarchy. 134 */ 135 ocp: ocp { 136 compatible = "ti,dra7-l3-noc", "simple-bus"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <0x0 0x0 0x0 0xc0000000>; 140 ti,hwmods = "l3_main_1", "l3_main_2"; 141 reg = <0x0 0x44000000 0x0 0x1000000>, 142 <0x0 0x45000000 0x0 0x1000>; 143 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 144 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 145 146 l4_cfg: l4@4a000000 { 147 compatible = "ti,dra7-l4-cfg", "simple-bus"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0 0x4a000000 0x22c000>; 151 152 scm: scm@2000 { 153 compatible = "ti,dra7-scm-core", "simple-bus"; 154 reg = <0x2000 0x2000>; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 ranges = <0 0x2000 0x2000>; 158 159 scm_conf: scm_conf@0 { 160 compatible = "syscon", "simple-bus"; 161 reg = <0x0 0x1400>; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0 0x0 0x1400>; 165 166 pbias_regulator: pbias_regulator@e00 { 167 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 168 reg = <0xe00 0x4>; 169 syscon = <&scm_conf>; 170 pbias_mmc_reg: pbias_mmc_omap5 { 171 regulator-name = "pbias_mmc_omap5"; 172 regulator-min-microvolt = <1800000>; 173 regulator-max-microvolt = <3300000>; 174 }; 175 }; 176 177 scm_conf_clocks: clocks { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 }; 181 }; 182 183 dra7_pmx_core: pinmux@1400 { 184 compatible = "ti,dra7-padconf", 185 "pinctrl-single"; 186 reg = <0x1400 0x0468>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 #pinctrl-cells = <1>; 190 #interrupt-cells = <1>; 191 interrupt-controller; 192 pinctrl-single,register-width = <32>; 193 pinctrl-single,function-mask = <0x3fffffff>; 194 }; 195 196 scm_conf1: scm_conf@1c04 { 197 compatible = "syscon"; 198 reg = <0x1c04 0x0020>; 199 #syscon-cells = <2>; 200 }; 201 202 scm_conf_pcie: scm_conf@1c24 { 203 compatible = "syscon"; 204 reg = <0x1c24 0x0024>; 205 }; 206 207 sdma_xbar: dma-router@b78 { 208 compatible = "ti,dra7-dma-crossbar"; 209 reg = <0xb78 0xfc>; 210 #dma-cells = <1>; 211 dma-requests = <205>; 212 ti,dma-safe-map = <0>; 213 dma-masters = <&sdma>; 214 }; 215 216 edma_xbar: dma-router@c78 { 217 compatible = "ti,dra7-dma-crossbar"; 218 reg = <0xc78 0x7c>; 219 #dma-cells = <2>; 220 dma-requests = <204>; 221 ti,dma-safe-map = <0>; 222 dma-masters = <&edma>; 223 }; 224 }; 225 226 cm_core_aon: cm_core_aon@5000 { 227 compatible = "ti,dra7-cm-core-aon"; 228 reg = <0x5000 0x2000>; 229 230 cm_core_aon_clocks: clocks { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 235 cm_core_aon_clockdomains: clockdomains { 236 }; 237 }; 238 239 cm_core: cm_core@8000 { 240 compatible = "ti,dra7-cm-core"; 241 reg = <0x8000 0x3000>; 242 243 cm_core_clocks: clocks { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 }; 247 248 cm_core_clockdomains: clockdomains { 249 }; 250 }; 251 }; 252 253 l4_wkup: l4@4ae00000 { 254 compatible = "ti,dra7-l4-wkup", "simple-bus"; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 ranges = <0 0x4ae00000 0x3f000>; 258 259 counter32k: counter@4000 { 260 compatible = "ti,omap-counter32k"; 261 reg = <0x4000 0x40>; 262 ti,hwmods = "counter_32k"; 263 }; 264 265 prm: prm@6000 { 266 compatible = "ti,dra7-prm", "simple-bus"; 267 reg = <0x6000 0x3000>; 268 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 ranges = <0 0x6000 0x3000>; 272 273 prm_clocks: clocks { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 }; 277 278 prm_clockdomains: clockdomains { 279 }; 280 281 ipu1_rst: ipu1_rst@510 { 282 compatible = "ti,dra7-reset"; 283 reg = <0x510 0x8>; 284 ti,nresets = <3>; 285 #reset-cells = <1>; 286 }; 287 288 ipu2_rst: ipu2_rst@910 { 289 compatible = "ti,dra7-reset"; 290 reg = <0x910 0x8>; 291 ti,nresets = <3>; 292 #reset-cells = <1>; 293 }; 294 }; 295 296 scm_wkup: scm_conf@c000 { 297 compatible = "syscon"; 298 reg = <0xc000 0x1000>; 299 }; 300 }; 301 302 axi@0 { 303 compatible = "simple-bus"; 304 #size-cells = <1>; 305 #address-cells = <1>; 306 ranges = <0x51000000 0x51000000 0x3000 307 0x0 0x20000000 0x10000000>; 308 /** 309 * To enable PCI endpoint mode, disable the pcie1_rc 310 * node and enable pcie1_ep mode. 311 */ 312 pcie1_rc: pcie@51000000 { 313 compatible = "ti,dra7-pcie"; 314 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 315 reg-names = "rc_dbics", "ti_conf", "config"; 316 interrupts = <0 232 0x4>, <0 233 0x4>; 317 #address-cells = <3>; 318 #size-cells = <2>; 319 device_type = "pci"; 320 ranges = <0x81000000 0 0 0x03000 0 0x00010000 321 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 322 bus-range = <0x00 0xff>; 323 #interrupt-cells = <1>; 324 num-lanes = <1>; 325 linux,pci-domain = <0>; 326 ti,hwmods = "pcie1"; 327 phys = <&pcie1_phy>; 328 phy-names = "pcie-phy0"; 329 interrupt-map-mask = <0 0 0 7>; 330 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 331 <0 0 0 2 &pcie1_intc 2>, 332 <0 0 0 3 &pcie1_intc 3>, 333 <0 0 0 4 &pcie1_intc 4>; 334 status = "disabled"; 335 pcie1_intc: interrupt-controller { 336 interrupt-controller; 337 #address-cells = <0>; 338 #interrupt-cells = <1>; 339 }; 340 }; 341 342 pcie1_ep: pcie_ep@51000000 { 343 compatible = "ti,dra7-pcie-ep"; 344 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 345 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 346 interrupts = <0 232 0x4>; 347 num-lanes = <1>; 348 num-ib-windows = <4>; 349 num-ob-windows = <16>; 350 ti,hwmods = "pcie1"; 351 phys = <&pcie1_phy>; 352 phy-names = "pcie-phy0"; 353 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 354 status = "disabled"; 355 }; 356 }; 357 358 /* 359 * Register access seems to have complex dependencies and also 360 * seems to need an enabled phy. See the TRM chapter for "Table 361 * 26-678. Main Sequence PCIe Controller Global Initialization" 362 * and also dra7xx_pcie_probe(). 363 */ 364 axi1: target-module@51800000 { 365 compatible = "simple-bus"; 366 #size-cells = <1>; 367 #address-cells = <1>; 368 ranges = <0x51800000 0x51800000 0x3000 369 0x0 0x30000000 0x10000000>; 370 status = "disabled"; 371 pcie@51800000 { 372 compatible = "ti,dra7-pcie"; 373 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 374 reg-names = "rc_dbics", "ti_conf", "config"; 375 interrupts = <0 355 0x4>, <0 356 0x4>; 376 #address-cells = <3>; 377 #size-cells = <2>; 378 device_type = "pci"; 379 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, 380 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; 381 bus-range = <0x00 0xff>; 382 #interrupt-cells = <1>; 383 num-lanes = <1>; 384 linux,pci-domain = <1>; 385 ti,hwmods = "pcie2"; 386 phys = <&pcie2_phy>; 387 phy-names = "pcie-phy0"; 388 interrupt-map-mask = <0 0 0 7>; 389 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 390 <0 0 0 2 &pcie2_intc 2>, 391 <0 0 0 3 &pcie2_intc 3>, 392 <0 0 0 4 &pcie2_intc 4>; 393 pcie2_intc: interrupt-controller { 394 interrupt-controller; 395 #address-cells = <0>; 396 #interrupt-cells = <1>; 397 }; 398 }; 399 }; 400 401 ocmcram1: ocmcram@40300000 { 402 compatible = "mmio-sram"; 403 reg = <0x40300000 0x80000>; 404 ranges = <0x0 0x40300000 0x80000>; 405 #address-cells = <1>; 406 #size-cells = <1>; 407 /* 408 * This is a placeholder for an optional reserved 409 * region for use by secure software. The size 410 * of this region is not known until runtime so it 411 * is set as zero to either be updated to reserve 412 * space or left unchanged to leave all SRAM for use. 413 * On HS parts that that require the reserved region 414 * either the bootloader can update the size to 415 * the required amount or the node can be overridden 416 * from the board dts file for the secure platform. 417 */ 418 sram-hs@0 { 419 compatible = "ti,secure-ram"; 420 reg = <0x0 0x0>; 421 }; 422 }; 423 424 /* 425 * NOTE: ocmcram2 and ocmcram3 are not available on all 426 * DRA7xx and AM57xx variants. Confirm availability in 427 * the data manual for the exact part number in use 428 * before enabling these nodes in the board dts file. 429 */ 430 ocmcram2: ocmcram@40400000 { 431 status = "disabled"; 432 compatible = "mmio-sram"; 433 reg = <0x40400000 0x100000>; 434 ranges = <0x0 0x40400000 0x100000>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 }; 438 439 ocmcram3: ocmcram@40500000 { 440 status = "disabled"; 441 compatible = "mmio-sram"; 442 reg = <0x40500000 0x100000>; 443 ranges = <0x0 0x40500000 0x100000>; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 }; 447 448 bandgap: bandgap@4a0021e0 { 449 reg = <0x4a0021e0 0xc 450 0x4a00232c 0xc 451 0x4a002380 0x2c 452 0x4a0023C0 0x3c 453 0x4a002564 0x8 454 0x4a002574 0x50>; 455 compatible = "ti,dra752-bandgap"; 456 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 457 #thermal-sensor-cells = <1>; 458 }; 459 460 dsp1_system: dsp_system@40d00000 { 461 compatible = "syscon"; 462 reg = <0x40d00000 0x100>; 463 }; 464 465 dra7_iodelay_core: padconf@4844a000 { 466 compatible = "ti,dra7-iodelay"; 467 reg = <0x4844a000 0x0d1c>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 #pinctrl-cells = <2>; 471 }; 472 473 sdma: dma-controller@4a056000 { 474 compatible = "ti,omap4430-sdma"; 475 reg = <0x4a056000 0x1000>; 476 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 480 #dma-cells = <1>; 481 dma-channels = <32>; 482 dma-requests = <127>; 483 }; 484 485 edma: edma@43300000 { 486 compatible = "ti,edma3-tpcc"; 487 ti,hwmods = "tpcc"; 488 reg = <0x43300000 0x100000>; 489 reg-names = "edma3_cc"; 490 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-names = "edma3_ccint", "edma3_mperr", 494 "edma3_ccerrint"; 495 dma-requests = <64>; 496 #dma-cells = <2>; 497 498 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 499 500 /* 501 * memcpy is disabled, can be enabled with: 502 * ti,edma-memcpy-channels = <20 21>; 503 * for example. Note that these channels need to be 504 * masked in the xbar as well. 505 */ 506 }; 507 508 edma_tptc0: tptc@43400000 { 509 compatible = "ti,edma3-tptc"; 510 ti,hwmods = "tptc0"; 511 reg = <0x43400000 0x100000>; 512 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "edma3_tcerrint"; 514 }; 515 516 edma_tptc1: tptc@43500000 { 517 compatible = "ti,edma3-tptc"; 518 ti,hwmods = "tptc1"; 519 reg = <0x43500000 0x100000>; 520 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 521 interrupt-names = "edma3_tcerrint"; 522 }; 523 524 gpio1: gpio@4ae10000 { 525 compatible = "ti,omap4-gpio"; 526 reg = <0x4ae10000 0x200>; 527 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 528 ti,hwmods = "gpio1"; 529 gpio-controller; 530 #gpio-cells = <2>; 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 }; 534 535 gpio2: gpio@48055000 { 536 compatible = "ti,omap4-gpio"; 537 reg = <0x48055000 0x200>; 538 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 539 ti,hwmods = "gpio2"; 540 gpio-controller; 541 #gpio-cells = <2>; 542 interrupt-controller; 543 #interrupt-cells = <2>; 544 }; 545 546 gpio3: gpio@48057000 { 547 compatible = "ti,omap4-gpio"; 548 reg = <0x48057000 0x200>; 549 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 550 ti,hwmods = "gpio3"; 551 gpio-controller; 552 #gpio-cells = <2>; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 }; 556 557 gpio4: gpio@48059000 { 558 compatible = "ti,omap4-gpio"; 559 reg = <0x48059000 0x200>; 560 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 561 ti,hwmods = "gpio4"; 562 gpio-controller; 563 #gpio-cells = <2>; 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 }; 567 568 gpio5: gpio@4805b000 { 569 compatible = "ti,omap4-gpio"; 570 reg = <0x4805b000 0x200>; 571 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 572 ti,hwmods = "gpio5"; 573 gpio-controller; 574 #gpio-cells = <2>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 }; 578 579 gpio6: gpio@4805d000 { 580 compatible = "ti,omap4-gpio"; 581 reg = <0x4805d000 0x200>; 582 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 583 ti,hwmods = "gpio6"; 584 gpio-controller; 585 #gpio-cells = <2>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 }; 589 590 gpio7: gpio@48051000 { 591 compatible = "ti,omap4-gpio"; 592 reg = <0x48051000 0x200>; 593 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 594 ti,hwmods = "gpio7"; 595 gpio-controller; 596 #gpio-cells = <2>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 }; 600 601 gpio8: gpio@48053000 { 602 compatible = "ti,omap4-gpio"; 603 reg = <0x48053000 0x200>; 604 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 605 ti,hwmods = "gpio8"; 606 gpio-controller; 607 #gpio-cells = <2>; 608 interrupt-controller; 609 #interrupt-cells = <2>; 610 }; 611 612 uart1: serial@4806a000 { 613 compatible = "ti,dra742-uart", "ti,omap4-uart"; 614 reg = <0x4806a000 0x100>; 615 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 616 ti,hwmods = "uart1"; 617 clock-frequency = <48000000>; 618 status = "disabled"; 619 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 620 dma-names = "tx", "rx"; 621 }; 622 623 uart2: serial@4806c000 { 624 compatible = "ti,dra742-uart", "ti,omap4-uart"; 625 reg = <0x4806c000 0x100>; 626 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 627 ti,hwmods = "uart2"; 628 clock-frequency = <48000000>; 629 status = "disabled"; 630 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 631 dma-names = "tx", "rx"; 632 }; 633 634 uart3: serial@48020000 { 635 compatible = "ti,dra742-uart", "ti,omap4-uart"; 636 reg = <0x48020000 0x100>; 637 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 638 ti,hwmods = "uart3"; 639 clock-frequency = <48000000>; 640 status = "disabled"; 641 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 642 dma-names = "tx", "rx"; 643 }; 644 645 uart4: serial@4806e000 { 646 compatible = "ti,dra742-uart", "ti,omap4-uart"; 647 reg = <0x4806e000 0x100>; 648 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 649 ti,hwmods = "uart4"; 650 clock-frequency = <48000000>; 651 status = "disabled"; 652 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 653 dma-names = "tx", "rx"; 654 }; 655 656 uart5: serial@48066000 { 657 compatible = "ti,dra742-uart", "ti,omap4-uart"; 658 reg = <0x48066000 0x100>; 659 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 660 ti,hwmods = "uart5"; 661 clock-frequency = <48000000>; 662 status = "disabled"; 663 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 664 dma-names = "tx", "rx"; 665 }; 666 667 uart6: serial@48068000 { 668 compatible = "ti,dra742-uart", "ti,omap4-uart"; 669 reg = <0x48068000 0x100>; 670 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 671 ti,hwmods = "uart6"; 672 clock-frequency = <48000000>; 673 status = "disabled"; 674 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 675 dma-names = "tx", "rx"; 676 }; 677 678 uart7: serial@48420000 { 679 compatible = "ti,dra742-uart", "ti,omap4-uart"; 680 reg = <0x48420000 0x100>; 681 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 682 ti,hwmods = "uart7"; 683 clock-frequency = <48000000>; 684 status = "disabled"; 685 }; 686 687 uart8: serial@48422000 { 688 compatible = "ti,dra742-uart", "ti,omap4-uart"; 689 reg = <0x48422000 0x100>; 690 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 691 ti,hwmods = "uart8"; 692 clock-frequency = <48000000>; 693 status = "disabled"; 694 }; 695 696 uart9: serial@48424000 { 697 compatible = "ti,dra742-uart", "ti,omap4-uart"; 698 reg = <0x48424000 0x100>; 699 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 700 ti,hwmods = "uart9"; 701 clock-frequency = <48000000>; 702 status = "disabled"; 703 }; 704 705 uart10: serial@4ae2b000 { 706 compatible = "ti,dra742-uart", "ti,omap4-uart"; 707 reg = <0x4ae2b000 0x100>; 708 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 709 ti,hwmods = "uart10"; 710 clock-frequency = <48000000>; 711 status = "disabled"; 712 }; 713 714 mailbox1: mailbox@4a0f4000 { 715 compatible = "ti,omap4-mailbox"; 716 reg = <0x4a0f4000 0x200>; 717 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 720 ti,hwmods = "mailbox1"; 721 #mbox-cells = <1>; 722 ti,mbox-num-users = <3>; 723 ti,mbox-num-fifos = <8>; 724 status = "disabled"; 725 }; 726 727 mailbox2: mailbox@4883a000 { 728 compatible = "ti,omap4-mailbox"; 729 reg = <0x4883a000 0x200>; 730 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 734 ti,hwmods = "mailbox2"; 735 #mbox-cells = <1>; 736 ti,mbox-num-users = <4>; 737 ti,mbox-num-fifos = <12>; 738 status = "disabled"; 739 }; 740 741 mailbox3: mailbox@4883c000 { 742 compatible = "ti,omap4-mailbox"; 743 reg = <0x4883c000 0x200>; 744 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 748 ti,hwmods = "mailbox3"; 749 #mbox-cells = <1>; 750 ti,mbox-num-users = <4>; 751 ti,mbox-num-fifos = <12>; 752 status = "disabled"; 753 }; 754 755 mailbox4: mailbox@4883e000 { 756 compatible = "ti,omap4-mailbox"; 757 reg = <0x4883e000 0x200>; 758 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 762 ti,hwmods = "mailbox4"; 763 #mbox-cells = <1>; 764 ti,mbox-num-users = <4>; 765 ti,mbox-num-fifos = <12>; 766 status = "disabled"; 767 }; 768 769 mailbox5: mailbox@48840000 { 770 compatible = "ti,omap4-mailbox"; 771 reg = <0x48840000 0x200>; 772 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 776 ti,hwmods = "mailbox5"; 777 #mbox-cells = <1>; 778 ti,mbox-num-users = <4>; 779 ti,mbox-num-fifos = <12>; 780 status = "disabled"; 781 }; 782 783 mailbox6: mailbox@48842000 { 784 compatible = "ti,omap4-mailbox"; 785 reg = <0x48842000 0x200>; 786 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 790 ti,hwmods = "mailbox6"; 791 #mbox-cells = <1>; 792 ti,mbox-num-users = <4>; 793 ti,mbox-num-fifos = <12>; 794 status = "disabled"; 795 }; 796 797 mailbox7: mailbox@48844000 { 798 compatible = "ti,omap4-mailbox"; 799 reg = <0x48844000 0x200>; 800 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 804 ti,hwmods = "mailbox7"; 805 #mbox-cells = <1>; 806 ti,mbox-num-users = <4>; 807 ti,mbox-num-fifos = <12>; 808 status = "disabled"; 809 }; 810 811 mailbox8: mailbox@48846000 { 812 compatible = "ti,omap4-mailbox"; 813 reg = <0x48846000 0x200>; 814 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 818 ti,hwmods = "mailbox8"; 819 #mbox-cells = <1>; 820 ti,mbox-num-users = <4>; 821 ti,mbox-num-fifos = <12>; 822 status = "disabled"; 823 }; 824 825 mailbox9: mailbox@4885e000 { 826 compatible = "ti,omap4-mailbox"; 827 reg = <0x4885e000 0x200>; 828 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 832 ti,hwmods = "mailbox9"; 833 #mbox-cells = <1>; 834 ti,mbox-num-users = <4>; 835 ti,mbox-num-fifos = <12>; 836 status = "disabled"; 837 }; 838 839 mailbox10: mailbox@48860000 { 840 compatible = "ti,omap4-mailbox"; 841 reg = <0x48860000 0x200>; 842 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 846 ti,hwmods = "mailbox10"; 847 #mbox-cells = <1>; 848 ti,mbox-num-users = <4>; 849 ti,mbox-num-fifos = <12>; 850 status = "disabled"; 851 }; 852 853 mailbox11: mailbox@48862000 { 854 compatible = "ti,omap4-mailbox"; 855 reg = <0x48862000 0x200>; 856 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 860 ti,hwmods = "mailbox11"; 861 #mbox-cells = <1>; 862 ti,mbox-num-users = <4>; 863 ti,mbox-num-fifos = <12>; 864 status = "disabled"; 865 }; 866 867 mailbox12: mailbox@48864000 { 868 compatible = "ti,omap4-mailbox"; 869 reg = <0x48864000 0x200>; 870 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 874 ti,hwmods = "mailbox12"; 875 #mbox-cells = <1>; 876 ti,mbox-num-users = <4>; 877 ti,mbox-num-fifos = <12>; 878 status = "disabled"; 879 }; 880 881 mailbox13: mailbox@48802000 { 882 compatible = "ti,omap4-mailbox"; 883 reg = <0x48802000 0x200>; 884 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 888 ti,hwmods = "mailbox13"; 889 #mbox-cells = <1>; 890 ti,mbox-num-users = <4>; 891 ti,mbox-num-fifos = <12>; 892 status = "disabled"; 893 }; 894 895 timer1: timer@4ae18000 { 896 compatible = "ti,omap5430-timer"; 897 reg = <0x4ae18000 0x80>; 898 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 899 ti,hwmods = "timer1"; 900 ti,timer-alwon; 901 }; 902 903 timer2: timer@48032000 { 904 compatible = "ti,omap5430-timer"; 905 reg = <0x48032000 0x80>; 906 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 907 ti,hwmods = "timer2"; 908 }; 909 910 timer3: timer@48034000 { 911 compatible = "ti,omap5430-timer"; 912 reg = <0x48034000 0x80>; 913 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 914 ti,hwmods = "timer3"; 915 }; 916 917 timer4: timer@48036000 { 918 compatible = "ti,omap5430-timer"; 919 reg = <0x48036000 0x80>; 920 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 921 ti,hwmods = "timer4"; 922 }; 923 924 timer5: timer@48820000 { 925 compatible = "ti,omap5430-timer"; 926 reg = <0x48820000 0x80>; 927 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 928 ti,hwmods = "timer5"; 929 }; 930 931 timer6: timer@48822000 { 932 compatible = "ti,omap5430-timer"; 933 reg = <0x48822000 0x80>; 934 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 935 ti,hwmods = "timer6"; 936 }; 937 938 timer7: timer@48824000 { 939 compatible = "ti,omap5430-timer"; 940 reg = <0x48824000 0x80>; 941 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 942 ti,hwmods = "timer7"; 943 }; 944 945 timer8: timer@48826000 { 946 compatible = "ti,omap5430-timer"; 947 reg = <0x48826000 0x80>; 948 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 949 ti,hwmods = "timer8"; 950 }; 951 952 timer9: timer@4803e000 { 953 compatible = "ti,omap5430-timer"; 954 reg = <0x4803e000 0x80>; 955 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 956 ti,hwmods = "timer9"; 957 }; 958 959 timer10: timer@48086000 { 960 compatible = "ti,omap5430-timer"; 961 reg = <0x48086000 0x80>; 962 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 963 ti,hwmods = "timer10"; 964 }; 965 966 timer11: timer@48088000 { 967 compatible = "ti,omap5430-timer"; 968 reg = <0x48088000 0x80>; 969 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 970 ti,hwmods = "timer11"; 971 }; 972 973 timer12: timer@4ae20000 { 974 compatible = "ti,omap5430-timer"; 975 reg = <0x4ae20000 0x80>; 976 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 977 ti,hwmods = "timer12"; 978 ti,timer-alwon; 979 ti,timer-secure; 980 }; 981 982 timer13: timer@48828000 { 983 compatible = "ti,omap5430-timer"; 984 reg = <0x48828000 0x80>; 985 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 986 ti,hwmods = "timer13"; 987 }; 988 989 timer14: timer@4882a000 { 990 compatible = "ti,omap5430-timer"; 991 reg = <0x4882a000 0x80>; 992 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 993 ti,hwmods = "timer14"; 994 }; 995 996 timer15: timer@4882c000 { 997 compatible = "ti,omap5430-timer"; 998 reg = <0x4882c000 0x80>; 999 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1000 ti,hwmods = "timer15"; 1001 }; 1002 1003 timer16: timer@4882e000 { 1004 compatible = "ti,omap5430-timer"; 1005 reg = <0x4882e000 0x80>; 1006 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1007 ti,hwmods = "timer16"; 1008 }; 1009 1010 wdt2: wdt@4ae14000 { 1011 compatible = "ti,omap3-wdt"; 1012 reg = <0x4ae14000 0x80>; 1013 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1014 ti,hwmods = "wd_timer2"; 1015 }; 1016 1017 hwspinlock: spinlock@4a0f6000 { 1018 compatible = "ti,omap4-hwspinlock"; 1019 reg = <0x4a0f6000 0x1000>; 1020 ti,hwmods = "spinlock"; 1021 #hwlock-cells = <1>; 1022 }; 1023 1024 dmm@4e000000 { 1025 compatible = "ti,omap5-dmm"; 1026 reg = <0x4e000000 0x800>; 1027 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1028 ti,hwmods = "dmm"; 1029 }; 1030 1031 i2c1: i2c@48070000 { 1032 compatible = "ti,omap4-i2c"; 1033 reg = <0x48070000 0x100>; 1034 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 ti,hwmods = "i2c1"; 1038 status = "disabled"; 1039 }; 1040 1041 i2c2: i2c@48072000 { 1042 compatible = "ti,omap4-i2c"; 1043 reg = <0x48072000 0x100>; 1044 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 ti,hwmods = "i2c2"; 1048 status = "disabled"; 1049 }; 1050 1051 i2c3: i2c@48060000 { 1052 compatible = "ti,omap4-i2c"; 1053 reg = <0x48060000 0x100>; 1054 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 ti,hwmods = "i2c3"; 1058 status = "disabled"; 1059 }; 1060 1061 i2c4: i2c@4807a000 { 1062 compatible = "ti,omap4-i2c"; 1063 reg = <0x4807a000 0x100>; 1064 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 ti,hwmods = "i2c4"; 1068 status = "disabled"; 1069 }; 1070 1071 i2c5: i2c@4807c000 { 1072 compatible = "ti,omap4-i2c"; 1073 reg = <0x4807c000 0x100>; 1074 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 ti,hwmods = "i2c5"; 1078 status = "disabled"; 1079 }; 1080 1081 mmc1: mmc@4809c000 { 1082 compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; 1083 reg = <0x4809c000 0x400>; 1084 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1085 ti,hwmods = "mmc1"; 1086 ti,dual-volt; 1087 ti,needs-special-reset; 1088 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; 1089 dma-names = "tx", "rx"; 1090 status = "disabled"; 1091 pbias-supply = <&pbias_mmc_reg>; 1092 max-frequency = <192000000>; 1093 sd-uhs-sdr104; 1094 sd-uhs-sdr50; 1095 sd-uhs-ddr50; 1096 sd-uhs-sdr25; 1097 sd-uhs-sdr12; 1098 }; 1099 1100 mmc2: mmc@480b4000 { 1101 compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; 1102 reg = <0x480b4000 0x400>; 1103 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1104 ti,hwmods = "mmc2"; 1105 ti,needs-special-reset; 1106 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; 1107 dma-names = "tx", "rx"; 1108 status = "disabled"; 1109 max-frequency = <192000000>; 1110 sd-uhs-sdr25; 1111 sd-uhs-sdr12; 1112 mmc-hs200-1_8v; 1113 mmc-ddr-1_8v; 1114 }; 1115 1116 mmc3: mmc@480ad000 { 1117 compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; 1118 reg = <0x480ad000 0x400>; 1119 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1120 ti,hwmods = "mmc3"; 1121 ti,needs-special-reset; 1122 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; 1123 dma-names = "tx", "rx"; 1124 status = "disabled"; 1125 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ 1126 max-frequency = <64000000>; 1127 sd-uhs-sdr12; 1128 sd-uhs-sdr25; 1129 sd-uhs-sdr50; 1130 }; 1131 1132 mmc4: mmc@480d1000 { 1133 compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; 1134 reg = <0x480d1000 0x400>; 1135 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1136 ti,hwmods = "mmc4"; 1137 ti,needs-special-reset; 1138 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; 1139 dma-names = "tx", "rx"; 1140 status = "disabled"; 1141 max-frequency = <192000000>; 1142 sd-uhs-sdr12; 1143 sd-uhs-sdr25; 1144 }; 1145 1146 mmu0_dsp1: mmu@40d01000 { 1147 compatible = "ti,dra7-dsp-iommu"; 1148 reg = <0x40d01000 0x100>; 1149 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1150 ti,hwmods = "mmu0_dsp1"; 1151 #iommu-cells = <0>; 1152 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 1153 status = "disabled"; 1154 }; 1155 1156 mmu1_dsp1: mmu@40d02000 { 1157 compatible = "ti,dra7-dsp-iommu"; 1158 reg = <0x40d02000 0x100>; 1159 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1160 ti,hwmods = "mmu1_dsp1"; 1161 #iommu-cells = <0>; 1162 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 1163 status = "disabled"; 1164 }; 1165 1166 mmu_ipu1: mmu@58882000 { 1167 compatible = "ti,dra7-iommu"; 1168 reg = <0x58882000 0x100>; 1169 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 1170 ti,hwmods = "mmu_ipu1"; 1171 #iommu-cells = <0>; 1172 ti,iommu-bus-err-back; 1173 status = "disabled"; 1174 }; 1175 1176 mmu_ipu2: mmu@55082000 { 1177 compatible = "ti,dra7-iommu"; 1178 reg = <0x55082000 0x100>; 1179 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 1180 ti,hwmods = "mmu_ipu2"; 1181 #iommu-cells = <0>; 1182 ti,iommu-bus-err-back; 1183 status = "disabled"; 1184 }; 1185 1186 abb_mpu: regulator-abb-mpu { 1187 compatible = "ti,abb-v3"; 1188 regulator-name = "abb_mpu"; 1189 #address-cells = <0>; 1190 #size-cells = <0>; 1191 clocks = <&sys_clkin1>; 1192 ti,settling-time = <50>; 1193 ti,clock-cycles = <16>; 1194 1195 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 1196 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 1197 <0x4ae0c158 0x4>; 1198 reg-names = "setup-address", "control-address", 1199 "int-address", "efuse-address", 1200 "ldo-address"; 1201 ti,tranxdone-status-mask = <0x80>; 1202 /* LDOVBBMPU_FBB_MUX_CTRL */ 1203 ti,ldovbb-override-mask = <0x400>; 1204 /* LDOVBBMPU_FBB_VSET_OUT */ 1205 ti,ldovbb-vset-mask = <0x1F>; 1206 1207 /* 1208 * NOTE: only FBB mode used but actual vset will 1209 * determine final biasing 1210 */ 1211 ti,abb_info = < 1212 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1213 1060000 0 0x0 0 0x02000000 0x01F00000 1214 1160000 0 0x4 0 0x02000000 0x01F00000 1215 1210000 0 0x8 0 0x02000000 0x01F00000 1216 >; 1217 }; 1218 1219 abb_ivahd: regulator-abb-ivahd { 1220 compatible = "ti,abb-v3"; 1221 regulator-name = "abb_ivahd"; 1222 #address-cells = <0>; 1223 #size-cells = <0>; 1224 clocks = <&sys_clkin1>; 1225 ti,settling-time = <50>; 1226 ti,clock-cycles = <16>; 1227 1228 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 1229 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 1230 <0x4a002470 0x4>; 1231 reg-names = "setup-address", "control-address", 1232 "int-address", "efuse-address", 1233 "ldo-address"; 1234 ti,tranxdone-status-mask = <0x40000000>; 1235 /* LDOVBBIVA_FBB_MUX_CTRL */ 1236 ti,ldovbb-override-mask = <0x400>; 1237 /* LDOVBBIVA_FBB_VSET_OUT */ 1238 ti,ldovbb-vset-mask = <0x1F>; 1239 1240 /* 1241 * NOTE: only FBB mode used but actual vset will 1242 * determine final biasing 1243 */ 1244 ti,abb_info = < 1245 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1246 1055000 0 0x0 0 0x02000000 0x01F00000 1247 1150000 0 0x4 0 0x02000000 0x01F00000 1248 1250000 0 0x8 0 0x02000000 0x01F00000 1249 >; 1250 }; 1251 1252 abb_dspeve: regulator-abb-dspeve { 1253 compatible = "ti,abb-v3"; 1254 regulator-name = "abb_dspeve"; 1255 #address-cells = <0>; 1256 #size-cells = <0>; 1257 clocks = <&sys_clkin1>; 1258 ti,settling-time = <50>; 1259 ti,clock-cycles = <16>; 1260 1261 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 1262 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 1263 <0x4a00246c 0x4>; 1264 reg-names = "setup-address", "control-address", 1265 "int-address", "efuse-address", 1266 "ldo-address"; 1267 ti,tranxdone-status-mask = <0x20000000>; 1268 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 1269 ti,ldovbb-override-mask = <0x400>; 1270 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 1271 ti,ldovbb-vset-mask = <0x1F>; 1272 1273 /* 1274 * NOTE: only FBB mode used but actual vset will 1275 * determine final biasing 1276 */ 1277 ti,abb_info = < 1278 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1279 1055000 0 0x0 0 0x02000000 0x01F00000 1280 1150000 0 0x4 0 0x02000000 0x01F00000 1281 1250000 0 0x8 0 0x02000000 0x01F00000 1282 >; 1283 }; 1284 1285 abb_gpu: regulator-abb-gpu { 1286 compatible = "ti,abb-v3"; 1287 regulator-name = "abb_gpu"; 1288 #address-cells = <0>; 1289 #size-cells = <0>; 1290 clocks = <&sys_clkin1>; 1291 ti,settling-time = <50>; 1292 ti,clock-cycles = <16>; 1293 1294 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1295 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1296 <0x4ae0c154 0x4>; 1297 reg-names = "setup-address", "control-address", 1298 "int-address", "efuse-address", 1299 "ldo-address"; 1300 ti,tranxdone-status-mask = <0x10000000>; 1301 /* LDOVBBGPU_FBB_MUX_CTRL */ 1302 ti,ldovbb-override-mask = <0x400>; 1303 /* LDOVBBGPU_FBB_VSET_OUT */ 1304 ti,ldovbb-vset-mask = <0x1F>; 1305 1306 /* 1307 * NOTE: only FBB mode used but actual vset will 1308 * determine final biasing 1309 */ 1310 ti,abb_info = < 1311 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1312 1090000 0 0x0 0 0x02000000 0x01F00000 1313 1210000 0 0x4 0 0x02000000 0x01F00000 1314 1280000 0 0x8 0 0x02000000 0x01F00000 1315 >; 1316 }; 1317 1318 mcspi1: spi@48098000 { 1319 compatible = "ti,omap4-mcspi"; 1320 reg = <0x48098000 0x200>; 1321 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 ti,hwmods = "mcspi1"; 1325 ti,spi-num-cs = <4>; 1326 dmas = <&sdma_xbar 35>, 1327 <&sdma_xbar 36>, 1328 <&sdma_xbar 37>, 1329 <&sdma_xbar 38>, 1330 <&sdma_xbar 39>, 1331 <&sdma_xbar 40>, 1332 <&sdma_xbar 41>, 1333 <&sdma_xbar 42>; 1334 dma-names = "tx0", "rx0", "tx1", "rx1", 1335 "tx2", "rx2", "tx3", "rx3"; 1336 status = "disabled"; 1337 }; 1338 1339 mcspi2: spi@4809a000 { 1340 compatible = "ti,omap4-mcspi"; 1341 reg = <0x4809a000 0x200>; 1342 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 ti,hwmods = "mcspi2"; 1346 ti,spi-num-cs = <2>; 1347 dmas = <&sdma_xbar 43>, 1348 <&sdma_xbar 44>, 1349 <&sdma_xbar 45>, 1350 <&sdma_xbar 46>; 1351 dma-names = "tx0", "rx0", "tx1", "rx1"; 1352 status = "disabled"; 1353 }; 1354 1355 mcspi3: spi@480b8000 { 1356 compatible = "ti,omap4-mcspi"; 1357 reg = <0x480b8000 0x200>; 1358 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 ti,hwmods = "mcspi3"; 1362 ti,spi-num-cs = <2>; 1363 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 1364 dma-names = "tx0", "rx0"; 1365 status = "disabled"; 1366 }; 1367 1368 mcspi4: spi@480ba000 { 1369 compatible = "ti,omap4-mcspi"; 1370 reg = <0x480ba000 0x200>; 1371 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 ti,hwmods = "mcspi4"; 1375 ti,spi-num-cs = <1>; 1376 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 1377 dma-names = "tx0", "rx0"; 1378 status = "disabled"; 1379 }; 1380 1381 qspi: qspi@4b300000 { 1382 compatible = "ti,dra7xxx-qspi"; 1383 reg = <0x4b300000 0x100>, 1384 <0x5c000000 0x4000000>; 1385 reg-names = "qspi_base", "qspi_mmap"; 1386 syscon-chipselects = <&scm_conf 0x558>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 ti,hwmods = "qspi"; 1390 clocks = <&qspi_gfclk_div>; 1391 clock-names = "fck"; 1392 num-cs = <4>; 1393 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1394 status = "disabled"; 1395 }; 1396 1397 /* OCP2SCP3 */ 1398 ocp2scp@4a090000 { 1399 compatible = "ti,omap-ocp2scp"; 1400 #address-cells = <1>; 1401 #size-cells = <1>; 1402 ranges; 1403 reg = <0x4a090000 0x20>; 1404 ti,hwmods = "ocp2scp3"; 1405 sata_phy: phy@4A096000 { 1406 compatible = "ti,phy-pipe3-sata"; 1407 reg = <0x4A096000 0x80>, /* phy_rx */ 1408 <0x4A096400 0x64>, /* phy_tx */ 1409 <0x4A096800 0x40>; /* pll_ctrl */ 1410 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1411 syscon-phy-power = <&scm_conf 0x374>; 1412 clocks = <&sys_clkin1>, <&sata_ref_clk>; 1413 clock-names = "sysclk", "refclk"; 1414 syscon-pllreset = <&scm_conf 0x3fc>; 1415 #phy-cells = <0>; 1416 }; 1417 1418 pcie1_phy: pciephy@4a094000 { 1419 compatible = "ti,phy-pipe3-pcie"; 1420 reg = <0x4a094000 0x80>, /* phy_rx */ 1421 <0x4a094400 0x64>; /* phy_tx */ 1422 reg-names = "phy_rx", "phy_tx"; 1423 syscon-phy-power = <&scm_conf_pcie 0x1c>; 1424 syscon-pcs = <&scm_conf_pcie 0x10>; 1425 clocks = <&dpll_pcie_ref_ck>, 1426 <&dpll_pcie_ref_m2ldo_ck>, 1427 <&optfclk_pciephy1_32khz>, 1428 <&optfclk_pciephy1_clk>, 1429 <&optfclk_pciephy1_div_clk>, 1430 <&optfclk_pciephy_div>, 1431 <&sys_clkin1>; 1432 clock-names = "dpll_ref", "dpll_ref_m2", 1433 "wkupclk", "refclk", 1434 "div-clk", "phy-div", "sysclk"; 1435 #phy-cells = <0>; 1436 }; 1437 1438 pcie2_phy: pciephy@4a095000 { 1439 compatible = "ti,phy-pipe3-pcie"; 1440 reg = <0x4a095000 0x80>, /* phy_rx */ 1441 <0x4a095400 0x64>; /* phy_tx */ 1442 reg-names = "phy_rx", "phy_tx"; 1443 syscon-phy-power = <&scm_conf_pcie 0x20>; 1444 syscon-pcs = <&scm_conf_pcie 0x10>; 1445 clocks = <&dpll_pcie_ref_ck>, 1446 <&dpll_pcie_ref_m2ldo_ck>, 1447 <&optfclk_pciephy2_32khz>, 1448 <&optfclk_pciephy2_clk>, 1449 <&optfclk_pciephy2_div_clk>, 1450 <&optfclk_pciephy_div>, 1451 <&sys_clkin1>; 1452 clock-names = "dpll_ref", "dpll_ref_m2", 1453 "wkupclk", "refclk", 1454 "div-clk", "phy-div", "sysclk"; 1455 #phy-cells = <0>; 1456 status = "disabled"; 1457 }; 1458 }; 1459 1460 sata: sata@4a141100 { 1461 compatible = "snps,dwc-ahci"; 1462 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1463 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1464 phys = <&sata_phy>; 1465 phy-names = "sata-phy"; 1466 clocks = <&sata_ref_clk>; 1467 ti,hwmods = "sata"; 1468 ports-implemented = <0x1>; 1469 }; 1470 1471 rtc: rtc@48838000 { 1472 compatible = "ti,am3352-rtc"; 1473 reg = <0x48838000 0x100>; 1474 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1476 ti,hwmods = "rtcss"; 1477 clocks = <&sys_32k_ck>; 1478 }; 1479 1480 /* OCP2SCP1 */ 1481 ocp2scp@4a080000 { 1482 compatible = "ti,omap-ocp2scp"; 1483 #address-cells = <1>; 1484 #size-cells = <1>; 1485 ranges; 1486 reg = <0x4a080000 0x20>; 1487 ti,hwmods = "ocp2scp1"; 1488 1489 usb2_phy1: phy@4a084000 { 1490 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 1491 reg = <0x4a084000 0x400>; 1492 syscon-phy-power = <&scm_conf 0x300>; 1493 clocks = <&usb_phy1_always_on_clk32k>, 1494 <&usb_otg_ss1_refclk960m>; 1495 clock-names = "wkupclk", 1496 "refclk"; 1497 #phy-cells = <0>; 1498 }; 1499 1500 usb2_phy2: phy@4a085000 { 1501 compatible = "ti,dra7x-usb2-phy2", 1502 "ti,omap-usb2"; 1503 reg = <0x4a085000 0x400>; 1504 syscon-phy-power = <&scm_conf 0xe74>; 1505 clocks = <&usb_phy2_always_on_clk32k>, 1506 <&usb_otg_ss2_refclk960m>; 1507 clock-names = "wkupclk", 1508 "refclk"; 1509 #phy-cells = <0>; 1510 }; 1511 1512 usb3_phy1: phy@4a084400 { 1513 compatible = "ti,omap-usb3"; 1514 reg = <0x4a084400 0x80>, 1515 <0x4a084800 0x64>, 1516 <0x4a084c00 0x40>; 1517 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1518 syscon-phy-power = <&scm_conf 0x370>; 1519 clocks = <&usb_phy3_always_on_clk32k>, 1520 <&sys_clkin1>, 1521 <&usb_otg_ss1_refclk960m>; 1522 clock-names = "wkupclk", 1523 "sysclk", 1524 "refclk"; 1525 #phy-cells = <0>; 1526 }; 1527 }; 1528 1529 omap_dwc3_1: omap_dwc3_1@48880000 { 1530 compatible = "ti,dwc3"; 1531 ti,hwmods = "usb_otg_ss1"; 1532 reg = <0x48880000 0x10000>; 1533 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1534 #address-cells = <1>; 1535 #size-cells = <1>; 1536 utmi-mode = <2>; 1537 ranges; 1538 usb1: usb@48890000 { 1539 compatible = "snps,dwc3"; 1540 reg = <0x48890000 0x17000>; 1541 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1544 interrupt-names = "peripheral", 1545 "host", 1546 "otg"; 1547 phys = <&usb2_phy1>, <&usb3_phy1>; 1548 phy-names = "usb2-phy", "usb3-phy"; 1549 maximum-speed = "super-speed"; 1550 dr_mode = "otg"; 1551 snps,dis_u3_susphy_quirk; 1552 snps,dis_u2_susphy_quirk; 1553 }; 1554 }; 1555 1556 omap_dwc3_2: omap_dwc3_2@488c0000 { 1557 compatible = "ti,dwc3"; 1558 ti,hwmods = "usb_otg_ss2"; 1559 reg = <0x488c0000 0x10000>; 1560 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1561 #address-cells = <1>; 1562 #size-cells = <1>; 1563 utmi-mode = <2>; 1564 ranges; 1565 usb2: usb@488d0000 { 1566 compatible = "snps,dwc3"; 1567 reg = <0x488d0000 0x17000>; 1568 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1571 interrupt-names = "peripheral", 1572 "host", 1573 "otg"; 1574 phys = <&usb2_phy2>; 1575 phy-names = "usb2-phy"; 1576 maximum-speed = "high-speed"; 1577 dr_mode = "otg"; 1578 snps,dis_u3_susphy_quirk; 1579 snps,dis_u2_susphy_quirk; 1580 }; 1581 }; 1582 1583 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1584 omap_dwc3_3: omap_dwc3_3@48900000 { 1585 compatible = "ti,dwc3"; 1586 ti,hwmods = "usb_otg_ss3"; 1587 reg = <0x48900000 0x10000>; 1588 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1589 #address-cells = <1>; 1590 #size-cells = <1>; 1591 utmi-mode = <2>; 1592 ranges; 1593 status = "disabled"; 1594 usb3: usb@48910000 { 1595 compatible = "snps,dwc3"; 1596 reg = <0x48910000 0x17000>; 1597 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1600 interrupt-names = "peripheral", 1601 "host", 1602 "otg"; 1603 maximum-speed = "high-speed"; 1604 dr_mode = "otg"; 1605 snps,dis_u3_susphy_quirk; 1606 snps,dis_u2_susphy_quirk; 1607 }; 1608 }; 1609 1610 elm: elm@48078000 { 1611 compatible = "ti,am3352-elm"; 1612 reg = <0x48078000 0xfc0>; /* device IO registers */ 1613 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1614 ti,hwmods = "elm"; 1615 status = "disabled"; 1616 }; 1617 1618 gpmc: gpmc@50000000 { 1619 compatible = "ti,am3352-gpmc"; 1620 ti,hwmods = "gpmc"; 1621 reg = <0x50000000 0x37c>; /* device IO registers */ 1622 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1623 dmas = <&edma_xbar 4 0>; 1624 dma-names = "rxtx"; 1625 gpmc,num-cs = <8>; 1626 gpmc,num-waitpins = <2>; 1627 #address-cells = <2>; 1628 #size-cells = <1>; 1629 interrupt-controller; 1630 #interrupt-cells = <2>; 1631 gpio-controller; 1632 #gpio-cells = <2>; 1633 status = "disabled"; 1634 }; 1635 1636 atl: atl@4843c000 { 1637 compatible = "ti,dra7-atl"; 1638 reg = <0x4843c000 0x3ff>; 1639 ti,hwmods = "atl"; 1640 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1641 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1642 clocks = <&atl_gfclk_mux>; 1643 clock-names = "fck"; 1644 status = "disabled"; 1645 }; 1646 1647 mcasp1: mcasp@48460000 { 1648 compatible = "ti,dra7-mcasp-audio"; 1649 ti,hwmods = "mcasp1"; 1650 reg = <0x48460000 0x2000>, 1651 <0x45800000 0x1000>; 1652 reg-names = "mpu","dat"; 1653 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1655 interrupt-names = "tx", "rx"; 1656 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 1657 dma-names = "tx", "rx"; 1658 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, 1659 <&mcasp1_ahclkr_mux>; 1660 clock-names = "fck", "ahclkx", "ahclkr"; 1661 status = "disabled"; 1662 }; 1663 1664 mcasp2: mcasp@48464000 { 1665 compatible = "ti,dra7-mcasp-audio"; 1666 ti,hwmods = "mcasp2"; 1667 reg = <0x48464000 0x2000>, 1668 <0x45c00000 0x1000>; 1669 reg-names = "mpu","dat"; 1670 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1672 interrupt-names = "tx", "rx"; 1673 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 1674 dma-names = "tx", "rx"; 1675 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, 1676 <&mcasp2_ahclkr_mux>; 1677 clock-names = "fck", "ahclkx", "ahclkr"; 1678 status = "disabled"; 1679 }; 1680 1681 mcasp3: mcasp@48468000 { 1682 compatible = "ti,dra7-mcasp-audio"; 1683 ti,hwmods = "mcasp3"; 1684 reg = <0x48468000 0x2000>, 1685 <0x46000000 0x1000>; 1686 reg-names = "mpu","dat"; 1687 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1689 interrupt-names = "tx", "rx"; 1690 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 1691 dma-names = "tx", "rx"; 1692 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; 1693 clock-names = "fck", "ahclkx"; 1694 status = "disabled"; 1695 }; 1696 1697 mcasp4: mcasp@4846c000 { 1698 compatible = "ti,dra7-mcasp-audio"; 1699 ti,hwmods = "mcasp4"; 1700 reg = <0x4846c000 0x2000>, 1701 <0x48436000 0x1000>; 1702 reg-names = "mpu","dat"; 1703 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1705 interrupt-names = "tx", "rx"; 1706 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 1707 dma-names = "tx", "rx"; 1708 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; 1709 clock-names = "fck", "ahclkx"; 1710 status = "disabled"; 1711 }; 1712 1713 mcasp5: mcasp@48470000 { 1714 compatible = "ti,dra7-mcasp-audio"; 1715 ti,hwmods = "mcasp5"; 1716 reg = <0x48470000 0x2000>, 1717 <0x4843a000 0x1000>; 1718 reg-names = "mpu","dat"; 1719 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1721 interrupt-names = "tx", "rx"; 1722 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 1723 dma-names = "tx", "rx"; 1724 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; 1725 clock-names = "fck", "ahclkx"; 1726 status = "disabled"; 1727 }; 1728 1729 mcasp6: mcasp@48474000 { 1730 compatible = "ti,dra7-mcasp-audio"; 1731 ti,hwmods = "mcasp6"; 1732 reg = <0x48474000 0x2000>, 1733 <0x4844c000 0x1000>; 1734 reg-names = "mpu","dat"; 1735 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1737 interrupt-names = "tx", "rx"; 1738 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 1739 dma-names = "tx", "rx"; 1740 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; 1741 clock-names = "fck", "ahclkx"; 1742 status = "disabled"; 1743 }; 1744 1745 mcasp7: mcasp@48478000 { 1746 compatible = "ti,dra7-mcasp-audio"; 1747 ti,hwmods = "mcasp7"; 1748 reg = <0x48478000 0x2000>, 1749 <0x48450000 0x1000>; 1750 reg-names = "mpu","dat"; 1751 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1753 interrupt-names = "tx", "rx"; 1754 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 1755 dma-names = "tx", "rx"; 1756 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; 1757 clock-names = "fck", "ahclkx"; 1758 status = "disabled"; 1759 }; 1760 1761 mcasp8: mcasp@4847c000 { 1762 compatible = "ti,dra7-mcasp-audio"; 1763 ti,hwmods = "mcasp8"; 1764 reg = <0x4847c000 0x2000>, 1765 <0x48454000 0x1000>; 1766 reg-names = "mpu","dat"; 1767 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1769 interrupt-names = "tx", "rx"; 1770 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 1771 dma-names = "tx", "rx"; 1772 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; 1773 clock-names = "fck", "ahclkx"; 1774 status = "disabled"; 1775 }; 1776 1777 crossbar_mpu: crossbar@4a002a48 { 1778 compatible = "ti,irq-crossbar"; 1779 reg = <0x4a002a48 0x130>; 1780 interrupt-controller; 1781 interrupt-parent = <&wakeupgen>; 1782 #interrupt-cells = <3>; 1783 ti,max-irqs = <160>; 1784 ti,max-crossbar-sources = <MAX_SOURCES>; 1785 ti,reg-size = <2>; 1786 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1787 ti,irqs-skip = <10 133 139 140>; 1788 ti,irqs-safe-map = <0>; 1789 }; 1790 1791 mac: ethernet@48484000 { 1792 compatible = "ti,dra7-cpsw","ti,cpsw"; 1793 ti,hwmods = "gmac"; 1794 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; 1795 clock-names = "fck", "cpts"; 1796 cpdma_channels = <8>; 1797 ale_entries = <1024>; 1798 bd_ram_size = <0x2000>; 1799 mac_control = <0x20>; 1800 slaves = <2>; 1801 active_slave = <0>; 1802 cpts_clock_mult = <0x784CFE14>; 1803 cpts_clock_shift = <29>; 1804 reg = <0x48484000 0x1000 1805 0x48485200 0x2E00>; 1806 #address-cells = <1>; 1807 #size-cells = <1>; 1808 1809 /* 1810 * Do not allow gating of cpsw clock as workaround 1811 * for errata i877. Keeping internal clock disabled 1812 * causes the device switching characteristics 1813 * to degrade over time and eventually fail to meet 1814 * the data manual delay time/skew specs. 1815 */ 1816 ti,no-idle; 1817 1818 /* 1819 * rx_thresh_pend 1820 * rx_pend 1821 * tx_pend 1822 * misc_pend 1823 */ 1824 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1828 ranges; 1829 syscon = <&scm_conf>; 1830 status = "disabled"; 1831 1832 davinci_mdio: mdio@48485000 { 1833 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 ti,hwmods = "davinci_mdio"; 1837 bus_freq = <1000000>; 1838 reg = <0x48485000 0x100>; 1839 }; 1840 1841 cpsw_emac0: slave@48480200 { 1842 /* Filled in by U-Boot */ 1843 mac-address = [ 00 00 00 00 00 00 ]; 1844 }; 1845 1846 cpsw_emac1: slave@48480300 { 1847 /* Filled in by U-Boot */ 1848 mac-address = [ 00 00 00 00 00 00 ]; 1849 }; 1850 1851 phy_sel: cpsw-phy-sel@4a002554 { 1852 compatible = "ti,dra7xx-cpsw-phy-sel"; 1853 reg= <0x4a002554 0x4>; 1854 reg-names = "gmii-sel"; 1855 }; 1856 }; 1857 1858 dcan1: can@481cc000 { 1859 compatible = "ti,dra7-d_can"; 1860 ti,hwmods = "dcan1"; 1861 reg = <0x4ae3c000 0x2000>; 1862 syscon-raminit = <&scm_conf 0x558 0>; 1863 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1864 clocks = <&dcan1_sys_clk_mux>; 1865 status = "disabled"; 1866 }; 1867 1868 dcan2: can@481d0000 { 1869 compatible = "ti,dra7-d_can"; 1870 ti,hwmods = "dcan2"; 1871 reg = <0x48480000 0x2000>; 1872 syscon-raminit = <&scm_conf 0x558 1>; 1873 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1874 clocks = <&sys_clkin1>; 1875 status = "disabled"; 1876 }; 1877 1878 dss: dss@58000000 { 1879 compatible = "ti,dra7-dss"; 1880 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 1881 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 1882 status = "disabled"; 1883 ti,hwmods = "dss_core"; 1884 /* CTRL_CORE_DSS_PLL_CONTROL */ 1885 syscon-pll-ctrl = <&scm_conf 0x538>; 1886 #address-cells = <1>; 1887 #size-cells = <1>; 1888 ranges; 1889 1890 dispc@58001000 { 1891 compatible = "ti,dra7-dispc"; 1892 reg = <0x58001000 0x1000>; 1893 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1894 ti,hwmods = "dss_dispc"; 1895 clocks = <&dss_dss_clk>; 1896 clock-names = "fck"; 1897 /* CTRL_CORE_SMA_SW_1 */ 1898 syscon-pol = <&scm_conf 0x534>; 1899 }; 1900 1901 hdmi: encoder@58060000 { 1902 compatible = "ti,dra7-hdmi"; 1903 reg = <0x58040000 0x200>, 1904 <0x58040200 0x80>, 1905 <0x58040300 0x80>, 1906 <0x58060000 0x19000>; 1907 reg-names = "wp", "pll", "phy", "core"; 1908 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1909 status = "disabled"; 1910 ti,hwmods = "dss_hdmi"; 1911 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; 1912 clock-names = "fck", "sys_clk"; 1913 }; 1914 }; 1915 1916 epwmss0: epwmss@4843e000 { 1917 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1918 reg = <0x4843e000 0x30>; 1919 ti,hwmods = "epwmss0"; 1920 #address-cells = <1>; 1921 #size-cells = <1>; 1922 status = "disabled"; 1923 ranges; 1924 1925 ehrpwm0: pwm@4843e200 { 1926 compatible = "ti,dra746-ehrpwm", 1927 "ti,am3352-ehrpwm"; 1928 #pwm-cells = <3>; 1929 reg = <0x4843e200 0x80>; 1930 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 1931 clock-names = "tbclk", "fck"; 1932 status = "disabled"; 1933 }; 1934 1935 ecap0: ecap@4843e100 { 1936 compatible = "ti,dra746-ecap", 1937 "ti,am3352-ecap"; 1938 #pwm-cells = <3>; 1939 reg = <0x4843e100 0x80>; 1940 clocks = <&l4_root_clk_div>; 1941 clock-names = "fck"; 1942 status = "disabled"; 1943 }; 1944 }; 1945 1946 epwmss1: epwmss@48440000 { 1947 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1948 reg = <0x48440000 0x30>; 1949 ti,hwmods = "epwmss1"; 1950 #address-cells = <1>; 1951 #size-cells = <1>; 1952 status = "disabled"; 1953 ranges; 1954 1955 ehrpwm1: pwm@48440200 { 1956 compatible = "ti,dra746-ehrpwm", 1957 "ti,am3352-ehrpwm"; 1958 #pwm-cells = <3>; 1959 reg = <0x48440200 0x80>; 1960 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 1961 clock-names = "tbclk", "fck"; 1962 status = "disabled"; 1963 }; 1964 1965 ecap1: ecap@48440100 { 1966 compatible = "ti,dra746-ecap", 1967 "ti,am3352-ecap"; 1968 #pwm-cells = <3>; 1969 reg = <0x48440100 0x80>; 1970 clocks = <&l4_root_clk_div>; 1971 clock-names = "fck"; 1972 status = "disabled"; 1973 }; 1974 }; 1975 1976 epwmss2: epwmss@48442000 { 1977 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1978 reg = <0x48442000 0x30>; 1979 ti,hwmods = "epwmss2"; 1980 #address-cells = <1>; 1981 #size-cells = <1>; 1982 status = "disabled"; 1983 ranges; 1984 1985 ehrpwm2: pwm@48442200 { 1986 compatible = "ti,dra746-ehrpwm", 1987 "ti,am3352-ehrpwm"; 1988 #pwm-cells = <3>; 1989 reg = <0x48442200 0x80>; 1990 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 1991 clock-names = "tbclk", "fck"; 1992 status = "disabled"; 1993 }; 1994 1995 ecap2: ecap@48442100 { 1996 compatible = "ti,dra746-ecap", 1997 "ti,am3352-ecap"; 1998 #pwm-cells = <3>; 1999 reg = <0x48442100 0x80>; 2000 clocks = <&l4_root_clk_div>; 2001 clock-names = "fck"; 2002 status = "disabled"; 2003 }; 2004 }; 2005 2006 aes1: aes@4b500000 { 2007 compatible = "ti,omap4-aes"; 2008 ti,hwmods = "aes1"; 2009 reg = <0x4b500000 0xa0>; 2010 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2011 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 2012 dma-names = "tx", "rx"; 2013 clocks = <&l3_iclk_div>; 2014 clock-names = "fck"; 2015 }; 2016 2017 aes2: aes@4b700000 { 2018 compatible = "ti,omap4-aes"; 2019 ti,hwmods = "aes2"; 2020 reg = <0x4b700000 0xa0>; 2021 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 2022 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 2023 dma-names = "tx", "rx"; 2024 clocks = <&l3_iclk_div>; 2025 clock-names = "fck"; 2026 }; 2027 2028 des: des@480a5000 { 2029 compatible = "ti,omap4-des"; 2030 ti,hwmods = "des"; 2031 reg = <0x480a5000 0xa0>; 2032 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 2033 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; 2034 dma-names = "tx", "rx"; 2035 clocks = <&l3_iclk_div>; 2036 clock-names = "fck"; 2037 }; 2038 2039 sham: sham@53100000 { 2040 compatible = "ti,omap5-sham"; 2041 ti,hwmods = "sham"; 2042 reg = <0x4b101000 0x300>; 2043 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 2044 dmas = <&edma_xbar 119 0>; 2045 dma-names = "rx"; 2046 clocks = <&l3_iclk_div>; 2047 clock-names = "fck"; 2048 }; 2049 2050 rng: rng@48090000 { 2051 compatible = "ti,omap4-rng"; 2052 ti,hwmods = "rng"; 2053 reg = <0x48090000 0x2000>; 2054 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2055 clocks = <&l3_iclk_div>; 2056 clock-names = "fck"; 2057 }; 2058 2059 ipu1: ipu@58820000 { 2060 compatible = "ti,dra7-ipu"; 2061 reg = <0x58820000 0x10000>; 2062 reg-names = "l2ram"; 2063 ti,hwmods = "ipu1"; 2064 resets = <&ipu1_rst 0>, <&ipu1_rst 1>, <&ipu1_rst 2>; 2065 iommus = <&mmu_ipu1>; 2066 ti,rproc-standby-info = <0x4a005520>; 2067 timers = <&timer11>; 2068 watchdog-timers = <&timer7>, <&timer8>; 2069 }; 2070 2071 ipu2: ipu@55020000 { 2072 compatible = "ti,dra7-ipu"; 2073 reg = <0x55020000 0x10000>; 2074 reg-names = "l2ram"; 2075 ti,hwmods = "ipu2"; 2076 resets = <&ipu2_rst 0>, <&ipu2_rst 1>, <&ipu2_rst 2>; 2077 iommus = <&mmu_ipu2>; 2078 ti,rproc-standby-info = <0x4a008920>; 2079 timers = <&timer3>; 2080 watchdog-timers = <&timer4>, <&timer9>; 2081 }; 2082 }; 2083 2084 thermal_zones: thermal-zones { 2085 #include "omap4-cpu-thermal.dtsi" 2086 #include "omap5-gpu-thermal.dtsi" 2087 #include "omap5-core-thermal.dtsi" 2088 #include "dra7-dspeve-thermal.dtsi" 2089 #include "dra7-iva-thermal.dtsi" 2090 }; 2091 2092}; 2093 2094&cpu_thermal { 2095 polling-delay = <500>; /* milliseconds */ 2096 coefficients = <0 2000>; 2097}; 2098 2099&gpu_thermal { 2100 coefficients = <0 2000>; 2101}; 2102 2103&core_thermal { 2104 coefficients = <0 2000>; 2105}; 2106 2107&dspeve_thermal { 2108 coefficients = <0 2000>; 2109}; 2110 2111&iva_thermal { 2112 coefficients = <0 2000>; 2113}; 2114 2115&cpu_crit { 2116 temperature = <120000>; /* milli Celsius */ 2117}; 2118 2119#include "dra7xx-clocks.dtsi" 2120