1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5/dts-v1/; 6 7#include "dra72x.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clk/ti-dra7-atl.h> 10 11/ { 12 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; 13 14 aliases { 15 display0 = &hdmi0; 16 }; 17 18 chosen { 19 stdout-path = &uart1; 20 }; 21 22 evm_12v0: fixedregulator-evm12v0 { 23 /* main supply */ 24 compatible = "regulator-fixed"; 25 regulator-name = "evm_12v0"; 26 regulator-min-microvolt = <12000000>; 27 regulator-max-microvolt = <12000000>; 28 regulator-always-on; 29 regulator-boot-on; 30 }; 31 32 evm_5v0: fixedregulator-evm5v0 { 33 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ 34 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ 35 compatible = "regulator-fixed"; 36 regulator-name = "evm_5v0"; 37 regulator-min-microvolt = <5000000>; 38 regulator-max-microvolt = <5000000>; 39 vin-supply = <&evm_12v0>; 40 regulator-always-on; 41 regulator-boot-on; 42 }; 43 44 vsys_3v3: fixedregulator-vsys3v3 { 45 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ 46 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ 47 compatible = "regulator-fixed"; 48 regulator-name = "vsys_3v3"; 49 regulator-min-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>; 51 vin-supply = <&evm_12v0>; 52 regulator-always-on; 53 regulator-boot-on; 54 }; 55 56 evm_3v3_sw: fixedregulator-evm_3v3 { 57 /* TPS22965DSG */ 58 compatible = "regulator-fixed"; 59 regulator-name = "evm_3v3"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 vin-supply = <&vsys_3v3>; 63 regulator-always-on; 64 regulator-boot-on; 65 }; 66 67 aic_dvdd: fixedregulator-aic_dvdd { 68 /* TPS77018DBVT */ 69 compatible = "regulator-fixed"; 70 regulator-name = "aic_dvdd"; 71 vin-supply = <&evm_3v3_sw>; 72 regulator-min-microvolt = <1800000>; 73 regulator-max-microvolt = <1800000>; 74 }; 75 76 evm_3v3_sd: fixedregulator-sd { 77 compatible = "regulator-fixed"; 78 regulator-name = "evm_3v3_sd"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 vin-supply = <&evm_3v3_sw>; 82 enable-active-high; 83 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 84 }; 85 86 extcon_usb1: extcon_usb1 { 87 compatible = "linux,extcon-usb-gpio"; 88 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 89 }; 90 91 extcon_usb2: extcon_usb2 { 92 compatible = "linux,extcon-usb-gpio"; 93 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 94 }; 95 96 hdmi0: connector { 97 compatible = "hdmi-connector"; 98 label = "hdmi"; 99 100 type = "a"; 101 102 port { 103 hdmi_connector_in: endpoint { 104 remote-endpoint = <&tpd12s015_out>; 105 }; 106 }; 107 }; 108 109 tpd12s015: encoder { 110 compatible = "ti,tpd12s015"; 111 112 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ 113 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ 114 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 115 116 ports { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 port@0 { 121 reg = <0>; 122 123 tpd12s015_in: endpoint { 124 remote-endpoint = <&hdmi_out>; 125 }; 126 }; 127 128 port@1 { 129 reg = <1>; 130 131 tpd12s015_out: endpoint { 132 remote-endpoint = <&hdmi_connector_in>; 133 }; 134 }; 135 }; 136 }; 137 138 sound0: sound0 { 139 compatible = "simple-audio-card"; 140 simple-audio-card,name = "DRA7xx-EVM"; 141 simple-audio-card,widgets = 142 "Headphone", "Headphone Jack", 143 "Line", "Line Out", 144 "Microphone", "Mic Jack", 145 "Line", "Line In"; 146 simple-audio-card,routing = 147 "Headphone Jack", "HPLOUT", 148 "Headphone Jack", "HPROUT", 149 "Line Out", "LLOUT", 150 "Line Out", "RLOUT", 151 "MIC3L", "Mic Jack", 152 "MIC3R", "Mic Jack", 153 "Mic Jack", "Mic Bias", 154 "LINE1L", "Line In", 155 "LINE1R", "Line In"; 156 simple-audio-card,format = "dsp_b"; 157 simple-audio-card,bitclock-master = <&sound0_master>; 158 simple-audio-card,frame-master = <&sound0_master>; 159 simple-audio-card,bitclock-inversion; 160 161 sound0_master: simple-audio-card,cpu { 162 sound-dai = <&mcasp3>; 163 system-clock-frequency = <5644800>; 164 }; 165 166 simple-audio-card,codec { 167 sound-dai = <&tlv320aic3106>; 168 clocks = <&atl_clkin2_ck>; 169 }; 170 }; 171}; 172 173&dra7_pmx_core { 174 mmc1_pins_default: mmc1_pins_default { 175 pinctrl-single,pins = < 176 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ 177 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 178 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 179 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 180 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 181 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 182 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 183 >; 184 }; 185 186 mmc2_pins_default: mmc2_pins_default { 187 pinctrl-single,pins = < 188 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 189 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 190 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 191 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 192 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 193 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 194 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 195 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 196 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 197 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 198 >; 199 }; 200 201 dcan1_pins_default: dcan1_pins_default { 202 pinctrl-single,pins = < 203 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 204 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 205 >; 206 }; 207 208 dcan1_pins_sleep: dcan1_pins_sleep { 209 pinctrl-single,pins = < 210 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 211 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 212 >; 213 }; 214}; 215 216&i2c1 { 217 status = "okay"; 218 clock-frequency = <400000>; 219 220 pcf_lcd: gpio@20 { 221 compatible = "nxp,pcf8575"; 222 reg = <0x20>; 223 gpio-controller; 224 #gpio-cells = <2>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 }; 228 229 pcf_gpio_21: gpio@21 { 230 compatible = "ti,pcf8575", "nxp,pcf8575"; 231 reg = <0x21>; 232 lines-initial-states = <0x1408>; 233 gpio-controller; 234 #gpio-cells = <2>; 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 }; 238 239 tlv320aic3106: tlv320aic3106@19 { 240 #sound-dai-cells = <0>; 241 compatible = "ti,tlv320aic3106"; 242 reg = <0x19>; 243 adc-settle-ms = <40>; 244 ai3x-micbias-vg = <1>; /* 2.0V */ 245 status = "okay"; 246 247 /* Regulators */ 248 AVDD-supply = <&evm_3v3_sw>; 249 IOVDD-supply = <&evm_3v3_sw>; 250 DRVDD-supply = <&evm_3v3_sw>; 251 DVDD-supply = <&aic_dvdd>; 252 }; 253}; 254 255&i2c5 { 256 status = "okay"; 257 clock-frequency = <400000>; 258 259 pcf_hdmi: pcf8575@26 { 260 compatible = "ti,pcf8575", "nxp,pcf8575"; 261 reg = <0x26>; 262 gpio-controller; 263 #gpio-cells = <2>; 264 /* 265 * initial state is used here to keep the mdio interface 266 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and 267 * VIN2_S0 driven high otherwise Ethernet stops working 268 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 269 */ 270 lines-initial-states = <0x0f2b>; 271 272 hdmi-audio-hog { 273 /* vin6_sel_s0: high: VIN6, low: audio */ 274 gpio-hog; 275 gpios = <1 GPIO_ACTIVE_HIGH>; 276 output-low; 277 line-name = "vin6_sel_s0"; 278 }; 279 }; 280}; 281 282&uart1 { 283 status = "okay"; 284 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 285 <&dra7_pmx_core 0x3e0>; 286}; 287 288&elm { 289 status = "okay"; 290}; 291 292&gpmc { 293 /* 294 * For the existing IOdelay configuration via U-Boot we don't 295 * support NAND on dra72-evm. Keep it disabled. Enabling it 296 * requires a different configuration by U-Boot. 297 */ 298 status = "disabled"; 299 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 300 nand@0,0 { 301 /* To use NAND, DIP switch SW5 must be set like so: 302 * SW5.1 (NAND_SELn) = ON (LOW) 303 * SW5.9 (GPMC_WPN) = OFF (HIGH) 304 */ 305 compatible = "ti,omap2-nand"; 306 reg = <0 0 4>; /* device IO registers */ 307 interrupt-parent = <&gpmc>; 308 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 309 <1 IRQ_TYPE_NONE>; /* termcount */ 310 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ 311 ti,nand-xfer-type = "prefetch-dma"; 312 ti,nand-ecc-opt = "bch8"; 313 ti,elm-id = <&elm>; 314 nand-bus-width = <16>; 315 gpmc,device-width = <2>; 316 gpmc,sync-clk-ps = <0>; 317 gpmc,cs-on-ns = <0>; 318 gpmc,cs-rd-off-ns = <80>; 319 gpmc,cs-wr-off-ns = <80>; 320 gpmc,adv-on-ns = <0>; 321 gpmc,adv-rd-off-ns = <60>; 322 gpmc,adv-wr-off-ns = <60>; 323 gpmc,we-on-ns = <10>; 324 gpmc,we-off-ns = <50>; 325 gpmc,oe-on-ns = <4>; 326 gpmc,oe-off-ns = <40>; 327 gpmc,access-ns = <40>; 328 gpmc,wr-access-ns = <80>; 329 gpmc,rd-cycle-ns = <80>; 330 gpmc,wr-cycle-ns = <80>; 331 gpmc,bus-turnaround-ns = <0>; 332 gpmc,cycle2cycle-delay-ns = <0>; 333 gpmc,clk-activation-ns = <0>; 334 gpmc,wr-data-mux-bus-ns = <0>; 335 /* MTD partition table */ 336 /* All SPL-* partitions are sized to minimal length 337 * which can be independently programmable. For 338 * NAND flash this is equal to size of erase-block */ 339 #address-cells = <1>; 340 #size-cells = <1>; 341 partition@0 { 342 label = "NAND.SPL"; 343 reg = <0x00000000 0x00020000>; 344 }; 345 partition@1 { 346 label = "NAND.SPL.backup1"; 347 reg = <0x00020000 0x00020000>; 348 }; 349 partition@2 { 350 label = "NAND.SPL.backup2"; 351 reg = <0x00040000 0x00020000>; 352 }; 353 partition@3 { 354 label = "NAND.SPL.backup3"; 355 reg = <0x00060000 0x00020000>; 356 }; 357 partition@4 { 358 label = "NAND.u-boot-spl-os"; 359 reg = <0x00080000 0x00040000>; 360 }; 361 partition@5 { 362 label = "NAND.u-boot"; 363 reg = <0x000c0000 0x00100000>; 364 }; 365 partition@6 { 366 label = "NAND.u-boot-env"; 367 reg = <0x001c0000 0x00020000>; 368 }; 369 partition@7 { 370 label = "NAND.u-boot-env.backup1"; 371 reg = <0x001e0000 0x00020000>; 372 }; 373 partition@8 { 374 label = "NAND.kernel"; 375 reg = <0x00200000 0x00800000>; 376 }; 377 partition@9 { 378 label = "NAND.file-system"; 379 reg = <0x00a00000 0x0f600000>; 380 }; 381 }; 382}; 383 384&omap_dwc3_1 { 385 extcon = <&extcon_usb1>; 386}; 387 388&omap_dwc3_2 { 389 extcon = <&extcon_usb2>; 390}; 391 392&usb1 { 393 dr_mode = "otg"; 394 extcon = <&extcon_usb1>; 395}; 396 397&usb2 { 398 dr_mode = "host"; 399}; 400 401&mmc1 { 402 status = "okay"; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&mmc1_pins_default>; 405 vmmc-supply = <&evm_3v3_sd>; 406 bus-width = <4>; 407 /* 408 * SDCD signal is not being used here - using the fact that GPIO mode 409 * is a viable alternative 410 */ 411 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 412 max-frequency = <192000000>; 413}; 414 415&mmc2 { 416 /* SW5-3 in ON position */ 417 status = "okay"; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&mmc2_pins_default>; 420 bus-width = <8>; 421 ti,non-removable; 422 max-frequency = <192000000>; 423}; 424 425&mac { 426 status = "okay"; 427}; 428 429&dcan1 { 430 status = "okay"; 431 pinctrl-names = "default", "sleep", "active"; 432 pinctrl-0 = <&dcan1_pins_sleep>; 433 pinctrl-1 = <&dcan1_pins_sleep>; 434 pinctrl-2 = <&dcan1_pins_default>; 435}; 436 437&qspi { 438 status = "okay"; 439 440 spi-max-frequency = <76800000>; 441 flash@0 { 442 compatible = "s25fl256s1"; 443 spi-max-frequency = <76800000>; 444 reg = <0>; 445 spi-tx-bus-width = <1>; 446 spi-rx-bus-width = <4>; 447 #address-cells = <1>; 448 #size-cells = <1>; 449 450 /* MTD partition table. 451 * The ROM checks the first four physical blocks 452 * for a valid file to boot and the flash here is 453 * 64KiB block size. 454 */ 455 partition@0 { 456 label = "QSPI.SPL"; 457 reg = <0x00000000 0x00010000>; 458 }; 459 partition@1 { 460 label = "QSPI.SPL.backup1"; 461 reg = <0x00010000 0x00010000>; 462 }; 463 partition@2 { 464 label = "QSPI.SPL.backup2"; 465 reg = <0x00020000 0x00010000>; 466 }; 467 partition@3 { 468 label = "QSPI.SPL.backup3"; 469 reg = <0x00030000 0x00010000>; 470 }; 471 partition@4 { 472 label = "QSPI.u-boot"; 473 reg = <0x00040000 0x00100000>; 474 }; 475 partition@5 { 476 label = "QSPI.u-boot-spl-os"; 477 reg = <0x00140000 0x00080000>; 478 }; 479 partition@6 { 480 label = "QSPI.u-boot-env"; 481 reg = <0x001c0000 0x00010000>; 482 }; 483 partition@7 { 484 label = "QSPI.u-boot-env.backup1"; 485 reg = <0x001d0000 0x0010000>; 486 }; 487 partition@8 { 488 label = "QSPI.kernel"; 489 reg = <0x001e0000 0x0800000>; 490 }; 491 partition@9 { 492 label = "QSPI.file-system"; 493 reg = <0x009e0000 0x01620000>; 494 }; 495 }; 496}; 497 498&dss { 499 status = "okay"; 500}; 501 502&hdmi { 503 status = "okay"; 504 505 port { 506 hdmi_out: endpoint { 507 remote-endpoint = <&tpd12s015_in>; 508 }; 509 }; 510}; 511 512&atl { 513 assigned-clocks = <&abe_dpll_sys_clk_mux>, 514 <&atl_gfclk_mux>, 515 <&dpll_abe_ck>, 516 <&dpll_abe_m2x2_ck>, 517 <&atl_clkin2_ck>; 518 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; 519 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; 520 521 status = "okay"; 522 523 atl2 { 524 bws = <DRA7_ATL_WS_MCASP2_FSX>; 525 aws = <DRA7_ATL_WS_MCASP3_FSX>; 526 }; 527}; 528 529&mcasp3 { 530 #sound-dai-cells = <0>; 531 532 assigned-clocks = <&mcasp3_ahclkx_mux>; 533 assigned-clock-parents = <&atl_clkin2_ck>; 534 535 status = "okay"; 536 537 op-mode = <0>; /* MCASP_IIS_MODE */ 538 tdm-slots = <2>; 539 /* 4 serializer */ 540 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 541 1 2 0 0 542 >; 543 tx-num-evt = <32>; 544 rx-num-evt = <32>; 545}; 546 547&mailbox5 { 548 status = "okay"; 549 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { 550 status = "okay"; 551 }; 552 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { 553 status = "okay"; 554 }; 555}; 556 557&mailbox6 { 558 status = "okay"; 559 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { 560 status = "okay"; 561 }; 562}; 563 564&pcie1_rc { 565 status = "okay"; 566}; 567