1 /*
2 * COM1 NS16550 support
3 * originally from linux source (arch/powerpc/boot/ns16550.c)
4 * modified to use CONFIG_SYS_ISA_MEM and new defines
5 */
6
7 #include <clock_legacy.h>
8 #include <config.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <log.h>
13 #include <ns16550.h>
14 #include <reset.h>
15 #include <spl.h>
16 #include <watchdog.h>
17 #include <asm/global_data.h>
18 #include <linux/err.h>
19 #include <linux/types.h>
20 #include <asm/io.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
25 #define UART_MCRVAL (UART_MCR_DTR | \
26 UART_MCR_RTS) /* RTS/DTR */
27
28 #if !CONFIG_IS_ENABLED(DM_SERIAL)
29 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
30 #define serial_out(x, y) outb(x, (ulong)y)
31 #define serial_in(y) inb((ulong)y)
32 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
33 #define serial_out(x, y) out_be32(y, x)
34 #define serial_in(y) in_be32(y)
35 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
36 #define serial_out(x, y) out_le32(y, x)
37 #define serial_in(y) in_le32(y)
38 #else
39 #define serial_out(x, y) writeb(x, y)
40 #define serial_in(y) readb(y)
41 #endif
42 #endif /* !CONFIG_DM_SERIAL */
43
44 #if defined(CONFIG_ARCH_KEYSTONE)
45 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
46 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
47 #undef UART_MCRVAL
48 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
49 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
50 #else
51 #define UART_MCRVAL (UART_MCR_RTS)
52 #endif
53 #endif
54
55 #ifndef CFG_SYS_NS16550_IER
56 #define CFG_SYS_NS16550_IER 0x00
57 #endif /* CFG_SYS_NS16550_IER */
58
serial_out_shift(void * addr,int shift,int value)59 static inline void serial_out_shift(void *addr, int shift, int value)
60 {
61 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
62 outb(value, (ulong)addr);
63 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
64 out_le32(addr, value);
65 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
66 out_be32(addr, value);
67 #elif defined(CONFIG_SYS_NS16550_MEM32)
68 writel(value, addr);
69 #elif defined(CONFIG_SYS_BIG_ENDIAN)
70 writeb(value, addr + (1 << shift) - 1);
71 #else
72 writeb(value, addr);
73 #endif
74 }
75
serial_in_shift(void * addr,int shift)76 static inline int serial_in_shift(void *addr, int shift)
77 {
78 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
79 return inb((ulong)addr);
80 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
81 return in_le32(addr);
82 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
83 return in_be32(addr);
84 #elif defined(CONFIG_SYS_NS16550_MEM32)
85 return readl(addr);
86 #elif defined(CONFIG_SYS_BIG_ENDIAN)
87 return readb(addr + (1 << shift) - 1);
88 #else
89 return readb(addr);
90 #endif
91 }
92
93 #if CONFIG_IS_ENABLED(DM_SERIAL)
94
95 #ifndef CFG_SYS_NS16550_CLK
96 #define CFG_SYS_NS16550_CLK 0
97 #endif
98
99 /*
100 * Use this #ifdef for now since many platforms don't define in(), out(),
101 * out_le32(), etc. but we don't have #defines to indicate this.
102 *
103 * TODO(sjg@chromium.org): Add CONFIG options to indicate what I/O is available
104 * on a platform
105 */
106 #ifdef CONFIG_NS16550_DYNAMIC
serial_out_dynamic(struct ns16550_plat * plat,u8 * addr,int value)107 static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
108 int value)
109 {
110 if (plat->flags & NS16550_FLAG_IO) {
111 outb(value, addr);
112 } else if (plat->reg_width == 4) {
113 if (plat->flags & NS16550_FLAG_ENDIAN) {
114 if (plat->flags & NS16550_FLAG_BE)
115 out_be32((u32 *)addr, value);
116 else
117 out_le32((u32 *)addr, value);
118 } else {
119 writel(value, addr);
120 }
121 } else if (plat->flags & NS16550_FLAG_BE) {
122 writeb(value, addr + (1 << plat->reg_shift) - 1);
123 } else {
124 writeb(value, addr);
125 }
126 }
127
serial_in_dynamic(struct ns16550_plat * plat,u8 * addr)128 static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
129 {
130 if (plat->flags & NS16550_FLAG_IO) {
131 return inb(addr);
132 } else if (plat->reg_width == 4) {
133 if (plat->flags & NS16550_FLAG_ENDIAN) {
134 if (plat->flags & NS16550_FLAG_BE)
135 return in_be32((u32 *)addr);
136 else
137 return in_le32((u32 *)addr);
138 } else {
139 return readl(addr);
140 }
141 } else if (plat->flags & NS16550_FLAG_BE) {
142 return readb(addr + (1 << plat->reg_shift) - 1);
143 } else {
144 return readb(addr);
145 }
146 }
147 #else
serial_out_dynamic(struct ns16550_plat * plat,u8 * addr,int value)148 static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
149 int value)
150 {
151 }
152
serial_in_dynamic(struct ns16550_plat * plat,u8 * addr)153 static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
154 {
155 return 0;
156 }
157
158 #endif /* CONFIG_NS16550_DYNAMIC */
159
ns16550_writeb(struct ns16550 * port,int offset,int value)160 void ns16550_writeb(struct ns16550 *port, int offset, int value)
161 {
162 struct ns16550_plat *plat = port->plat;
163 unsigned char *addr;
164
165 offset *= 1 << plat->reg_shift;
166 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
167
168 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
169 serial_out_dynamic(plat, addr, value);
170 else
171 serial_out_shift(addr, plat->reg_shift, value);
172 }
173
ns16550_readb(struct ns16550 * port,int offset)174 static int ns16550_readb(struct ns16550 *port, int offset)
175 {
176 struct ns16550_plat *plat = port->plat;
177 unsigned char *addr;
178
179 offset *= 1 << plat->reg_shift;
180 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
181
182 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
183 return serial_in_dynamic(plat, addr);
184 else
185 return serial_in_shift(addr, plat->reg_shift);
186 }
187
ns16550_getfcr(struct ns16550 * port)188 static u32 ns16550_getfcr(struct ns16550 *port)
189 {
190 struct ns16550_plat *plat = port->plat;
191
192 return plat->fcr;
193 }
194
195 #else
ns16550_getfcr(struct ns16550 * port)196 static u32 ns16550_getfcr(struct ns16550 *port)
197 {
198 return UART_FCR_DEFVAL;
199 }
200 #endif
201
ns16550_calc_divisor(struct ns16550 * port,int clock,int baudrate)202 int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate)
203 {
204 const unsigned int mode_x_div = 16;
205
206 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
207 }
208
ns16550_setbrg(struct ns16550 * com_port,int baud_divisor)209 void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
210 {
211 /* to keep serial format, read lcr before writing BKSE */
212 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
213
214 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
215 serial_out(baud_divisor & 0xff, &com_port->dll);
216 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
217 serial_out(lcr_val, &com_port->lcr);
218 }
219
ns16550_init(struct ns16550 * com_port,int baud_divisor)220 void ns16550_init(struct ns16550 *com_port, int baud_divisor)
221 {
222 #if defined(CONFIG_XPL_BUILD) && defined(CONFIG_OMAP34XX)
223 /*
224 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
225 * before SPL starts only THRE bit is set. We have to empty the
226 * transmitter before initialization starts.
227 */
228 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
229 == UART_LSR_THRE) {
230 if (baud_divisor != -1)
231 ns16550_setbrg(com_port, baud_divisor);
232 else {
233 // Re-use old baud rate divisor to flush transmit reg.
234 const int dll = serial_in(&com_port->dll);
235 const int dlm = serial_in(&com_port->dlm);
236 const int divisor = dll | (dlm << 8);
237 ns16550_setbrg(com_port, divisor);
238 }
239 serial_out(0, &com_port->mdr1);
240 }
241 #endif
242
243 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
244 ;
245
246 serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
247 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL)
248 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
249 #endif
250
251 serial_out(UART_MCRVAL, &com_port->mcr);
252 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
253 /* initialize serial config to 8N1 before writing baudrate */
254 serial_out(UART_LCRVAL, &com_port->lcr);
255 if (baud_divisor != -1)
256 ns16550_setbrg(com_port, baud_divisor);
257 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \
258 defined(CONFIG_OMAP_SERIAL)
259 /* /16 is proper to hit 115200 with 48MHz */
260 serial_out(0, &com_port->mdr1);
261 #endif
262 #if defined(CONFIG_ARCH_KEYSTONE)
263 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
264 #endif
265 }
266
267 #if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
ns16550_reinit(struct ns16550 * com_port,int baud_divisor)268 void ns16550_reinit(struct ns16550 *com_port, int baud_divisor)
269 {
270 serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
271 ns16550_setbrg(com_port, 0);
272 serial_out(UART_MCRVAL, &com_port->mcr);
273 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
274 ns16550_setbrg(com_port, baud_divisor);
275 }
276 #endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
277
ns16550_putc(struct ns16550 * com_port,char c)278 void ns16550_putc(struct ns16550 *com_port, char c)
279 {
280 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
281 ;
282 serial_out(c, &com_port->thr);
283
284 /*
285 * Call schedule() upon newline. This is done here in putc
286 * since the environment code uses a single puts() to print the complete
287 * environment upon "printenv". So we can't put this schedule call
288 * in puts().
289 */
290 if (c == '\n')
291 schedule();
292 }
293
294 #if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
ns16550_getc(struct ns16550 * com_port)295 char ns16550_getc(struct ns16550 *com_port)
296 {
297 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0)
298 schedule();
299
300 return serial_in(&com_port->rbr);
301 }
302
ns16550_tstc(struct ns16550 * com_port)303 int ns16550_tstc(struct ns16550 *com_port)
304 {
305 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
306 }
307
308 #endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
309
310 #ifdef CONFIG_DEBUG_UART_NS16550
311
312 #include <debug_uart.h>
313
_debug_uart_init(void)314 static inline void _debug_uart_init(void)
315 {
316 struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
317 int baud_divisor;
318
319 /* Wait until tx buffer is empty */
320 while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT))
321 ;
322
323 /*
324 * We copy the code from above because it is already horribly messy.
325 * Trying to refactor to nicely remove the duplication doesn't seem
326 * feasible. The better fix is to move all users of this driver to
327 * driver model.
328 */
329 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
330 CONFIG_BAUDRATE);
331 serial_dout(&com_port->ier, CFG_SYS_NS16550_IER);
332 serial_dout(&com_port->mcr, UART_MCRVAL);
333 serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
334
335 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
336 serial_dout(&com_port->dll, baud_divisor & 0xff);
337 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
338 serial_dout(&com_port->lcr, UART_LCRVAL);
339 }
340
NS16550_read_baud_divisor(struct ns16550 * com_port)341 static inline int NS16550_read_baud_divisor(struct ns16550 *com_port)
342 {
343 int ret;
344
345 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
346 ret = serial_din(&com_port->dll) & 0xff;
347 ret |= (serial_din(&com_port->dlm) & 0xff) << 8;
348 serial_dout(&com_port->lcr, UART_LCRVAL);
349
350 return ret;
351 }
352
_debug_uart_putc(int ch)353 static inline void _debug_uart_putc(int ch)
354 {
355 struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
356
357 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
358 #ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED
359 if (!NS16550_read_baud_divisor(com_port))
360 return;
361 #endif
362 }
363 serial_dout(&com_port->thr, ch);
364 }
365
366 DEBUG_UART_FUNCS
367
368 #endif
369
370 #if CONFIG_IS_ENABLED(DM_SERIAL)
ns16550_serial_putc(struct udevice * dev,const char ch)371 int ns16550_serial_putc(struct udevice *dev, const char ch)
372 {
373 struct ns16550 *const com_port = dev_get_priv(dev);
374
375 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE))
376 return -EAGAIN;
377 serial_out(ch, &com_port->thr);
378
379 /*
380 * Call schedule() upon newline. This is done here in putc
381 * since the environment code uses a single puts() to print the complete
382 * environment upon "printenv". So we can't put this schedule call
383 * in puts().
384 */
385 if (ch == '\n')
386 schedule();
387
388 return 0;
389 }
390
ns16550_serial_pending(struct udevice * dev,bool input)391 int ns16550_serial_pending(struct udevice *dev, bool input)
392 {
393 struct ns16550 *const com_port = dev_get_priv(dev);
394
395 if (input)
396 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0;
397 else
398 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
399 }
400
ns16550_serial_getc(struct udevice * dev)401 int ns16550_serial_getc(struct udevice *dev)
402 {
403 struct ns16550 *const com_port = dev_get_priv(dev);
404
405 if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
406 return -EAGAIN;
407
408 return serial_in(&com_port->rbr);
409 }
410
ns16550_serial_setbrg(struct udevice * dev,int baudrate)411 int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
412 {
413 struct ns16550 *const com_port = dev_get_priv(dev);
414 struct ns16550_plat *plat = com_port->plat;
415 int clock_divisor;
416
417 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
418
419 ns16550_setbrg(com_port, clock_divisor);
420
421 return 0;
422 }
423
ns16550_serial_setconfig(struct udevice * dev,uint serial_config)424 int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
425 {
426 struct ns16550 *const com_port = dev_get_priv(dev);
427 int lcr_val = UART_LCR_WLS_8;
428 uint parity = SERIAL_GET_PARITY(serial_config);
429 uint bits = SERIAL_GET_BITS(serial_config);
430 uint stop = SERIAL_GET_STOP(serial_config);
431
432 /*
433 * only parity config is implemented, check if other serial settings
434 * are the default one.
435 */
436 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP)
437 return -ENOTSUPP; /* not supported in driver*/
438
439 switch (parity) {
440 case SERIAL_PAR_NONE:
441 /* no bits to add */
442 break;
443 case SERIAL_PAR_ODD:
444 lcr_val |= UART_LCR_PEN;
445 break;
446 case SERIAL_PAR_EVEN:
447 lcr_val |= UART_LCR_PEN | UART_LCR_EPS;
448 break;
449 default:
450 return -ENOTSUPP; /* not supported in driver*/
451 }
452
453 serial_out(lcr_val, &com_port->lcr);
454 return 0;
455 }
456
ns16550_serial_getinfo(struct udevice * dev,struct serial_device_info * info)457 int ns16550_serial_getinfo(struct udevice *dev, struct serial_device_info *info)
458 {
459 struct ns16550 *const com_port = dev_get_priv(dev);
460 struct ns16550_plat *plat = com_port->plat;
461
462 /* save code size */
463 if (!not_xpl() && !CONFIG_IS_ENABLED(UPL_OUT))
464 return -ENOSYS;
465
466 info->type = SERIAL_CHIP_16550_COMPATIBLE;
467 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
468 info->addr_space = SERIAL_ADDRESS_SPACE_IO;
469 #else
470 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
471 #endif
472 info->addr = plat->base;
473 info->size = plat->size;
474 info->reg_width = plat->reg_width;
475 info->reg_shift = plat->reg_shift;
476 info->reg_offset = plat->reg_offset;
477 info->clock = plat->clock;
478
479 return 0;
480 }
481
ns16550_serial_assign_base(struct ns16550_plat * plat,fdt_addr_t base,fdt_size_t size)482 static int ns16550_serial_assign_base(struct ns16550_plat *plat,
483 fdt_addr_t base, fdt_size_t size)
484 {
485 if (base == FDT_ADDR_T_NONE)
486 return -EINVAL;
487
488 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
489 plat->base = base;
490 #else
491 plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
492 #endif
493 plat->size = size;
494
495 return 0;
496 }
497
ns16550_serial_probe(struct udevice * dev)498 int ns16550_serial_probe(struct udevice *dev)
499 {
500 struct ns16550_plat *plat = dev_get_plat(dev);
501 struct ns16550 *const com_port = dev_get_priv(dev);
502 struct reset_ctl_bulk reset_bulk;
503 fdt_addr_t addr;
504 fdt_addr_t size;
505 int ret;
506
507 /*
508 * If we are on PCI bus, either directly attached to a PCI root port,
509 * or via a PCI bridge, assign plat->base before probing hardware.
510 */
511 if (device_is_on_pci_bus(dev)) {
512 addr = devfdt_get_addr_pci(dev, &size);
513 ret = ns16550_serial_assign_base(plat, addr, size);
514 if (ret)
515 return ret;
516 }
517
518 ret = reset_get_bulk(dev, &reset_bulk);
519 if (!ret)
520 reset_deassert_bulk(&reset_bulk);
521
522 com_port->plat = dev_get_plat(dev);
523 ns16550_init(com_port, -1);
524
525 return 0;
526 }
527
528 #if CONFIG_IS_ENABLED(OF_CONTROL)
529 enum {
530 PORT_NS16550 = 0,
531 PORT_JZ4780,
532 };
533 #endif
534
535 #if CONFIG_IS_ENABLED(OF_REAL)
ns16550_serial_of_to_plat(struct udevice * dev)536 int ns16550_serial_of_to_plat(struct udevice *dev)
537 {
538 struct ns16550_plat *plat = dev_get_plat(dev);
539 const u32 port_type = dev_get_driver_data(dev);
540 fdt_size_t size = 0;
541 fdt_addr_t addr;
542 struct clk clk;
543 int err;
544
545 addr = not_xpl() ? dev_read_addr_size(dev, &size) :
546 dev_read_addr(dev);
547 err = ns16550_serial_assign_base(plat, addr, size);
548 if (err && !device_is_on_pci_bus(dev))
549 return err;
550
551 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
552 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
553 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
554
555 if (!plat->clock)
556 plat->clock = dev_read_u32_default(dev, "clock-frequency", 0);
557 if (!plat->clock) {
558 err = clk_get_by_index(dev, 0, &clk);
559 if (!err) {
560 err = clk_get_rate(&clk);
561 if (!IS_ERR_VALUE(err))
562 plat->clock = err;
563 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
564 debug("ns16550 failed to get clock\n");
565 return err;
566 }
567 }
568 if (!plat->clock)
569 plat->clock = CFG_SYS_NS16550_CLK;
570 if (!plat->clock) {
571 debug("ns16550 clock not defined\n");
572 return -EINVAL;
573 }
574
575 plat->fcr = UART_FCR_DEFVAL;
576 if (port_type == PORT_JZ4780)
577 plat->fcr |= UART_FCR_UME;
578
579 return 0;
580 }
581 #endif
582
583 const struct dm_serial_ops ns16550_serial_ops = {
584 .putc = ns16550_serial_putc,
585 .pending = ns16550_serial_pending,
586 .getc = ns16550_serial_getc,
587 .setbrg = ns16550_serial_setbrg,
588 .setconfig = ns16550_serial_setconfig,
589 .getinfo = ns16550_serial_getinfo,
590 };
591
592 #if CONFIG_IS_ENABLED(OF_REAL)
593 /*
594 * Please consider existing compatible strings before adding a new
595 * one to keep this table compact. Or you may add a generic "ns16550"
596 * compatible string to your dts.
597 */
598 static const struct udevice_id ns16550_serial_ids[] = {
599 { .compatible = "ns16550", .data = PORT_NS16550 },
600 { .compatible = "ns16550a", .data = PORT_NS16550 },
601 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
602 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
603 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
604 { .compatible = "intel,xscale-uart", .data = PORT_NS16550 },
605 {}
606 };
607 #endif /* OF_REAL */
608
609 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
610
611 /* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */
612 #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
613 U_BOOT_DRIVER(ns16550_serial) = {
614 .name = "ns16550_serial",
615 .id = UCLASS_SERIAL,
616 #if CONFIG_IS_ENABLED(OF_REAL)
617 .of_match = ns16550_serial_ids,
618 .of_to_plat = ns16550_serial_of_to_plat,
619 .plat_auto = sizeof(struct ns16550_plat),
620 #endif
621 .priv_auto = sizeof(struct ns16550),
622 .probe = ns16550_serial_probe,
623 .ops = &ns16550_serial_ops,
624 #if !CONFIG_IS_ENABLED(OF_CONTROL)
625 .flags = DM_FLAG_PRE_RELOC,
626 #endif
627 };
628
629 DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart)
630 #endif
631 #endif /* SERIAL_PRESENT */
632
633 #endif /* CONFIG_DM_SERIAL */
634