1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * ColdFire Internal Memory Map and Defines 4 * 5 * Copyright 2004-2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 #ifndef __IMMAP_H 10 #define __IMMAP_H 11 12 #include <config.h> 13 #if defined(CONFIG_MCF520x) 14 #include <asm/immap_520x.h> 15 #include <asm/m520x.h> 16 17 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) 18 19 /* Timer */ 20 #if CONFIG_IS_ENABLED(MCFTMR) 21 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 22 #define CFG_SYS_TMR_BASE (MMAP_DTMR1) 23 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) 24 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 25 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 26 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 27 #define CFG_SYS_TMRINTR_PRI (6) 28 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 29 #else 30 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 31 #endif 32 33 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 34 #define CFG_SYS_NUM_IRQS (128) 35 #endif /* CONFIG_M520x */ 36 37 #ifdef CONFIG_M5235 38 #include <asm/immap_5235.h> 39 #include <asm/m5235.h> 40 41 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) 42 43 /* Timer */ 44 #if CONFIG_IS_ENABLED(MCFTMR) 45 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 46 #define CFG_SYS_TMR_BASE (MMAP_DTMR3) 47 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) 48 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 49 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 50 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 51 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 52 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 53 #else 54 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 55 #endif 56 57 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 58 #define CFG_SYS_NUM_IRQS (128) 59 #endif /* CONFIG_M5235 */ 60 61 #ifdef CONFIG_M5249 62 #include <asm/immap_5249.h> 63 #include <asm/m5249.h> 64 65 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) 66 67 #define CFG_SYS_INTR_BASE (MMAP_INTC) 68 #define CFG_SYS_NUM_IRQS (64) 69 70 /* Timer */ 71 #if CONFIG_IS_ENABLED(MCFTMR) 72 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 73 #define CFG_SYS_TMR_BASE (MMAP_DTMR1) 74 #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 75 #define CFG_SYS_TMRINTR_NO (31) 76 #define CFG_SYS_TMRINTR_MASK (0x00000400) 77 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 78 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 79 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 80 #else 81 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 82 #endif 83 #endif /* CONFIG_M5249 */ 84 85 #ifdef CONFIG_M5253 86 #include <asm/immap_5253.h> 87 #include <asm/m5249.h> 88 #include <asm/m5253.h> 89 90 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) 91 92 #define CFG_SYS_INTR_BASE (MMAP_INTC) 93 #define CFG_SYS_NUM_IRQS (64) 94 95 /* Timer */ 96 #if CONFIG_IS_ENABLED(MCFTMR) 97 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 98 #define CFG_SYS_TMR_BASE (MMAP_DTMR1) 99 #define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 100 #define CFG_SYS_TMRINTR_NO (27) 101 #define CFG_SYS_TMRINTR_MASK (0x00000400) 102 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 103 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) 104 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 105 #else 106 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 107 #endif 108 #endif /* CONFIG_M5253 */ 109 110 #ifdef CONFIG_M5271 111 #include <asm/immap_5271.h> 112 #include <asm/m5271.h> 113 114 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) 115 116 /* Timer */ 117 #if CONFIG_IS_ENABLED(MCFTMR) 118 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 119 #define CFG_SYS_TMR_BASE (MMAP_DTMR3) 120 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) 121 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 122 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 123 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 124 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ 125 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 126 #else 127 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 128 #endif 129 130 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 131 #define CFG_SYS_NUM_IRQS (128) 132 #endif /* CONFIG_M5271 */ 133 134 #ifdef CONFIG_M5272 135 #include <asm/immap_5272.h> 136 #include <asm/m5272.h> 137 138 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) 139 140 #define CFG_SYS_INTR_BASE (MMAP_INTC) 141 #define CFG_SYS_NUM_IRQS (64) 142 143 /* Timer */ 144 #if CONFIG_IS_ENABLED(MCFTMR) 145 #define CFG_SYS_UDELAY_BASE (MMAP_TMR0) 146 #define CFG_SYS_TMR_BASE (MMAP_TMR3) 147 #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr) 148 #define CFG_SYS_TMRINTR_NO (INT_TMR3) 149 #define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24) 150 #define CFG_SYS_TMRINTR_PEND (0) 151 #define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) 152 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 153 #else 154 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 155 #endif 156 #endif /* CONFIG_M5272 */ 157 158 #ifdef CONFIG_M5275 159 #include <asm/immap_5275.h> 160 #include <asm/m5275.h> 161 162 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) 163 164 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 165 #define CFG_SYS_NUM_IRQS (192) 166 167 /* Timer */ 168 #if CONFIG_IS_ENABLED(MCFTMR) 169 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 170 #define CFG_SYS_TMR_BASE (MMAP_DTMR3) 171 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) 172 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 173 #define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 174 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 175 #define CFG_SYS_TMRINTR_PRI (0x1E) 176 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 177 #else 178 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 179 #endif 180 #endif /* CONFIG_M5275 */ 181 182 #ifdef CONFIG_M5282 183 #include <asm/immap_5282.h> 184 #include <asm/m5282.h> 185 186 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) 187 188 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 189 #define CFG_SYS_NUM_IRQS (128) 190 191 /* Timer */ 192 #if CONFIG_IS_ENABLED(MCFTMR) 193 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 194 #define CFG_SYS_TMR_BASE (MMAP_DTMR3) 195 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) 196 #define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 197 #define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) 198 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 199 #define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 200 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 201 #else 202 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 203 #endif 204 #endif /* CONFIG_M5282 */ 205 206 #ifdef CONFIG_M5307 207 #include <asm/immap_5307.h> 208 #include <asm/m5307.h> 209 210 #define CFG_SYS_UART_BASE (MMAP_UART0 + \ 211 (CFG_SYS_UART_PORT * 0x40)) 212 #define CFG_SYS_INTR_BASE (MMAP_INTC) 213 #define CFG_SYS_NUM_IRQS (64) 214 215 /* Timer */ 216 #if CONFIG_IS_ENABLED(MCFTMR) 217 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 218 #define CFG_SYS_TMR_BASE (MMAP_DTMR1) 219 #define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \ 220 (CFG_SYS_INTR_BASE))->ipr) 221 #define CFG_SYS_TMRINTR_NO (31) 222 #define CFG_SYS_TMRINTR_MASK (0x00000400) 223 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 224 #define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ 225 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 226 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 227 #else 228 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 229 #endif 230 #endif /* CONFIG_M5307 */ 231 232 #if defined(CONFIG_MCF5301x) 233 #include <asm/immap_5301x.h> 234 #include <asm/m5301x.h> 235 236 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) 237 238 /* Timer */ 239 #if CONFIG_IS_ENABLED(MCFTMR) 240 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 241 #define CFG_SYS_TMR_BASE (MMAP_DTMR1) 242 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) 243 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 244 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 245 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 246 #define CFG_SYS_TMRINTR_PRI (6) 247 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 248 #else 249 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 250 #endif 251 252 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 253 #define CFG_SYS_NUM_IRQS (128) 254 #endif /* CONFIG_M5301x */ 255 256 #if defined(CONFIG_M5329) || defined(CONFIG_M5373) 257 #include <asm/immap_5329.h> 258 #include <asm/m5329.h> 259 260 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) 261 262 /* Timer */ 263 #if CONFIG_IS_ENABLED(MCFTMR) 264 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 265 #define CFG_SYS_TMR_BASE (MMAP_DTMR1) 266 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) 267 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 268 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 269 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 270 #define CFG_SYS_TMRINTR_PRI (6) 271 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 272 #else 273 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 274 #endif 275 276 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 277 #define CFG_SYS_NUM_IRQS (128) 278 #endif /* CONFIG_M5329 && CONFIG_M5373 */ 279 280 #if defined(CONFIG_M54418) 281 #include <asm/immap_5441x.h> 282 #include <asm/m5441x.h> 283 284 #if (CFG_SYS_UART_PORT < 4) 285 #define CFG_SYS_UART_BASE (MMAP_UART0 + \ 286 (CFG_SYS_UART_PORT * 0x4000)) 287 #else 288 #define CFG_SYS_UART_BASE (MMAP_UART4 + \ 289 ((CFG_SYS_UART_PORT - 4) * 0x4000)) 290 #endif 291 292 #define MMAP_DSPI MMAP_DSPI0 293 294 /* Timer */ 295 #if CONFIG_IS_ENABLED(MCFTMR) 296 #define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) 297 #define CFG_SYS_TMR_BASE (MMAP_DTMR1) 298 #define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0) 299 #define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 300 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 301 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 302 #define CFG_SYS_TMRINTR_PRI (6) 303 #define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 304 #else 305 #define CFG_SYS_UDELAY_BASE (MMAP_PIT0) 306 #endif 307 308 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 309 #define CFG_SYS_NUM_IRQS (192) 310 311 #endif /* CONFIG_M54418 */ 312 313 #ifdef CONFIG_M547x 314 #include <asm/immap_547x_8x.h> 315 #include <asm/m547x_8x.h> 316 317 #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) 318 319 #ifdef CONFIG_SLTTMR 320 #define CFG_SYS_UDELAY_BASE (MMAP_SLT1) 321 #define CFG_SYS_TMR_BASE (MMAP_SLT0) 322 #define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) 323 #define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0) 324 #define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 325 #define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) 326 #define CFG_SYS_TMRINTR_PRI (0x1E) 327 #define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 328 #endif 329 330 #define CFG_SYS_INTR_BASE (MMAP_INTC0) 331 #define CFG_SYS_NUM_IRQS (128) 332 333 #ifdef CONFIG_PCI 334 #define CFG_SYS_PCI_BAR0 (0x40000000) 335 #define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) 336 #define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR) 337 #define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) 338 #endif 339 #endif /* CONFIG_M547x */ 340 341 #endif /* __IMMAP_H */ 342