1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K3: J721E SoC definitions, structures etc. 4 * 5 * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 #ifndef __ASM_ARCH_J721E_HARDWARE_H 8 #define __ASM_ARCH_J721E_HARDWARE_H 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 #define WKUP_CTRL_MMR0_BASE 0x43000000 15 #define MCU_CTRL_MMR0_BASE 0x40f00000 16 #define CTRL_MMR0_BASE 0x00100000 17 18 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) 19 #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) 20 #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 21 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) 22 #define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1 23 #define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6) 24 #define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6 25 #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) 26 #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 27 28 #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) 29 #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) 30 #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 31 #define WKUP_DEVSTAT_MCU_ONLY_MASK BIT(6) 32 #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 33 34 /* ROM HANDOFF Structure location */ 35 #define ROM_EXTENDED_BOOT_DATA_INFO 0x41cffb00 36 37 /* MCU SCRATCHPAD usage */ 38 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE 39 40 #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) 41 42 #define J721E_DEV_MCU_RTI0 262 43 #define J721E_DEV_MCU_RTI1 263 44 45 static const u32 put_device_ids[] = { 46 J721E_DEV_MCU_RTI0, 47 J721E_DEV_MCU_RTI1, 48 }; 49 50 #endif 51 52 #define J721E_DEV_MCU_ARMSS0_CPU0 250 53 #define J721E_DEV_MCU_ARMSS0_CPU1 251 54 55 static const u32 put_core_ids[] = { 56 J721E_DEV_MCU_ARMSS0_CPU1, 57 J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ 58 }; 59 60 #endif /* __ASM_ARCH_J721E_HARDWARE_H */ 61