1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 *
6 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
8 */
9 #ifndef __LINUX_CLK_PROVIDER_H
10 #define __LINUX_CLK_PROVIDER_H
11
12 #include <linux/bitops.h>
13 #include <linux/err.h>
14 #include <clk-uclass.h>
15
16 struct udevice;
17
18 /* update clock ID for the dev = clock provider, compatible with CLK_AUTO_ID */
dev_clk_dm(const struct udevice * dev,ulong id,struct clk * clk)19 static inline void dev_clk_dm(const struct udevice *dev, ulong id, struct clk *clk)
20 {
21 if (!IS_ERR(clk))
22 clk->id = CLK_ID(dev, id);
23 }
24
clk_dm(ulong id,struct clk * clk)25 static inline void clk_dm(ulong id, struct clk *clk)
26 {
27 if (!IS_ERR(clk))
28 clk->id = CLK_ID(clk->dev, id);
29 }
30
31 /*
32 * flags used across common struct clk. these flags should only affect the
33 * top-level framework. custom flags for dealing with hardware specifics
34 * belong in struct clk_foo
35 *
36 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
37 */
38 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
39 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
40 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
41 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
42 /* unused */
43 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
44 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
45 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
46 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
47 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
48 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
49 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
50 /* parents need enable during gate/ungate, set rate and re-parent */
51 #define CLK_OPS_PARENT_ENABLE BIT(12)
52 /* duty cycle call may be forwarded to the parent clock */
53 #define CLK_DUTY_CYCLE_PARENT BIT(13)
54
55 #define CLK_MUX_INDEX_ONE BIT(0)
56 #define CLK_MUX_INDEX_BIT BIT(1)
57 #define CLK_MUX_HIWORD_MASK BIT(2)
58 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
59 #define CLK_MUX_ROUND_CLOSEST BIT(4)
60
61 struct clk_mux {
62 struct clk clk;
63 void __iomem *reg;
64 u32 *table;
65 u32 mask;
66 u8 shift;
67 u8 flags;
68
69 /*
70 * Fields from struct clk_init_data - this struct has been
71 * omitted to avoid too deep level of CCF for bootloader
72 */
73 const char * const *parent_names;
74 u8 num_parents;
75 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
76 u32 io_mux_val;
77 #endif
78
79 };
80
81 #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
82 extern const struct clk_ops clk_mux_ops;
83 u8 clk_mux_get_parent(struct clk *clk);
84 int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent);
85
86 /**
87 * clk_mux_index_to_val() - Convert the parent index to the register value
88 *
89 * It returns the value to write in the hardware register to output the selected
90 * input clock parent.
91 *
92 * @table: array of register values corresponding to the parent index (optional)
93 * @flags: hardware-specific flags
94 * @index: parent clock index
95 * Return: the register value
96 */
97 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
98
99 struct clk_gate {
100 struct clk clk;
101 void __iomem *reg;
102 u8 bit_idx;
103 u8 flags;
104 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
105 u32 io_gate_val;
106 #endif
107 };
108
109 #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
110
111 #define CLK_GATE_SET_TO_DISABLE BIT(0)
112 #define CLK_GATE_HIWORD_MASK BIT(1)
113
114 extern const struct clk_ops clk_gate_ops;
115 struct clk *clk_register_gate(struct udevice *dev, const char *name,
116 const char *parent_name, unsigned long flags,
117 void __iomem *reg, u8 bit_idx,
118 u8 clk_gate_flags, spinlock_t *lock);
119
120 struct clk_div_table {
121 unsigned int val;
122 unsigned int div;
123 };
124
125 struct clk_divider {
126 struct clk clk;
127 void __iomem *reg;
128 u8 shift;
129 u8 width;
130 u8 flags;
131 const struct clk_div_table *table;
132 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
133 u32 io_divider_val;
134 #endif
135 };
136
137 #define clk_div_mask(width) ((1 << (width)) - 1)
138 #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
139
140 #define CLK_DIVIDER_ONE_BASED BIT(0)
141 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
142 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
143 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
144 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
145 #define CLK_DIVIDER_READ_ONLY BIT(5)
146 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
147 extern const struct clk_ops clk_divider_ops;
148
149 /**
150 * clk_divider_get_table_div() - convert the register value to the divider
151 *
152 * @table: array of register values corresponding to valid dividers
153 * @val: value to convert
154 * Return: the divider
155 */
156 unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
157 unsigned int val);
158
159 /**
160 * clk_divider_get_table_val() - convert the divider to the register value
161 *
162 * It returns the value to write in the hardware register to divide the input
163 * clock rate by @div.
164 *
165 * @table: array of register values corresponding to valid dividers
166 * @div: requested divider
167 * Return: the register value
168 */
169 unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
170 unsigned int div);
171
172 /**
173 * clk_divider_is_valid_div() - check if the divider is valid
174 *
175 * @table: array of valid dividers (optional)
176 * @div: divider to check
177 * @flags: hardware-specific flags
178 * Return: true if the divider is valid, false otherwise
179 */
180 bool clk_divider_is_valid_div(const struct clk_div_table *table,
181 unsigned int div, unsigned long flags);
182
183 /**
184 * clk_divider_is_valid_table_div - check if the divider is in the @table array
185 *
186 * @table: array of valid dividers
187 * @div: divider to check
188 * Return: true if the divider is found in the @table array, false otherwise
189 */
190 bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
191 unsigned int div);
192 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
193 unsigned int val,
194 const struct clk_div_table *table,
195 unsigned long flags, unsigned long width);
196
197 struct clk_fixed_factor {
198 struct clk clk;
199 unsigned int mult;
200 unsigned int div;
201 };
202
203 extern const struct clk_ops clk_fixed_rate_ops;
204
205 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
206 clk)
207
208 struct clk_fixed_rate {
209 struct clk clk;
210 unsigned long fixed_rate;
211 };
212
213 #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_plat(dev))
214
215 void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
216 struct clk_fixed_rate *plat);
217
218 struct clk_composite {
219 struct clk clk;
220 struct clk_ops ops;
221
222 struct clk *mux;
223 struct clk *rate;
224 struct clk *gate;
225
226 const struct clk_ops *mux_ops;
227 const struct clk_ops *rate_ops;
228 const struct clk_ops *gate_ops;
229
230 struct udevice *dev;
231 };
232
233 #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
234
235 struct clk *clk_register_composite(struct udevice *dev, const char *name,
236 const char * const *parent_names, int num_parents,
237 struct clk *mux_clk, const struct clk_ops *mux_ops,
238 struct clk *rate_clk, const struct clk_ops *rate_ops,
239 struct clk *gate_clk, const struct clk_ops *gate_ops,
240 unsigned long flags);
241
242 int clk_register(struct clk *clk, const char *drv_name, const char *name,
243 const char *parent_name);
244
245 struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name,
246 const char *parent_name, unsigned long flags,
247 unsigned int mult, unsigned int div);
248
249 struct clk *clk_register_divider(struct udevice *dev, const char *name,
250 const char *parent_name, unsigned long flags,
251 void __iomem *reg, u8 shift, u8 width,
252 u8 clk_divider_flags);
253
254 struct clk *clk_register_mux(struct udevice *dev, const char *name,
255 const char * const *parent_names, u8 num_parents,
256 unsigned long flags,
257 void __iomem *reg, u8 shift, u8 width,
258 u8 clk_mux_flags);
259
260 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
261 ulong rate);
262
263 const char *clk_hw_get_name(const struct clk *hw);
264 ulong clk_generic_get_rate(struct clk *clk);
265
266 struct clk *dev_get_clk_ptr(struct udevice *dev);
267
268 ulong ccf_clk_get_rate(struct clk *clk);
269 ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate);
270 int ccf_clk_set_parent(struct clk *clk, struct clk *parent);
271 int ccf_clk_enable(struct clk *clk);
272 int ccf_clk_disable(struct clk *clk);
273 extern const struct clk_ops ccf_clk_ops;
274
275 #endif /* __LINUX_CLK_PROVIDER_H */
276