1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
9
10 #include <mtd.h>
11 #include <linux/bitops.h>
12 #include <linux/mtd/cfi.h>
13 #include <linux/mtd/mtd.h>
14 #include <spi-mem.h>
15
16 /* In parallel configuration enable multiple CS */
17 #define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1))
18
19 /*
20 * Manufacturer IDs
21 *
22 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
23 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
24 */
25 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
26 #define SNOR_MFR_GIGADEVICE 0xc8
27 #define SNOR_MFR_INTEL CFI_MFR_INTEL
28 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
29 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
30 #define SNOR_MFR_ISSI CFI_MFR_PMC
31 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
32 #define SNOR_MFR_SPANSION CFI_MFR_AMD
33 #define SNOR_MFR_SST CFI_MFR_SST
34 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
35 #define SNOR_MFR_CYPRESS 0x34
36
37 /*
38 * Note on opcode nomenclature: some opcodes have a format like
39 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
40 * of I/O lines used for the opcode, address, and data (respectively). The
41 * FUNCTION has an optional suffix of '4', to represent an opcode which
42 * requires a 4-byte (32-bit) address.
43 */
44
45 /* Flash opcodes. */
46 #define SPINOR_OP_WREN 0x06 /* Write enable */
47 #define SPINOR_OP_RDSR 0x05 /* Read status register */
48 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
49 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
50 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
51 #define SPINOR_OP_RDSR3 0x15 /* Read status register 3 */
52 #define SPINOR_OP_WRSR3 0x11 /* Write status register 3 */
53 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
54 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
55 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
56 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
57 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
58 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
59 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
60 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
61 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
62 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
63 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
64 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
65 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
66 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
67 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
68 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
69 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
70 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
71 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
72 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
73 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
74 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
75 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
76 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
77 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
78 #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
79 #define SPINOR_OP_SRST 0x99 /* Software Reset */
80
81 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
82 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
83 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
84 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
85 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
86 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
87 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
88 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
89 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
90 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
91 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
92 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
93 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
94 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
95 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
96 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
97 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
98
99 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
100 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
101 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
102 #define SPINOR_OP_READ_1_4_4_DTR 0xed
103
104 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
105 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
106 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
107
108 /* Used for SST flashes only. */
109 #define SPINOR_OP_BP 0x02 /* Byte program */
110 #define SPINOR_OP_WRDI 0x04 /* Write disable */
111 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
112
113 /* Used for SST26* flashes only. */
114 #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
115 #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
116
117 /* Used for S3AN flashes only */
118 #define SPINOR_OP_XSE 0x50 /* Sector erase */
119 #define SPINOR_OP_XPP 0x82 /* Page program */
120 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
121
122 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
123 #define XSR_RDY BIT(7) /* Ready */
124
125 /* Used for Macronix and Winbond flashes. */
126 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
127 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
128 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
129 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
130 #define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */
131 #define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */
132 #define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */
133 #define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */
134 #define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
135 #define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */
136 #define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */
137 #define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */
138
139 /* Used for Spansion flashes only. */
140 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
141 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
142 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
143 #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */
144
145 /* Used for Micron flashes only. */
146 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
147 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
148 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
149 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
150 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
151 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
152 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
153 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */
154
155 /* Status Register bits. */
156 #define SR_WIP BIT(0) /* Write in progress */
157 #define SR_WEL BIT(1) /* Write enable latch */
158 /* meaning of other SR_* bits may differ between vendors */
159 #define SR_BP0 BIT(2) /* Block protect 0 */
160 #define SR_BP1 BIT(3) /* Block protect 1 */
161 #define SR_BP2 BIT(4) /* Block protect 2 */
162 #define SR_TB BIT(5) /* Top/Bottom protect */
163 #define SR_SRWD BIT(7) /* SR write protect */
164 /* Spansion/Cypress specific status bits */
165 #define SR_E_ERR BIT(5)
166 #define SR_P_ERR BIT(6)
167
168 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
169
170 /* Enhanced Volatile Configuration Register bits */
171 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
172
173 /* Flag Status Register bits */
174 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
175 #define FSR_E_ERR BIT(5) /* Erase operation status */
176 #define FSR_P_ERR BIT(4) /* Program operation status */
177 #define FSR_PT_ERR BIT(1) /* Protection error bit */
178
179 /* Configuration Register bits. */
180 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
181
182 /* Status Register 2 bits. */
183 #define SR2_QUAD_EN_BIT7 BIT(7)
184
185 /* Status Register 3 bits. */
186 #define SR3_WPS BIT(2)
187
188 /*
189 * Maximum number of flashes that can be connected
190 * in stacked/parallel configuration
191 */
192 #define SNOR_FLASH_CNT_MAX 2
193
194 /* For Cypress flash. */
195 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
196 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
197 #define SPINOR_OP_CYPRESS_CLPEF 0x82 /* Clear P/E err flag */
198 #define SPINOR_REG_CYPRESS_ARCFN 0x00000006
199 #define SPINOR_REG_CYPRESS_STR1V 0x00800000
200 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002
201 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
202 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0)
203 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb
204 #define SPINOR_REG_CYPRESS_CFR3V 0x00800004
205 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */
206 #define SPINOR_REG_CYPRESS_CFR3_UNISECT BIT(3) /* Uniform sector mode */
207 #define SPINOR_REG_CYPRESS_CFR5V 0x00800006
208 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
209 #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
210 #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
211 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \
212 (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
213 SPINOR_REG_CYPRESS_CFR5_OPI)
214 #define SPINOR_OP_CYPRESS_RD_FAST 0xee
215
216 /* Supported SPI protocols */
217 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
218 #define SNOR_PROTO_INST_SHIFT 16
219 #define SNOR_PROTO_INST(_nbits) \
220 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
221 SNOR_PROTO_INST_MASK)
222
223 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
224 #define SNOR_PROTO_ADDR_SHIFT 8
225 #define SNOR_PROTO_ADDR(_nbits) \
226 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
227 SNOR_PROTO_ADDR_MASK)
228
229 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
230 #define SNOR_PROTO_DATA_SHIFT 0
231 #define SNOR_PROTO_DATA(_nbits) \
232 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
233 SNOR_PROTO_DATA_MASK)
234
235 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
236
237 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
238 (SNOR_PROTO_INST(_inst_nbits) | \
239 SNOR_PROTO_ADDR(_addr_nbits) | \
240 SNOR_PROTO_DATA(_data_nbits))
241 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
242 (SNOR_PROTO_IS_DTR | \
243 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
244
245 enum spi_nor_protocol {
246 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
247 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
248 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
249 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
250 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
251 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
252 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
253 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
254 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
255 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
256
257 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
258 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
259 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
260 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
261 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
262 };
263
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)264 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
265 {
266 return !!(proto & SNOR_PROTO_IS_DTR);
267 }
268
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)269 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
270 {
271 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
272 SNOR_PROTO_INST_SHIFT;
273 }
274
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)275 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
276 {
277 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
278 SNOR_PROTO_ADDR_SHIFT;
279 }
280
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)281 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
282 {
283 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
284 SNOR_PROTO_DATA_SHIFT;
285 }
286
spi_nor_get_protocol_width(enum spi_nor_protocol proto)287 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
288 {
289 return spi_nor_get_protocol_data_nbits(proto);
290 }
291
292 #define SPI_NOR_MAX_CMD_SIZE 8
293 enum spi_nor_ops {
294 SPI_NOR_OPS_READ = 0,
295 SPI_NOR_OPS_WRITE,
296 SPI_NOR_OPS_ERASE,
297 SPI_NOR_OPS_LOCK,
298 SPI_NOR_OPS_UNLOCK,
299 };
300
301 enum spi_nor_option_flags {
302 SNOR_F_USE_FSR = BIT(0),
303 SNOR_F_HAS_SR_TB = BIT(1),
304 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
305 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
306 SNOR_F_READY_XSR_RDY = BIT(4),
307 SNOR_F_USE_CLSR = BIT(5),
308 SNOR_F_BROKEN_RESET = BIT(6),
309 SNOR_F_SOFT_RESET = BIT(7),
310 SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
311 #if defined(CONFIG_SPI_STACKED_PARALLEL)
312 SNOR_F_HAS_STACKED = BIT(9),
313 SNOR_F_HAS_PARALLEL = BIT(10),
314 #else
315 SNOR_F_HAS_STACKED = 0,
316 SNOR_F_HAS_PARALLEL = 0,
317 #endif
318 };
319
320 struct spi_nor;
321
322 /**
323 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
324 * supported by the SPI controller (bus master).
325 * @mask: the bitmask listing all the supported hw capabilies
326 */
327 struct spi_nor_hwcaps {
328 u32 mask;
329 };
330
331 /*
332 *(Fast) Read capabilities.
333 * MUST be ordered by priority: the higher bit position, the higher priority.
334 * As a matter of performances, it is relevant to use Octo SPI protocols first,
335 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
336 * (Slow) Read.
337 */
338 #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
339 #define SNOR_HWCAPS_READ BIT(0)
340 #define SNOR_HWCAPS_READ_FAST BIT(1)
341 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
342
343 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
344 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
345 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
346 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
347 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
348
349 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
350 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
351 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
352 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
353 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
354
355 #define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11)
356 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
357 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
358 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
359 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
360 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
361
362 /*
363 * Page Program capabilities.
364 * MUST be ordered by priority: the higher bit position, the higher priority.
365 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
366 * legacy SPI 1-1-1 protocol.
367 * Note that Dual Page Programs are not supported because there is no existing
368 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
369 * implements such commands.
370 */
371 #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
372 #define SNOR_HWCAPS_PP BIT(16)
373
374 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
375 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
376 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
377 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
378
379 #define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20)
380 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
381 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
382 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
383 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
384
385 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
386 SNOR_HWCAPS_READ_4_4_4 | \
387 SNOR_HWCAPS_READ_8_8_8 | \
388 SNOR_HWCAPS_PP_4_4_4 | \
389 SNOR_HWCAPS_PP_8_8_8)
390
391 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
392 SNOR_HWCAPS_PP_8_8_8_DTR)
393
394 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
395 SNOR_HWCAPS_READ_1_2_2_DTR | \
396 SNOR_HWCAPS_READ_1_4_4_DTR | \
397 SNOR_HWCAPS_READ_1_8_8_DTR)
398
399 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
400 SNOR_HWCAPS_PP_MASK)
401
402 struct spi_nor_read_command {
403 u8 num_mode_clocks;
404 u8 num_wait_states;
405 u8 opcode;
406 enum spi_nor_protocol proto;
407 };
408
409 struct spi_nor_pp_command {
410 u8 opcode;
411 enum spi_nor_protocol proto;
412 };
413
414 enum spi_nor_read_command_index {
415 SNOR_CMD_READ,
416 SNOR_CMD_READ_FAST,
417 SNOR_CMD_READ_1_1_1_DTR,
418
419 /* Dual SPI */
420 SNOR_CMD_READ_1_1_2,
421 SNOR_CMD_READ_1_2_2,
422 SNOR_CMD_READ_2_2_2,
423 SNOR_CMD_READ_1_2_2_DTR,
424
425 /* Quad SPI */
426 SNOR_CMD_READ_1_1_4,
427 SNOR_CMD_READ_1_4_4,
428 SNOR_CMD_READ_4_4_4,
429 SNOR_CMD_READ_1_4_4_DTR,
430
431 /* Octo SPI */
432 SNOR_CMD_READ_1_1_8,
433 SNOR_CMD_READ_1_8_8,
434 SNOR_CMD_READ_8_8_8,
435 SNOR_CMD_READ_1_8_8_DTR,
436 SNOR_CMD_READ_8_8_8_DTR,
437
438 SNOR_CMD_READ_MAX
439 };
440
441 enum spi_nor_pp_command_index {
442 SNOR_CMD_PP,
443
444 /* Quad SPI */
445 SNOR_CMD_PP_1_1_4,
446 SNOR_CMD_PP_1_4_4,
447 SNOR_CMD_PP_4_4_4,
448
449 /* Octo SPI */
450 SNOR_CMD_PP_1_1_8,
451 SNOR_CMD_PP_1_8_8,
452 SNOR_CMD_PP_8_8_8,
453 SNOR_CMD_PP_8_8_8_DTR,
454
455 SNOR_CMD_PP_MAX
456 };
457
458 struct spi_nor_flash_parameter {
459 u64 size;
460 u32 writesize;
461 u32 page_size;
462 u8 rdsr_dummy;
463 u8 rdsr_addr_nbytes;
464
465 struct spi_nor_hwcaps hwcaps;
466 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
467 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
468
469 int (*quad_enable)(struct spi_nor *nor);
470 };
471
472 /**
473 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
474 * @SPI_MEM_NOR_NONE: no extension. This is the default, and is used in Legacy
475 * SPI mode
476 * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode
477 * @SPI_MEM_NOR_INVERT: the extension is the bitwise inverse of the opcode
478 * @SPI_MEM_NOR_HEX: the extension is any hex value. The command and opcode
479 * combine to form a 16-bit opcode.
480 */
481 enum spi_nor_cmd_ext {
482 SPI_NOR_EXT_NONE = 0,
483 SPI_NOR_EXT_REPEAT,
484 SPI_NOR_EXT_INVERT,
485 SPI_NOR_EXT_HEX,
486 };
487
488 /**
489 * struct flash_info - Forward declaration of a structure used internally by
490 * spi_nor_scan()
491 */
492 struct flash_info;
493
494 /*
495 * TODO: Remove, once all users of spi_flash interface are moved to MTD
496 *
497 struct spi_flash {
498 * Defined below (keep this text to enable searching for spi_flash decl)
499 * }
500 */
501 #ifndef DT_PLAT_C
502 #define spi_flash spi_nor
503 #endif
504
505 /**
506 * struct spi_nor - Structure for defining a the SPI NOR layer
507 * @mtd: point to a mtd_info structure
508 * @lock: the lock for the read/write/erase/lock/unlock operations
509 * @dev: point to a spi device, or a spi nor controller device.
510 * @info: spi-nor part JDEC MFR id and other info
511 * @manufacturer_sfdp: manufacturer specific SFDP table
512 * @page_size: the page size of the SPI NOR
513 * @addr_width: number of address bytes
514 * @erase_opcode: the opcode for erasing a sector
515 * @read_opcode: the read opcode
516 * @read_dummy: the dummy needed by the read operation
517 * @program_opcode: the program opcode
518 * @rdsr_dummy dummy cycles needed for Read Status Register command.
519 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
520 * command.
521 * @addr_mode_nbytes: number of address bytes of current address mode. Useful
522 * when the flash operates with 4B opcodes but needs the
523 * internal address mode for opcodes that don't have a 4B
524 * opcode correspondent.
525 * @bank_read_cmd: Bank read cmd
526 * @bank_write_cmd: Bank write cmd
527 * @bank_curr: Current flash bank
528 * @sst_write_second: used by the SST write operation
529 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
530 * @read_proto: the SPI protocol for read operations
531 * @write_proto: the SPI protocol for write operations
532 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
533 * @cmd_buf: used by the write_reg
534 * @cmd_ext_type: the command opcode extension for DTR mode.
535 * @fixups: flash-specific fixup hooks.
536 * @prepare: [OPTIONAL] do some preparations for the
537 * read/write/erase/lock/unlock operations
538 * @unprepare: [OPTIONAL] do some post work after the
539 * read/write/erase/lock/unlock operations
540 * @read_reg: [DRIVER-SPECIFIC] read out the register
541 * @write_reg: [DRIVER-SPECIFIC] write data to the register
542 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
543 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
544 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
545 * at the offset @offs; if not provided by the driver,
546 * spi-nor will send the erase opcode via write_reg()
547 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
548 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
549 * @flash_is_unlocked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
550 * completely unlocked
551 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
552 * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode.
553 * @ready: [FLASH-SPECIFIC] check if the flash is ready
554 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
555 * @priv: the private data
556 */
557 struct spi_nor {
558 struct mtd_info mtd;
559 struct udevice *dev;
560 struct spi_slave *spi;
561 const struct flash_info *info;
562 u8 *manufacturer_sfdp;
563 u32 page_size;
564 u8 addr_width;
565 u8 erase_opcode;
566 u8 read_opcode;
567 u8 read_dummy;
568 u8 program_opcode;
569 u8 rdsr_dummy;
570 u8 rdsr_addr_nbytes;
571 u8 addr_mode_nbytes;
572 #if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
573 u8 bank_read_cmd;
574 u8 bank_write_cmd;
575 u8 bank_curr;
576 u8 upage_prev;
577 #endif
578 enum spi_nor_protocol read_proto;
579 enum spi_nor_protocol write_proto;
580 enum spi_nor_protocol reg_proto;
581 bool sst_write_second;
582 u32 flags;
583 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
584 enum spi_nor_cmd_ext cmd_ext_type;
585 struct spi_nor_fixups *fixups;
586
587 int (*setup)(struct spi_nor *nor, const struct flash_info *info,
588 const struct spi_nor_flash_parameter *params);
589 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
590 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
591 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
592 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
593
594 ssize_t (*read)(struct spi_nor *nor, loff_t from,
595 size_t len, u_char *read_buf);
596 ssize_t (*write)(struct spi_nor *nor, loff_t to,
597 size_t len, const u_char *write_buf);
598 int (*erase)(struct spi_nor *nor, loff_t offs);
599
600 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
601 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
602 int (*flash_is_unlocked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
603 int (*quad_enable)(struct spi_nor *nor);
604 int (*octal_dtr_enable)(struct spi_nor *nor);
605 int (*ready)(struct spi_nor *nor);
606
607 struct {
608 struct spi_mem_dirmap_desc *rdesc;
609 struct spi_mem_dirmap_desc *wdesc;
610 } dirmap;
611
612 void *priv;
613 char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
614 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
615 const char *name;
616 u32 size;
617 u32 sector_size;
618 u32 erase_size;
619 };
620
621 #ifndef __UBOOT__
spi_nor_set_flash_node(struct spi_nor * nor,const struct device_node * np)622 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
623 const struct device_node *np)
624 {
625 mtd_set_of_node(&nor->mtd, np);
626 }
627
628 static inline const struct
spi_nor_get_flash_node(struct spi_nor * nor)629 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
630 {
631 return mtd_get_of_node(&nor->mtd);
632 }
633 #endif /* __UBOOT__ */
634
635 /**
636 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
637 * @nor: pointer to a 'struct spi_nor'
638 * @op: pointer to the 'struct spi_mem_op' whose properties
639 * need to be initialized.
640 * @proto: the protocol from which the properties need to be set.
641 */
642 void spi_nor_setup_op(const struct spi_nor *nor,
643 struct spi_mem_op *op,
644 const enum spi_nor_protocol proto);
645
646 /**
647 * spi_nor_scan() - scan the SPI NOR
648 * @nor: the spi_nor structure
649 *
650 * The drivers can use this function to scan the SPI NOR.
651 * In the scanning, it will try to get all the necessary information to
652 * fill the mtd_info{} and the spi_nor{}.
653 *
654 * Return: 0 for success, others for failure.
655 */
656 int spi_nor_scan(struct spi_nor *nor);
657
658 #if CONFIG_IS_ENABLED(SPI_FLASH_TINY)
spi_nor_remove(struct spi_nor * nor)659 static inline int spi_nor_remove(struct spi_nor *nor)
660 {
661 return 0;
662 }
663 #else
664 /**
665 * spi_nor_remove() - perform cleanup before booting to the next stage
666 * @nor: the spi_nor structure
667 *
668 * Return: 0 for success, -errno for failure.
669 */
670 int spi_nor_remove(struct spi_nor *nor);
671 #endif
672
673 #endif
674