1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Special driver to handle of-platdata
4 *
5 * Copyright 2019 Google LLC
6 *
7 * Some code from coreboot lpss.c
8 */
9
10 #include <dm.h>
11 #include <pci.h>
12 #include <asm/io.h>
13 #include <asm/lpss.h>
14
15 enum {
16 LPSS_RESET_CTL_REG = 0x204,
17
18 /*
19 * Bit 1:0 controls LPSS controller reset.
20 *
21 * 00 ->LPSS Host Controller is in reset (Reset Asserted)
22 * 01/10 ->Reserved
23 * 11 ->LPSS Host Controller is NOT at reset (Reset Released)
24 */
25 LPSS_CNT_RST_RELEASE = 3,
26
27 /* Power management control and status register */
28 PME_CTRL_STATUS = 0x84,
29
30 /* Bit 1:0 Powerstate, controls D0 and D3 state */
31 POWER_STATE_MASK = 3,
32 };
33
34 /* Take controller out of reset */
lpss_reset_release(void * regs)35 void lpss_reset_release(void *regs)
36 {
37 writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG);
38 }
39
lpss_set_power_state(struct udevice * dev,enum lpss_pwr_state state)40 void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state)
41 {
42 dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state);
43 }
44