1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 * 10 */ 11 12#include "skeleton.dtsi" 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/clk/at91.h> 16#include <dt-bindings/dma/at91.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/mfd/at91-usart.h> 19 20/ { 21 model = "Microchip SAMA7G5 family SoC"; 22 compatible = "microchip,sama7g5"; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 interrupt-parent = <&gic>; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0x0>; 35 clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>; 36 clock-names = "cpu", "master", "xtal"; 37 operating-points-v2 = <&cpu_opp_table>; 38 }; 39 }; 40 41 cpu_opp_table: opp-table { 42 compatible = "operating-points-v2"; 43 44 opp-90000000 { 45 opp-hz = /bits/ 64 <90000000>; 46 opp-microvolt = <1050000 1050000 1225000>; 47 clock-latency-ns = <320000>; 48 }; 49 50 opp-250000000 { 51 opp-hz = /bits/ 64 <250000000>; 52 opp-microvolt = <1050000 1050000 1225000>; 53 clock-latency-ns = <320000>; 54 }; 55 56 opp-600000000 { 57 opp-hz = /bits/ 64 <600000000>; 58 opp-microvolt = <1050000 1050000 1225000>; 59 clock-latency-ns = <320000>; 60 opp-suspend; 61 }; 62 63 opp-800000000 { 64 opp-hz = /bits/ 64 <800000000>; 65 opp-microvolt = <1150000 1125000 1225000>; 66 clock-latency-ns = <320000>; 67 }; 68 69 opp-1000000002 { 70 opp-hz = /bits/ 64 <1000000002>; 71 opp-microvolt = <1250000 1225000 1300000>; 72 clock-latency-ns = <320000>; 73 }; 74 }; 75 76 clocks { 77 slow_rc_osc: slow_rc_osc { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <32000>; 81 }; 82 83 main_rc: main_rc { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <12000000>; 87 }; 88 89 slow_xtal: slow_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 }; 93 94 main_xtal: main_xtal { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 }; 98 99 usb_clk: usb_clk { 100 compatible = "fixed-clock"; 101 #clock-cells = <0>; 102 clock-frequency = <48000000>; 103 }; 104 }; 105 106 vddout25: fixed-regulator-vddout25 { 107 compatible = "regulator-fixed"; 108 109 regulator-name = "VDDOUT25"; 110 regulator-min-microvolt = <2500000>; 111 regulator-max-microvolt = <2500000>; 112 regulator-boot-on; 113 status = "disabled"; 114 }; 115 116 ns_sram: sram@100000 { 117 compatible = "mmio-sram"; 118 #address-cells = <1>; 119 #size-cells = <1>; 120 reg = <0x100000 0x20000>; 121 ranges; 122 }; 123 124 soc { 125 compatible = "simple-bus"; 126 #address-cells = <1>; 127 #size-cells = <1>; 128 ranges; 129 130 nfc_sram: sram@600000 { 131 compatible = "mmio-sram"; 132 no-memory-wc; 133 reg = <0x00600000 0x2400>; 134 #address-cells = <1>; 135 #size-cells = <1>; 136 ranges = <0 0x00600000 0x2400>; 137 }; 138 139 nfc_io: nfc-io@10000000 { 140 compatible = "atmel,sama5d3-nfc-io", "syscon"; 141 reg = <0x10000000 0x8000000>; 142 }; 143 144 ebi: ebi@40000000 { 145 compatible = "atmel,sama5d3-ebi"; 146 #address-cells = <2>; 147 #size-cells = <1>; 148 atmel,smc = <&hsmc>; 149 reg = <0x40000000 0x20000000>; 150 ranges = <0x0 0x0 0x40000000 0x8000000 151 0x1 0x0 0x48000000 0x8000000 152 0x2 0x0 0x50000000 0x8000000 153 0x3 0x0 0x58000000 0x8000000>; 154 clocks = <&pmc PMC_TYPE_CORE 23>; /* PMC_MCK1 */ 155 status = "disabled"; 156 157 nand_controller: nand-controller { 158 compatible = "atmel,sama5d3-nand-controller"; 159 atmel,nfc-sram = <&nfc_sram>; 160 atmel,nfc-io = <&nfc_io>; 161 ecc-engine = <&pmecc>; 162 #address-cells = <2>; 163 #size-cells = <1>; 164 ranges; 165 status = "disabled"; 166 }; 167 }; 168 169 securam: securam@e0000000 { 170 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 171 reg = <0xe0000000 0x4000>; 172 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0 0xe0000000 0x4000>; 176 no-memory-wc; 177 }; 178 179 secumod: secumod@e0004000 { 180 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 181 reg = <0xe0004000 0x4000>; 182 gpio-controller; 183 #gpio-cells = <2>; 184 }; 185 186 sfrbu: sfr@e0008000 { 187 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 188 reg = <0xe0008000 0x20>; 189 }; 190 191 pioA: pinctrl@e0014000 { 192 compatible = "microchip,sama7g5-pinctrl"; 193 reg = <0xe0014000 0x800>; 194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-controller; 200 #interrupt-cells = <2>; 201 gpio-controller; 202 #gpio-cells = <2>; 203 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 204 }; 205 206 pmc: pmc@e0018000 { 207 compatible = "microchip,sama7g5-pmc", "syscon"; 208 reg = <0xe0018000 0x200>; 209 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 210 #clock-cells = <2>; 211 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>, <&main_rc>; 212 clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; 213 }; 214 215 reset_controller: reset-controller@e001d000 { 216 compatible = "microchip,sama7g5-rstc"; 217 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; 218 #reset-cells = <1>; 219 clocks = <&clk32k 0>; 220 }; 221 222 shdwc: shdwc@e001d010 { 223 compatible = "microchip,sama7g5-shdwc", "syscon"; 224 reg = <0xe001d010 0x10>; 225 clocks = <&clk32k 0>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 atmel,wakeup-rtc-timer; 229 atmel,wakeup-rtt-timer; 230 status = "disabled"; 231 }; 232 233 rtt: rtc@e001d020 { 234 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 235 reg = <0xe001d020 0x30>; 236 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&clk32k 0>; 238 }; 239 240 clk32k: clock-controller@e001d050 { 241 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 242 reg = <0xe001d050 0x4>; 243 clocks = <&slow_rc_osc>, <&slow_xtal>; 244 #clock-cells = <1>; 245 }; 246 247 gpbr: gpbr@e001d060 { 248 compatible = "microchip,sama7g5-gpbr", "syscon"; 249 reg = <0xe001d060 0x48>; 250 }; 251 252 rtc: rtc@e001d0a8 { 253 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; 254 reg = <0xe001d0a8 0x30>; 255 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&clk32k 1>; 257 }; 258 259 ps_wdt: watchdog@e001d180 { 260 compatible = "microchip,sama7g5-wdt"; 261 reg = <0xe001d180 0x24>; 262 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&clk32k 0>; 264 }; 265 266 chipid@e0020000 { 267 compatible = "microchip,sama7g5-chipid"; 268 reg = <0xe0020000 0x8>; 269 }; 270 271 tcb1: timer@e0800000 { 272 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 reg = <0xe0800000 0x100>; 276 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; 278 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 279 }; 280 281 hsmc: hsmc@e0808000 { 282 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 283 reg = <0xe0808000 0x1000>; 284 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges; 289 290 pmecc: ecc-engine@e0808070 { 291 compatible = "atmel,sama5d2-pmecc"; 292 reg = <0xe0808070 0x490>, 293 <0xe0808500 0x200>; 294 }; 295 }; 296 297 qspi0: spi@e080c000 { 298 compatible = "microchip,sama7g5-ospi"; 299 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; 300 reg-names = "qspi_base", "qspi_mmap"; 301 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 302 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, 303 <&dma0 AT91_XDMAC_DT_PERID(40)>; 304 dma-names = "tx", "rx"; 305 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; 306 clock-names = "pclk", "gclk"; 307 assigned-clocks = <&pmc PMC_TYPE_GCK 78>; 308 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ 309 #address-cells = <1>; 310 #size-cells = <0>; 311 status = "disabled"; 312 }; 313 314 qspi1: spi@e0810000 { 315 compatible = "microchip,sama7g5-qspi"; 316 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; 317 reg-names = "qspi_base", "qspi_mmap"; 318 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 319 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, 320 <&dma0 AT91_XDMAC_DT_PERID(42)>; 321 dma-names = "tx", "rx"; 322 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; 323 clock-names = "pclk", "gclk"; 324 assigned-clocks = <&pmc PMC_TYPE_GCK 79>; 325 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 can0: can@e0828000 { 332 compatible = "bosch,m_can"; 333 reg = <0xe0828000 0x100>, <0x100000 0x7800>; 334 reg-names = "m_can", "message_ram"; 335 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 337 interrupt-names = "int0", "int1"; 338 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 339 clock-names = "hclk", "cclk"; 340 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 341 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ 342 assigned-clock-rates = <40000000>; 343 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 344 status = "disabled"; 345 }; 346 347 can1: can@e082c000 { 348 compatible = "bosch,m_can"; 349 reg = <0xe082c000 0x100>, <0x100000 0xbc00>; 350 reg-names = "m_can", "message_ram"; 351 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 352 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 353 interrupt-names = "int0", "int1"; 354 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 355 clock-names = "hclk", "cclk"; 356 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 357 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ 358 assigned-clock-rates = <40000000>; 359 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 360 status = "disabled"; 361 }; 362 363 can2: can@e0830000 { 364 compatible = "bosch,m_can"; 365 reg = <0xe0830000 0x100>, <0x100000 0x10000>; 366 reg-names = "m_can", "message_ram"; 367 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 369 interrupt-names = "int0", "int1"; 370 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; 371 clock-names = "hclk", "cclk"; 372 assigned-clocks = <&pmc PMC_TYPE_GCK 63>; 373 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ 374 assigned-clock-rates = <40000000>; 375 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 376 status = "disabled"; 377 }; 378 379 can3: can@e0834000 { 380 compatible = "bosch,m_can"; 381 reg = <0xe0834000 0x100>, <0x110000 0x4400>; 382 reg-names = "m_can", "message_ram"; 383 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 384 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 385 interrupt-names = "int0", "int1"; 386 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; 387 clock-names = "hclk", "cclk"; 388 assigned-clocks = <&pmc PMC_TYPE_GCK 64>; 389 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ 390 assigned-clock-rates = <40000000>; 391 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 392 status = "disabled"; 393 }; 394 395 can4: can@e0838000 { 396 compatible = "bosch,m_can"; 397 reg = <0xe0838000 0x100>, <0x110000 0x8800>; 398 reg-names = "m_can", "message_ram"; 399 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 400 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 401 interrupt-names = "int0", "int1"; 402 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; 403 clock-names = "hclk", "cclk"; 404 assigned-clocks = <&pmc PMC_TYPE_GCK 65>; 405 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ 406 assigned-clock-rates = <40000000>; 407 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 408 status = "disabled"; 409 }; 410 411 can5: can@e083c000 { 412 compatible = "bosch,m_can"; 413 reg = <0xe083c000 0x100>, <0x110000 0xcc00>; 414 reg-names = "m_can", "message_ram"; 415 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 416 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-names = "int0", "int1"; 418 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 419 clock-names = "hclk", "cclk"; 420 assigned-clocks = <&pmc PMC_TYPE_GCK 66>; 421 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ 422 assigned-clock-rates = <40000000>; 423 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; 424 status = "disabled"; 425 }; 426 427 adc: adc@e1000000 { 428 compatible = "microchip,sama7g5-adc"; 429 reg = <0xe1000000 0x200>; 430 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&pmc PMC_TYPE_GCK 26>; 432 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 433 assigned-clock-rates = <100000000>; 434 clock-names = "adc_clk"; 435 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; 436 dma-names = "rx"; 437 atmel,min-sample-rate-hz = <200000>; 438 atmel,max-sample-rate-hz = <20000000>; 439 atmel,startup-time-ms = <4>; 440 status = "disabled"; 441 }; 442 443 sdmmc0: mmc@e1204000 { 444 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 445 reg = <0xe1204000 0x4000>; 446 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 448 clock-names = "hclock", "multclk"; 449 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ 450 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 451 assigned-clock-rates = <200000000>; 452 microchip,sdcal-inverted; 453 status = "disabled"; 454 }; 455 456 sdmmc1: mmc@e1208000 { 457 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 458 reg = <0xe1208000 0x4000>; 459 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 461 clock-names = "hclock", "multclk"; 462 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ 463 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 464 assigned-clock-rates = <200000000>; 465 microchip,sdcal-inverted; 466 status = "disabled"; 467 }; 468 469 sdmmc2: mmc@e120c000 { 470 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 471 reg = <0xe120c000 0x4000>; 472 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 474 clock-names = "hclock", "multclk"; 475 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */ 476 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 477 assigned-clock-rates = <200000000>; 478 microchip,sdcal-inverted; 479 status = "disabled"; 480 }; 481 482 pwm: pwm@e1604000 { 483 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 484 reg = <0xe1604000 0x4000>; 485 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 486 #pwm-cells = <3>; 487 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 488 status = "disabled"; 489 }; 490 491 pdmc0: sound@e1608000 { 492 compatible = "microchip,sama7g5-pdmc"; 493 reg = <0xe1608000 0x1000>; 494 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 495 #sound-dai-cells = <0>; 496 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; 497 dma-names = "rx"; 498 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; 499 clock-names = "pclk", "gclk"; 500 status = "disabled"; 501 }; 502 503 pdmc1: sound@e160c000 { 504 compatible = "microchip,sama7g5-pdmc"; 505 reg = <0xe160c000 0x1000>; 506 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 507 #sound-dai-cells = <0>; 508 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; 509 dma-names = "rx"; 510 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; 511 clock-names = "pclk", "gclk"; 512 status = "disabled"; 513 }; 514 515 spdifrx: spdifrx@e1614000 { 516 #sound-dai-cells = <0>; 517 compatible = "microchip,sama7g5-spdifrx"; 518 reg = <0xe1614000 0x4000>; 519 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 520 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 521 dma-names = "rx"; 522 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 523 clock-names = "pclk", "gclk"; 524 status = "disabled"; 525 }; 526 527 spdiftx: spdiftx@e1618000 { 528 #sound-dai-cells = <0>; 529 compatible = "microchip,sama7g5-spdiftx"; 530 reg = <0xe1618000 0x4000>; 531 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 532 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 533 dma-names = "tx"; 534 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 535 clock-names = "pclk", "gclk"; 536 }; 537 538 i2s0: i2s@e161c000 { 539 compatible = "microchip,sama7g5-i2smcc"; 540 #sound-dai-cells = <0>; 541 reg = <0xe161c000 0x4000>; 542 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 543 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 544 dma-names = "tx", "rx"; 545 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 546 clock-names = "pclk", "gclk"; 547 status = "disabled"; 548 }; 549 550 i2s1: i2s@e1620000 { 551 compatible = "microchip,sama7g5-i2smcc"; 552 #sound-dai-cells = <0>; 553 reg = <0xe1620000 0x4000>; 554 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 555 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 556 dma-names = "tx", "rx"; 557 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 558 clock-names = "pclk", "gclk"; 559 status = "disabled"; 560 }; 561 562 eic: interrupt-controller@e1628000 { 563 compatible = "microchip,sama7g5-eic"; 564 reg = <0xe1628000 0xec>; 565 interrupt-parent = <&gic>; 566 interrupt-controller; 567 #interrupt-cells = <2>; 568 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 571 clock-names = "pclk"; 572 status = "disabled"; 573 }; 574 575 pit64b0: timer@e1800000 { 576 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 577 reg = <0xe1800000 0x4000>; 578 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 580 clock-names = "pclk", "gclk"; 581 }; 582 583 pit64b1: timer@e1804000 { 584 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 585 reg = <0xe1804000 0x4000>; 586 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 588 clock-names = "pclk", "gclk"; 589 }; 590 591 aes: crypto@e1810000 { 592 compatible = "atmel,at91sam9g46-aes"; 593 reg = <0xe1810000 0x100>; 594 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 596 clock-names = "aes_clk"; 597 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 598 <&dma0 AT91_XDMAC_DT_PERID(2)>; 599 dma-names = "tx", "rx"; 600 }; 601 602 sha: crypto@e1814000 { 603 compatible = "atmel,at91sam9g46-sha"; 604 reg = <0xe1814000 0x100>; 605 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 607 clock-names = "sha_clk"; 608 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 609 dma-names = "tx"; 610 }; 611 612 flx0: flexcom@e1818000 { 613 compatible = "atmel,sama5d2-flexcom"; 614 reg = <0xe1818000 0x200>; 615 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0x0 0xe1818000 0x800>; 619 status = "disabled"; 620 621 uart0: serial@200 { 622 compatible = "atmel,at91sam9260-usart"; 623 reg = <0x200 0x200>; 624 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 625 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 627 clock-names = "usart"; 628 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 629 <&dma1 AT91_XDMAC_DT_PERID(5)>; 630 dma-names = "tx", "rx"; 631 atmel,use-dma-rx; 632 atmel,use-dma-tx; 633 status = "disabled"; 634 }; 635 }; 636 637 flx1: flexcom@e181c000 { 638 compatible = "atmel,sama5d2-flexcom"; 639 reg = <0xe181c000 0x200>; 640 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 641 #address-cells = <1>; 642 #size-cells = <1>; 643 ranges = <0x0 0xe181c000 0x800>; 644 status = "disabled"; 645 646 i2c1: i2c@600 { 647 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 648 reg = <0x600 0x200>; 649 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 653 atmel,fifo-size = <32>; 654 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 655 <&dma0 AT91_XDMAC_DT_PERID(7)>; 656 dma-names = "tx", "rx"; 657 status = "disabled"; 658 }; 659 }; 660 661 flx3: flexcom@e1824000 { 662 compatible = "atmel,sama5d2-flexcom"; 663 reg = <0xe1824000 0x200>; 664 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 ranges = <0x0 0xe1824000 0x800>; 668 status = "disabled"; 669 670 uart3: serial@200 { 671 compatible = "atmel,at91sam9260-usart"; 672 reg = <0x200 0x200>; 673 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 674 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 676 clock-names = "usart"; 677 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 678 <&dma1 AT91_XDMAC_DT_PERID(11)>; 679 dma-names = "tx", "rx"; 680 atmel,use-dma-rx; 681 atmel,use-dma-tx; 682 status = "disabled"; 683 }; 684 }; 685 686 trng: rng@e2010000 { 687 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 688 reg = <0xe2010000 0x100>; 689 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 691 status = "disabled"; 692 }; 693 694 tdes: crypto@e2014000 { 695 compatible = "atmel,at91sam9g46-tdes"; 696 reg = <0xe2014000 0x100>; 697 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 699 clock-names = "tdes_clk"; 700 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 701 <&dma0 AT91_XDMAC_DT_PERID(53)>; 702 dma-names = "tx", "rx"; 703 }; 704 705 flx4: flexcom@e2018000 { 706 compatible = "atmel,sama5d2-flexcom"; 707 reg = <0xe2018000 0x200>; 708 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 709 #address-cells = <1>; 710 #size-cells = <1>; 711 ranges = <0x0 0xe2018000 0x800>; 712 status = "disabled"; 713 714 uart4: serial@200 { 715 compatible = "atmel,at91sam9260-usart"; 716 reg = <0x200 0x200>; 717 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 718 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 720 clock-names = "usart"; 721 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 722 <&dma1 AT91_XDMAC_DT_PERID(13)>; 723 dma-names = "tx", "rx"; 724 atmel,use-dma-rx; 725 atmel,use-dma-tx; 726 atmel,fifo-size = <16>; 727 status = "disabled"; 728 }; 729 }; 730 731 flx7: flexcom@e2024000 { 732 compatible = "atmel,sama5d2-flexcom"; 733 reg = <0xe2024000 0x200>; 734 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 735 #address-cells = <1>; 736 #size-cells = <1>; 737 ranges = <0x0 0xe2024000 0x800>; 738 status = "disabled"; 739 740 uart7: serial@200 { 741 compatible = "atmel,at91sam9260-usart"; 742 reg = <0x200 0x200>; 743 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 744 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 746 clock-names = "usart"; 747 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 748 <&dma1 AT91_XDMAC_DT_PERID(19)>; 749 dma-names = "tx", "rx"; 750 atmel,use-dma-rx; 751 atmel,use-dma-tx; 752 atmel,fifo-size = <16>; 753 status = "disabled"; 754 }; 755 }; 756 757 gmac0: ethernet@e2800000 { 758 compatible = "cdns,sama7g5-gem"; 759 reg = <0xe2800000 0x1000>; 760 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 761 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 762 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 763 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 764 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 765 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 767 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 768 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 769 assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */ 770 assigned-clock-rates = <125000000>; 771 status = "disabled"; 772 }; 773 774 gmac1: ethernet@e2804000 { 775 compatible = "cdns,sama7g5-emac"; 776 reg = <0xe2804000 0x1000>; 777 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 778 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; 780 clock-names = "pclk", "hclk"; 781 status = "disabled"; 782 }; 783 784 dma0: dma-controller@e2808000 { 785 compatible = "microchip,sama7g5-dma"; 786 reg = <0xe2808000 0x1000>; 787 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 788 #dma-cells = <1>; 789 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 790 clock-names = "dma_clk"; 791 status = "disabled"; 792 }; 793 794 dma1: dma-controller@e280c000 { 795 compatible = "microchip,sama7g5-dma"; 796 reg = <0xe280c000 0x1000>; 797 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 798 #dma-cells = <1>; 799 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 800 clock-names = "dma_clk"; 801 status = "disabled"; 802 }; 803 804 /* Place dma2 here despite it's address */ 805 dma2: dma-controller@e1200000 { 806 compatible = "microchip,sama7g5-dma"; 807 reg = <0xe1200000 0x1000>; 808 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 809 #dma-cells = <1>; 810 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 811 clock-names = "dma_clk"; 812 dma-requests = <0>; 813 status = "disabled"; 814 }; 815 816 tcb0: timer@e2814000 { 817 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 reg = <0xe2814000 0x100>; 821 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; 823 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 824 }; 825 826 flx8: flexcom@e2818000 { 827 compatible = "atmel,sama5d2-flexcom"; 828 reg = <0xe2818000 0x200>; 829 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 830 #address-cells = <1>; 831 #size-cells = <1>; 832 ranges = <0x0 0xe2818000 0x800>; 833 status = "disabled"; 834 835 i2c8: i2c@600 { 836 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 837 reg = <0x600 0x200>; 838 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 842 atmel,fifo-size = <32>; 843 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 844 <&dma0 AT91_XDMAC_DT_PERID(21)>; 845 dma-names = "tx", "rx"; 846 status = "disabled"; 847 }; 848 }; 849 850 flx9: flexcom@e281c000 { 851 compatible = "atmel,sama5d2-flexcom"; 852 reg = <0xe281c000 0x200>; 853 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 854 #address-cells = <1>; 855 #size-cells = <1>; 856 ranges = <0x0 0xe281c000 0x800>; 857 status = "disabled"; 858 859 i2c9: i2c@600 { 860 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 861 reg = <0x600 0x200>; 862 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 866 atmel,fifo-size = <32>; 867 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 868 <&dma0 AT91_XDMAC_DT_PERID(23)>; 869 dma-names = "tx", "rx"; 870 status = "disabled"; 871 }; 872 }; 873 874 flx10: flexcom@e2820000 { 875 compatible = "atmel,sama5d2-flexcom"; 876 reg = <0xe2820000 0x200>; 877 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 878 #address-cells = <1>; 879 #size-cells = <1>; 880 ranges = <0x0 0xe2820000 0x800>; 881 status = "disabled"; 882 883 i2c10: i2c@600 { 884 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 885 reg = <0x600 0x200>; 886 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 890 atmel,fifo-size = <32>; 891 dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, 892 <&dma0 AT91_XDMAC_DT_PERID(25)>; 893 dma-names = "tx", "rx"; 894 status = "disabled"; 895 }; 896 }; 897 898 flx11: flexcom@e2824000 { 899 compatible = "atmel,sama5d2-flexcom"; 900 reg = <0xe2824000 0x200>; 901 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 902 #address-cells = <1>; 903 #size-cells = <1>; 904 ranges = <0x0 0xe2824000 0x800>; 905 status = "disabled"; 906 907 spi11: spi@400 { 908 compatible = "atmel,at91rm9200-spi"; 909 reg = <0x400 0x200>; 910 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 912 clock-names = "spi_clk"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 atmel,fifo-size = <32>; 916 dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, 917 <&dma0 AT91_XDMAC_DT_PERID(27)>; 918 dma-names = "tx", "rx"; 919 status = "disabled"; 920 }; 921 }; 922 923 uddrc: uddrc@e3800000 { 924 compatible = "microchip,sama7g5-uddrc"; 925 reg = <0xe3800000 0x4000>; 926 }; 927 928 ddr3phy: ddr3phy@e3804000 { 929 compatible = "microchip,sama7g5-ddr3phy"; 930 reg = <0xe3804000 0x1000>; 931 }; 932 933 gic: interrupt-controller@e8c11000 { 934 compatible = "arm,cortex-a7-gic"; 935 #interrupt-cells = <3>; 936 #address-cells = <0>; 937 interrupt-controller; 938 reg = <0xe8c11000 0x1000>, 939 <0xe8c12000 0x2000>; 940 }; 941 }; 942}; 943