1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2020-2023 NXP 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #ifndef CONFIG_SDCARD 19 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc 20 #else 21 #define RESET_VECTOR_OFFSET 0x27FFC 22 #define BOOT_PAGE_OFFSET 0x27000 23 24 #ifdef CONFIG_SDCARD 25 #define CFG_RESET_VECTOR_ADDRESS 0x200FFC 26 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) 27 #define CFG_SYS_MMC_U_BOOT_DST 0x00200000 28 #define CFG_SYS_MMC_U_BOOT_START 0x00200000 29 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) 30 #endif 31 32 #endif 33 #endif /* CONFIG_RAMBOOT_PBL */ 34 35 /* High Level Configuration Options */ 36 37 #ifndef CFG_RESET_VECTOR_ADDRESS 38 #define CFG_RESET_VECTOR_ADDRESS 0xeffffffc 39 #endif 40 41 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 42 43 /* 44 * Config the L3 Cache as L3 SRAM 45 */ 46 #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 47 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 48 49 #define CFG_SYS_DCSRBAR 0xf0000000 50 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull 51 52 /* 53 * DDR Setup 54 */ 55 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 56 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE 57 58 /* 59 * IFC Definitions 60 */ 61 #define CFG_SYS_FLASH_BASE 0xe0000000 62 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) 63 64 /* define to use L1 as initial stack */ 65 #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 66 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 67 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 68 /* The assembler doesn't like typecast */ 69 #define CFG_SYS_INIT_RAM_ADDR_PHYS \ 70 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 71 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) 72 #define CFG_SYS_INIT_RAM_SIZE 0x00004000 73 74 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 75 76 /* Serial Port - controlled on board with jumper J8 77 * open - index 2 78 * shorted - index 1 79 */ 80 #if !CONFIG_IS_ENABLED(DM_SERIAL) 81 #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) 82 #endif 83 84 #define CFG_SYS_BAUDRATE_TABLE \ 85 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 86 87 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) 88 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) 89 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) 90 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) 91 92 /* I2C */ 93 94 /* 95 * General PCI 96 * Memory space is mapped 1-1, but I/O space must start from 0. 97 */ 98 99 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 100 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 101 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 102 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 103 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull 104 105 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 106 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 107 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 108 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 109 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull 110 111 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 112 #define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 113 #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 114 115 /* controller 4, Base address 203000 */ 116 #define CFG_SYS_PCIE4_MEM_BUS 0xe0000000 117 #define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 118 119 /* 120 * Miscellaneous configurable options 121 */ 122 123 /* 124 * For booting Linux, the board info and command line data 125 * have to be in the first 64 MB of memory, since this is 126 * the maximum mapped by the Linux kernel during initialization. 127 */ 128 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 129 130 /* 131 * Environment Configuration 132 */ 133 134 #define HVBOOT \ 135 "setenv bootargs config-addr=0x60000000; " \ 136 "bootm 0x01000000 - 0x00f00000" 137 138 /* 139 * DDR Setup 140 */ 141 #define SPD_EEPROM_ADDRESS1 0x52 142 #define SPD_EEPROM_ADDRESS2 0x54 143 #define SPD_EEPROM_ADDRESS3 0x56 144 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 145 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 146 147 /* 148 * IFC Definitions 149 */ 150 #define CFG_SYS_NOR0_CSPR_EXT (0xf) 151 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ 152 + 0x8000000) | \ 153 CSPR_PORT_SIZE_16 | \ 154 CSPR_MSEL_NOR | \ 155 CSPR_V) 156 #define CFG_SYS_NOR1_CSPR_EXT (0xf) 157 #define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ 158 CSPR_PORT_SIZE_16 | \ 159 CSPR_MSEL_NOR | \ 160 CSPR_V) 161 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 162 /* NOR Flash Timing Params */ 163 #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 164 165 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 166 FTIM0_NOR_TEADC(0x5) | \ 167 FTIM0_NOR_TEAHC(0x5)) 168 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 169 FTIM1_NOR_TRAD_NOR(0x1A) |\ 170 FTIM1_NOR_TSEQRAD_NOR(0x13)) 171 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 172 FTIM2_NOR_TCH(0x4) | \ 173 FTIM2_NOR_TWPH(0x0E) | \ 174 FTIM2_NOR_TWP(0x1c)) 175 #define CFG_SYS_NOR_FTIM3 0x0 176 177 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ 178 + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} 179 180 /* NAND Flash on IFC */ 181 #define CFG_SYS_NAND_BASE 0xff800000 182 #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) 183 184 #define CFG_SYS_NAND_CSPR_EXT (0xf) 185 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ 186 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 187 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 188 | CSPR_V) 189 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) 190 191 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 192 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 193 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 194 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 195 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 196 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 197 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 198 199 /* ONFI NAND Flash mode0 Timing Params */ 200 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 201 FTIM0_NAND_TWP(0x18) | \ 202 FTIM0_NAND_TWCHT(0x07) | \ 203 FTIM0_NAND_TWH(0x0a)) 204 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 205 FTIM1_NAND_TWBE(0x39) | \ 206 FTIM1_NAND_TRR(0x0e) | \ 207 FTIM1_NAND_TRP(0x18)) 208 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 209 FTIM2_NAND_TREH(0x0a) | \ 210 FTIM2_NAND_TWHRE(0x1e)) 211 #define CFG_SYS_NAND_FTIM3 0x0 212 213 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 214 215 #if defined(CONFIG_MTD_RAW_NAND) 216 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT 217 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR 218 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK 219 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR 220 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 221 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 222 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 223 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 224 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT 225 #define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR 226 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK 227 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR 228 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 229 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 230 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 231 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 232 #else 233 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT 234 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR 235 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK 236 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR 237 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 238 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 239 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 240 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 241 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT 242 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR 243 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK 244 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR 245 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 246 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 247 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 248 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 249 #endif 250 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT 251 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR 252 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK 253 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR 254 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 255 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 256 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 257 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 258 259 /* CPLD on IFC */ 260 #define CFG_SYS_CPLD_BASE 0xffdf0000 261 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) 262 #define CFG_SYS_CSPR3_EXT (0xf) 263 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ 264 | CSPR_PORT_SIZE_8 \ 265 | CSPR_MSEL_GPCM \ 266 | CSPR_V) 267 268 #define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) 269 #define CFG_SYS_CSOR3 0x0 270 271 /* CPLD Timing parameters for IFC CS3 */ 272 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 273 FTIM0_GPCM_TEADC(0x0e) | \ 274 FTIM0_GPCM_TEAHC(0x0e)) 275 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 276 FTIM1_GPCM_TRAD(0x1f)) 277 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 278 FTIM2_GPCM_TCH(0x8) | \ 279 FTIM2_GPCM_TWP(0x1f)) 280 #define CFG_SYS_CS3_FTIM3 0x0 281 282 /* I2C */ 283 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 284 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 285 286 #define I2C_MUX_CH_DEFAULT 0x8 287 #define I2C_MUX_CH_VOL_MONITOR 0xa 288 #define I2C_MUX_CH_VSC3316_FS 0xc 289 #define I2C_MUX_CH_VSC3316_BS 0xd 290 291 /* Voltage monitor on channel 2*/ 292 #define I2C_VOL_MONITOR_ADDR 0x40 293 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 294 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 295 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 296 297 /* The lowest and highest voltage allowed for T4240RDB */ 298 #define VDD_MV_MIN 819 299 #define VDD_MV_MAX 1212 300 301 /* 302 * eSPI - Enhanced SPI 303 */ 304 305 /* Qman/Bman */ 306 #ifndef CONFIG_NOBQFMAN 307 #define CFG_SYS_BMAN_NUM_PORTALS 50 308 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000 309 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull 310 #define CFG_SYS_BMAN_MEM_SIZE 0x02000000 311 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 312 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 313 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE 314 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 315 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ 316 CFG_SYS_BMAN_CENA_SIZE) 317 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) 318 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 319 #define CFG_SYS_QMAN_NUM_PORTALS 50 320 #define CFG_SYS_QMAN_MEM_BASE 0xf6000000 321 #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull 322 #define CFG_SYS_QMAN_MEM_SIZE 0x02000000 323 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 324 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 325 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ 326 CFG_SYS_QMAN_CENA_SIZE) 327 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) 328 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 329 #endif /* CONFIG_NOBQFMAN */ 330 331 #ifdef CONFIG_SYS_DPAA_FMAN 332 #define SGMII_PHY_ADDR1 0x0 333 #define SGMII_PHY_ADDR2 0x1 334 #define SGMII_PHY_ADDR3 0x2 335 #define SGMII_PHY_ADDR4 0x3 336 #define SGMII_PHY_ADDR5 0x4 337 #define SGMII_PHY_ADDR6 0x5 338 #define SGMII_PHY_ADDR7 0x6 339 #define SGMII_PHY_ADDR8 0x7 340 #define FM1_10GEC1_PHY_ADDR 0x10 341 #define FM1_10GEC2_PHY_ADDR 0x11 342 #define FM2_10GEC1_PHY_ADDR 0x12 343 #define FM2_10GEC2_PHY_ADDR 0x13 344 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 345 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 346 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 347 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 348 #endif 349 350 /* 351 * USB 352 */ 353 354 #ifdef CONFIG_MMC 355 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR 356 #endif 357 358 #define __USB_PHY_TYPE utmi 359 360 /* 361 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 362 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 363 * interleaving. It can be cacheline, page, bank, superbank. 364 * See doc/README.fsl-ddr for details. 365 */ 366 #ifdef CONFIG_ARCH_T4240 367 #define CTRL_INTLV_PREFERED 3way_4KB 368 #else 369 #define CTRL_INTLV_PREFERED cacheline 370 #endif 371 372 #define CFG_EXTRA_ENV_SETTINGS \ 373 "hwconfig=fsl_ddr:" \ 374 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 375 "bank_intlv=auto;" \ 376 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 377 "netdev=eth0\0" \ 378 "uboot=" CONFIG_UBOOTPATH "\0" \ 379 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ 380 "tftpflash=tftpboot $loadaddr $uboot && " \ 381 "protect off $ubootaddr +$filesize && " \ 382 "erase $ubootaddr +$filesize && " \ 383 "cp.b $loadaddr $ubootaddr $filesize && " \ 384 "protect on $ubootaddr +$filesize && " \ 385 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 386 "consoledev=ttyS0\0" \ 387 "ramdiskaddr=2000000\0" \ 388 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 389 "fdtaddr=1e00000\0" \ 390 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 391 "bdev=sda3\0" 392 393 #define HVBOOT \ 394 "setenv bootargs config-addr=0x60000000; " \ 395 "bootm 0x01000000 - 0x00f00000" 396 397 #include <asm/fsl_secure_boot.h> 398 399 #endif /* __CONFIG_H */ 400