1#include <dt-bindings/clock/tegra20-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/pinctrl/pinctrl-tegra.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5 6#include "skeleton.dtsi" 7 8/ { 9 compatible = "nvidia,tegra20"; 10 interrupt-parent = <&lic>; 11 12 host1x@50000000 { 13 compatible = "nvidia,tegra20-host1x", "simple-bus"; 14 reg = <0x50000000 0x00024000>; 15 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 16 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 17 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 18 resets = <&tegra_car 28>; 19 reset-names = "host1x"; 20 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 ranges = <0x54000000 0x54000000 0x04000000>; 25 26 mpe@54040000 { 27 compatible = "nvidia,tegra20-mpe"; 28 reg = <0x54040000 0x00040000>; 29 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 30 clocks = <&tegra_car TEGRA20_CLK_MPE>; 31 resets = <&tegra_car 60>; 32 reset-names = "mpe"; 33 }; 34 35 vi@54080000 { 36 compatible = "nvidia,tegra20-vi"; 37 reg = <0x54080000 0x00040000>; 38 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 39 clocks = <&tegra_car TEGRA20_CLK_VI>; 40 resets = <&tegra_car 20>; 41 reset-names = "vi"; 42 }; 43 44 epp@540c0000 { 45 compatible = "nvidia,tegra20-epp"; 46 reg = <0x540c0000 0x00040000>; 47 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 48 clocks = <&tegra_car TEGRA20_CLK_EPP>; 49 resets = <&tegra_car 19>; 50 reset-names = "epp"; 51 }; 52 53 isp@54100000 { 54 compatible = "nvidia,tegra20-isp"; 55 reg = <0x54100000 0x00040000>; 56 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 57 clocks = <&tegra_car TEGRA20_CLK_ISP>; 58 resets = <&tegra_car 23>; 59 reset-names = "isp"; 60 }; 61 62 gr2d@54140000 { 63 compatible = "nvidia,tegra20-gr2d"; 64 reg = <0x54140000 0x00040000>; 65 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 66 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 67 resets = <&tegra_car 21>; 68 reset-names = "2d"; 69 }; 70 71 gr3d@54180000 { 72 compatible = "nvidia,tegra20-gr3d"; 73 reg = <0x54180000 0x00040000>; 74 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 75 resets = <&tegra_car 24>; 76 reset-names = "3d"; 77 }; 78 79 dc@54200000 { 80 compatible = "nvidia,tegra20-dc"; 81 reg = <0x54200000 0x00040000>; 82 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 84 <&tegra_car TEGRA20_CLK_PLL_P>; 85 clock-names = "dc", "parent"; 86 resets = <&tegra_car 27>; 87 reset-names = "dc"; 88 89 nvidia,head = <0>; 90 91 rgb { 92 status = "disabled"; 93 }; 94 }; 95 96 dc@54240000 { 97 compatible = "nvidia,tegra20-dc"; 98 reg = <0x54240000 0x00040000>; 99 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 101 <&tegra_car TEGRA20_CLK_PLL_P>; 102 clock-names = "dc", "parent"; 103 resets = <&tegra_car 26>; 104 reset-names = "dc"; 105 106 nvidia,head = <1>; 107 108 rgb { 109 status = "disabled"; 110 }; 111 }; 112 113 hdmi@54280000 { 114 compatible = "nvidia,tegra20-hdmi"; 115 reg = <0x54280000 0x00040000>; 116 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 118 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 119 clock-names = "hdmi", "parent"; 120 resets = <&tegra_car 51>; 121 reset-names = "hdmi"; 122 status = "disabled"; 123 }; 124 125 tvo@542c0000 { 126 compatible = "nvidia,tegra20-tvo"; 127 reg = <0x542c0000 0x00040000>; 128 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&tegra_car TEGRA20_CLK_TVO>; 130 status = "disabled"; 131 }; 132 133 dsi@54300000 { 134 compatible = "nvidia,tegra20-dsi"; 135 reg = <0x54300000 0x00040000>; 136 clocks = <&tegra_car TEGRA20_CLK_DSI>; 137 resets = <&tegra_car 48>; 138 reset-names = "dsi"; 139 status = "disabled"; 140 }; 141 }; 142 143 timer@50040600 { 144 compatible = "arm,cortex-a9-twd-timer"; 145 interrupt-parent = <&intc>; 146 reg = <0x50040600 0x20>; 147 interrupts = <GIC_PPI 13 148 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 149 clocks = <&tegra_car TEGRA20_CLK_TWD>; 150 }; 151 152 intc: interrupt-controller@50041000 { 153 compatible = "arm,cortex-a9-gic"; 154 reg = <0x50041000 0x1000 155 0x50040100 0x0100>; 156 interrupt-controller; 157 #interrupt-cells = <3>; 158 interrupt-parent = <&intc>; 159 }; 160 161 cache-controller@50043000 { 162 compatible = "arm,pl310-cache"; 163 reg = <0x50043000 0x1000>; 164 arm,data-latency = <5 5 2>; 165 arm,tag-latency = <4 4 2>; 166 cache-unified; 167 cache-level = <2>; 168 }; 169 170 lic: interrupt-controller@60004000 { 171 compatible = "nvidia,tegra20-ictlr"; 172 reg = <0x60004000 0x100>, 173 <0x60004100 0x50>, 174 <0x60004200 0x50>, 175 <0x60004300 0x50>; 176 interrupt-controller; 177 #interrupt-cells = <3>; 178 interrupt-parent = <&intc>; 179 }; 180 181 timer@60005000 { 182 compatible = "nvidia,tegra20-timer"; 183 reg = <0x60005000 0x60>; 184 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 189 }; 190 191 tegra_car: clock@60006000 { 192 compatible = "nvidia,tegra20-car"; 193 reg = <0x60006000 0x1000>; 194 #clock-cells = <1>; 195 #reset-cells = <1>; 196 }; 197 198 flow-controller@60007000 { 199 compatible = "nvidia,tegra20-flowctrl"; 200 reg = <0x60007000 0x1000>; 201 }; 202 203 apbdma: dma@6000a000 { 204 compatible = "nvidia,tegra20-apbdma"; 205 reg = <0x6000a000 0x1200>; 206 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 223 resets = <&tegra_car 34>; 224 reset-names = "dma"; 225 #dma-cells = <1>; 226 }; 227 228 ahb@6000c000 { 229 compatible = "nvidia,tegra20-ahb"; 230 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ 231 }; 232 233 gpio: gpio@6000d000 { 234 compatible = "nvidia,tegra20-gpio"; 235 reg = <0x6000d000 0x1000>; 236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 243 #gpio-cells = <2>; 244 gpio-controller; 245 #interrupt-cells = <2>; 246 interrupt-controller; 247 /* 248 gpio-ranges = <&pinmux 0 0 224>; 249 */ 250 }; 251 252 /* Audio Bitstream Engine */ 253 bsea@60011000 { 254 compatible = "nvidia,tegra20-bsea"; 255 reg = <0x60011000 0x1000>, <0x4000c000 0x4000>; 256 reg-names = "bsea", "iram-buffer"; 257 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 258 interrupt-names = "bsea"; 259 clocks = <&tegra_car TEGRA20_CLK_BSEA>; 260 resets = <&tegra_car 62>; 261 reset-names = "bsea"; 262 status = "disabled"; 263 }; 264 265 /* Video Bitstream Engine */ 266 bsev@6001b000 { 267 compatible = "nvidia,tegra20-bsev"; 268 reg = <0x6001b000 0x1000>, <0x40008000 0x4000>; 269 reg-names = "bsev", "iram-buffer"; 270 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-names = "bsev"; 272 clocks = <&tegra_car TEGRA20_CLK_BSEV>, 273 <&tegra_car TEGRA20_CLK_VDE>; 274 clock-names = "bsev", "vde"; 275 resets = <&tegra_car 63>, 276 <&tegra_car 61>; 277 reset-names = "bsev", "vde"; 278 status = "disabled"; 279 }; 280 281 apbmisc@70000800 { 282 compatible = "nvidia,tegra20-apbmisc"; 283 reg = <0x70000800 0x64 /* Chip revision */ 284 0x70000008 0x04>; /* Strapping options */ 285 }; 286 287 pinmux: pinmux@70000014 { 288 compatible = "nvidia,tegra20-pinmux"; 289 reg = <0x70000014 0x10 /* Tri-state registers */ 290 0x70000080 0x20 /* Mux registers */ 291 0x700000a0 0x14 /* Pull-up/down registers */ 292 0x70000868 0xa8>; /* Pad control registers */ 293 }; 294 295 das@70000c00 { 296 compatible = "nvidia,tegra20-das"; 297 reg = <0x70000c00 0x80>; 298 }; 299 300 tegra_ac97: ac97@70002000 { 301 compatible = "nvidia,tegra20-ac97"; 302 reg = <0x70002000 0x200>; 303 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA20_CLK_AC97>; 305 resets = <&tegra_car 3>; 306 reset-names = "ac97"; 307 dmas = <&apbdma 12>, <&apbdma 12>; 308 dma-names = "rx", "tx"; 309 status = "disabled"; 310 }; 311 312 tegra_i2s1: i2s@70002800 { 313 compatible = "nvidia,tegra20-i2s"; 314 reg = <0x70002800 0x200>; 315 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 317 resets = <&tegra_car 11>; 318 reset-names = "i2s"; 319 dmas = <&apbdma 2>, <&apbdma 2>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 }; 323 324 tegra_i2s2: i2s@70002a00 { 325 compatible = "nvidia,tegra20-i2s"; 326 reg = <0x70002a00 0x200>; 327 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 329 resets = <&tegra_car 18>; 330 reset-names = "i2s"; 331 dmas = <&apbdma 1>, <&apbdma 1>; 332 dma-names = "rx", "tx"; 333 status = "disabled"; 334 }; 335 336 /* 337 * There are two serial driver i.e. 8250 based simple serial 338 * driver and APB DMA based serial driver for higher baudrate 339 * and performace. To enable the 8250 based driver, the compatible 340 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial 341 * driver, the compatible is "nvidia,tegra20-hsuart". 342 */ 343 uarta: serial@70006000 { 344 compatible = "nvidia,tegra20-uart"; 345 reg = <0x70006000 0x40>; 346 reg-shift = <2>; 347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 349 resets = <&tegra_car 6>; 350 reset-names = "serial"; 351 dmas = <&apbdma 8>, <&apbdma 8>; 352 dma-names = "rx", "tx"; 353 status = "disabled"; 354 }; 355 356 uartb: serial@70006040 { 357 compatible = "nvidia,tegra20-uart"; 358 reg = <0x70006040 0x40>; 359 reg-shift = <2>; 360 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 362 resets = <&tegra_car 7>; 363 reset-names = "serial"; 364 dmas = <&apbdma 9>, <&apbdma 9>; 365 dma-names = "rx", "tx"; 366 status = "disabled"; 367 }; 368 369 uartc: serial@70006200 { 370 compatible = "nvidia,tegra20-uart"; 371 reg = <0x70006200 0x100>; 372 reg-shift = <2>; 373 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 375 resets = <&tegra_car 55>; 376 reset-names = "serial"; 377 dmas = <&apbdma 10>, <&apbdma 10>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 uartd: serial@70006300 { 383 compatible = "nvidia,tegra20-uart"; 384 reg = <0x70006300 0x100>; 385 reg-shift = <2>; 386 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 388 resets = <&tegra_car 65>; 389 reset-names = "serial"; 390 dmas = <&apbdma 19>, <&apbdma 19>; 391 dma-names = "rx", "tx"; 392 status = "disabled"; 393 }; 394 395 uarte: serial@70006400 { 396 compatible = "nvidia,tegra20-uart"; 397 reg = <0x70006400 0x100>; 398 reg-shift = <2>; 399 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 401 resets = <&tegra_car 66>; 402 reset-names = "serial"; 403 dmas = <&apbdma 20>, <&apbdma 20>; 404 dma-names = "rx", "tx"; 405 status = "disabled"; 406 }; 407 408 nand: nand-controller@70008000 { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 compatible = "nvidia,tegra20-nand"; 412 reg = <0x70008000 0x100>; 413 }; 414 415 pwm: pwm@7000a000 { 416 compatible = "nvidia,tegra20-pwm"; 417 reg = <0x7000a000 0x100>; 418 #pwm-cells = <2>; 419 clocks = <&tegra_car TEGRA20_CLK_PWM>; 420 resets = <&tegra_car 17>; 421 reset-names = "pwm"; 422 status = "disabled"; 423 }; 424 425 rtc@7000e000 { 426 compatible = "nvidia,tegra20-rtc"; 427 reg = <0x7000e000 0x100>; 428 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&tegra_car TEGRA20_CLK_RTC>; 430 }; 431 432 i2c@7000c000 { 433 compatible = "nvidia,tegra20-i2c"; 434 reg = <0x7000c000 0x100>; 435 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 clocks = <&tegra_car TEGRA20_CLK_I2C1>, 439 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 440 clock-names = "div-clk", "fast-clk"; 441 resets = <&tegra_car 12>; 442 reset-names = "i2c"; 443 dmas = <&apbdma 21>, <&apbdma 21>; 444 dma-names = "rx", "tx"; 445 status = "disabled"; 446 }; 447 448 spi@7000c380 { 449 compatible = "nvidia,tegra20-sflash"; 450 reg = <0x7000c380 0x80>; 451 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 clocks = <&tegra_car TEGRA20_CLK_SPI>; 455 resets = <&tegra_car 43>; 456 reset-names = "spi"; 457 dmas = <&apbdma 11>, <&apbdma 11>; 458 dma-names = "rx", "tx"; 459 status = "disabled"; 460 }; 461 462 i2c@7000c400 { 463 compatible = "nvidia,tegra20-i2c"; 464 reg = <0x7000c400 0x100>; 465 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 clocks = <&tegra_car TEGRA20_CLK_I2C2>, 469 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 470 clock-names = "div-clk", "fast-clk"; 471 resets = <&tegra_car 54>; 472 reset-names = "i2c"; 473 dmas = <&apbdma 22>, <&apbdma 22>; 474 dma-names = "rx", "tx"; 475 status = "disabled"; 476 }; 477 478 i2c@7000c500 { 479 compatible = "nvidia,tegra20-i2c"; 480 reg = <0x7000c500 0x100>; 481 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 485 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 486 clock-names = "div-clk", "fast-clk"; 487 resets = <&tegra_car 67>; 488 reset-names = "i2c"; 489 dmas = <&apbdma 23>, <&apbdma 23>; 490 dma-names = "rx", "tx"; 491 status = "disabled"; 492 }; 493 494 i2c@7000d000 { 495 compatible = "nvidia,tegra20-i2c-dvc"; 496 reg = <0x7000d000 0x200>; 497 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&tegra_car TEGRA20_CLK_DVC>, 501 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 502 clock-names = "div-clk", "fast-clk"; 503 resets = <&tegra_car 47>; 504 reset-names = "i2c"; 505 dmas = <&apbdma 24>, <&apbdma 24>; 506 dma-names = "rx", "tx"; 507 status = "disabled"; 508 }; 509 510 spi@7000d400 { 511 compatible = "nvidia,tegra20-slink"; 512 reg = <0x7000d400 0x200>; 513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 517 resets = <&tegra_car 41>; 518 reset-names = "spi"; 519 dmas = <&apbdma 15>, <&apbdma 15>; 520 dma-names = "rx", "tx"; 521 status = "disabled"; 522 }; 523 524 spi@7000d600 { 525 compatible = "nvidia,tegra20-slink"; 526 reg = <0x7000d600 0x200>; 527 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 531 resets = <&tegra_car 44>; 532 reset-names = "spi"; 533 dmas = <&apbdma 16>, <&apbdma 16>; 534 dma-names = "rx", "tx"; 535 status = "disabled"; 536 }; 537 538 spi@7000d800 { 539 compatible = "nvidia,tegra20-slink"; 540 reg = <0x7000d800 0x200>; 541 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 545 resets = <&tegra_car 46>; 546 reset-names = "spi"; 547 dmas = <&apbdma 17>, <&apbdma 17>; 548 dma-names = "rx", "tx"; 549 status = "disabled"; 550 }; 551 552 spi@7000da00 { 553 compatible = "nvidia,tegra20-slink"; 554 reg = <0x7000da00 0x200>; 555 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 559 resets = <&tegra_car 68>; 560 reset-names = "spi"; 561 dmas = <&apbdma 18>, <&apbdma 18>; 562 dma-names = "rx", "tx"; 563 status = "disabled"; 564 }; 565 566 kbc@7000e200 { 567 compatible = "nvidia,tegra20-kbc"; 568 reg = <0x7000e200 0x100>; 569 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&tegra_car TEGRA20_CLK_KBC>; 571 resets = <&tegra_car 36>; 572 reset-names = "kbc"; 573 status = "disabled"; 574 }; 575 576 pmc@7000e400 { 577 compatible = "nvidia,tegra20-pmc"; 578 reg = <0x7000e400 0x400>; 579 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 580 clock-names = "pclk", "clk32k_in"; 581 }; 582 583 memory-controller@7000f000 { 584 compatible = "nvidia,tegra20-mc"; 585 reg = <0x7000f000 0x024 586 0x7000f03c 0x3c4>; 587 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 588 }; 589 590 iommu@7000f024 { 591 compatible = "nvidia,tegra20-gart"; 592 reg = <0x7000f024 0x00000018 /* controller registers */ 593 0x58000000 0x02000000>; /* GART aperture */ 594 }; 595 596 memory-controller@7000f400 { 597 compatible = "nvidia,tegra20-emc"; 598 reg = <0x7000f400 0x200>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 }; 602 603 fuse@7000f800 { 604 compatible = "nvidia,tegra20-efuse"; 605 reg = <0x7000f800 0x400>; 606 clocks = <&tegra_car TEGRA20_CLK_FUSE>; 607 clock-names = "fuse"; 608 resets = <&tegra_car 39>; 609 reset-names = "fuse"; 610 }; 611 612 pcie@80003000 { 613 compatible = "nvidia,tegra20-pcie"; 614 device_type = "pci"; 615 reg = <0x80003000 0x00000800 /* PADS registers */ 616 0x80003800 0x00000200 /* AFI registers */ 617 0x90000000 0x10000000>; /* configuration space */ 618 reg-names = "pads", "afi", "cs"; 619 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 620 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 621 interrupt-names = "intr", "msi"; 622 623 #interrupt-cells = <1>; 624 interrupt-map-mask = <0 0 0 0>; 625 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 626 627 bus-range = <0x00 0xff>; 628 #address-cells = <3>; 629 #size-cells = <2>; 630 631 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 632 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 633 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 634 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ 635 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 636 637 clocks = <&tegra_car TEGRA20_CLK_PEX>, 638 <&tegra_car TEGRA20_CLK_AFI>, 639 <&tegra_car TEGRA20_CLK_PLL_E>; 640 clock-names = "pex", "afi", "pll_e"; 641 resets = <&tegra_car 70>, 642 <&tegra_car 72>, 643 <&tegra_car 74>; 644 reset-names = "pex", "afi", "pcie_x"; 645 status = "disabled"; 646 647 pci@1,0 { 648 device_type = "pci"; 649 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 650 reg = <0x000800 0 0 0 0>; 651 status = "disabled"; 652 653 #address-cells = <3>; 654 #size-cells = <2>; 655 ranges; 656 657 nvidia,num-lanes = <2>; 658 }; 659 660 pci@2,0 { 661 device_type = "pci"; 662 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 663 reg = <0x001000 0 0 0 0>; 664 status = "disabled"; 665 666 #address-cells = <3>; 667 #size-cells = <2>; 668 ranges; 669 670 nvidia,num-lanes = <2>; 671 }; 672 }; 673 674 usb@c5000000 { 675 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 676 reg = <0xc5000000 0x4000>; 677 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 678 phy_type = "utmi"; 679 nvidia,has-legacy-mode; 680 clocks = <&tegra_car TEGRA20_CLK_USBD>; 681 resets = <&tegra_car 22>; 682 reset-names = "usb"; 683 nvidia,needs-double-reset; 684 nvidia,phy = <&phy1>; 685 status = "disabled"; 686 }; 687 688 phy1: usb-phy@c5000000 { 689 compatible = "nvidia,tegra20-usb-phy"; 690 reg = <0xc5000000 0x4000 0xc5000000 0x4000>; 691 phy_type = "utmi"; 692 clocks = <&tegra_car TEGRA20_CLK_USBD>, 693 <&tegra_car TEGRA20_CLK_PLL_U>, 694 <&tegra_car TEGRA20_CLK_CLK_M>, 695 <&tegra_car TEGRA20_CLK_USBD>; 696 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 697 resets = <&tegra_car 22>, <&tegra_car 22>; 698 reset-names = "usb", "utmi-pads"; 699 nvidia,has-legacy-mode; 700 nvidia,hssync-start-delay = <9>; 701 nvidia,idle-wait-delay = <17>; 702 nvidia,elastic-limit = <16>; 703 nvidia,term-range-adj = <6>; 704 nvidia,xcvr-setup = <9>; 705 nvidia,xcvr-lsfslew = <1>; 706 nvidia,xcvr-lsrslew = <1>; 707 nvidia,has-utmi-pad-registers; 708 status = "disabled"; 709 }; 710 711 usb@c5004000 { 712 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 713 reg = <0xc5004000 0x4000>; 714 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 715 phy_type = "ulpi"; 716 clocks = <&tegra_car TEGRA20_CLK_USB2>; 717 resets = <&tegra_car 58>; 718 reset-names = "usb"; 719 nvidia,phy = <&phy2>; 720 status = "disabled"; 721 }; 722 723 phy2: usb-phy@c5004000 { 724 compatible = "nvidia,tegra20-usb-phy"; 725 reg = <0xc5004000 0x4000>; 726 phy_type = "ulpi"; 727 clocks = <&tegra_car TEGRA20_CLK_USB2>, 728 <&tegra_car TEGRA20_CLK_PLL_U>, 729 <&tegra_car TEGRA20_CLK_CDEV2>; 730 clock-names = "reg", "pll_u", "ulpi-link"; 731 resets = <&tegra_car 58>, <&tegra_car 22>; 732 reset-names = "usb", "utmi-pads"; 733 status = "disabled"; 734 }; 735 736 usb@c5008000 { 737 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 738 reg = <0xc5008000 0x4000>; 739 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 740 phy_type = "utmi"; 741 clocks = <&tegra_car TEGRA20_CLK_USB3>; 742 resets = <&tegra_car 59>; 743 reset-names = "usb"; 744 nvidia,phy = <&phy3>; 745 status = "disabled"; 746 }; 747 748 phy3: usb-phy@c5008000 { 749 compatible = "nvidia,tegra20-usb-phy"; 750 reg = <0xc5008000 0x4000 0xc5000000 0x4000>; 751 phy_type = "utmi"; 752 clocks = <&tegra_car TEGRA20_CLK_USB3>, 753 <&tegra_car TEGRA20_CLK_PLL_U>, 754 <&tegra_car TEGRA20_CLK_CLK_M>, 755 <&tegra_car TEGRA20_CLK_USBD>; 756 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 757 resets = <&tegra_car 59>, <&tegra_car 22>; 758 reset-names = "usb", "utmi-pads"; 759 nvidia,hssync-start-delay = <9>; 760 nvidia,idle-wait-delay = <17>; 761 nvidia,elastic-limit = <16>; 762 nvidia,term-range-adj = <6>; 763 nvidia,xcvr-setup = <9>; 764 nvidia,xcvr-lsfslew = <2>; 765 nvidia,xcvr-lsrslew = <2>; 766 status = "disabled"; 767 }; 768 769 sdhci@c8000000 { 770 compatible = "nvidia,tegra20-sdhci"; 771 reg = <0xc8000000 0x200>; 772 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 774 resets = <&tegra_car 14>; 775 reset-names = "sdhci"; 776 status = "disabled"; 777 }; 778 779 sdhci@c8000200 { 780 compatible = "nvidia,tegra20-sdhci"; 781 reg = <0xc8000200 0x200>; 782 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 784 resets = <&tegra_car 9>; 785 reset-names = "sdhci"; 786 status = "disabled"; 787 }; 788 789 sdhci@c8000400 { 790 compatible = "nvidia,tegra20-sdhci"; 791 reg = <0xc8000400 0x200>; 792 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 794 resets = <&tegra_car 69>; 795 reset-names = "sdhci"; 796 status = "disabled"; 797 }; 798 799 sdhci@c8000600 { 800 compatible = "nvidia,tegra20-sdhci"; 801 reg = <0xc8000600 0x200>; 802 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 804 resets = <&tegra_car 15>; 805 reset-names = "sdhci"; 806 status = "disabled"; 807 }; 808 809 cpus { 810 #address-cells = <1>; 811 #size-cells = <0>; 812 813 cpu@0 { 814 device_type = "cpu"; 815 compatible = "arm,cortex-a9"; 816 reg = <0>; 817 }; 818 819 cpu@1 { 820 device_type = "cpu"; 821 compatible = "arm,cortex-a9"; 822 reg = <1>; 823 }; 824 }; 825 826 pmu { 827 compatible = "arm,cortex-a9-pmu"; 828 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 830 }; 831}; 832